JPS596541B2 - clock regenerator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock regeneration device that extracts and regenerates a clock signal as a timing pulse necessary for identifying, reproducing, demodulating, etc. a received digital signal in a repeater or receiving terminal station of a digital transmission system. It is something.

In digital transmission systems, when extracting clock pulses from a received digital signal sequence, the extracted clock pulses may fluctuate due to changes in the signal pattern.

If there is a deviation from the correct identification point of the clock pulse based on this signal pattern change, that is, a large amount of jitter, not only will the bit error rate worsen, but also phase modulation noise will be added to the demodulated signal at the receiving end station due to jitter addition due to multiple relays. occurs. Therefore, pattern jitter due to particularly strong additive signal pattern changes must be sufficiently suppressed. Generally, in a conventional dot playback device, a digital signal arriving at an input terminal 1 is supplied to a dot extraction circuit 2, as shown in FIG. Depending on the state of the input digital signal, the pulse extraction circuit 2 uses, for example, an envelope detection method in the carrier band, and a nonlinear extraction method such as a full-wave rectification method or a differential method in the baseband band. Pattern jitter phase noise and thermal noise components included in the output of the clock extraction circuit 2 are removed by a narrow band filter 3 such as a tank circuit or a phase synchronization circuit, and the output of the narrow band filter 3 becomes a clock signal and is sent to an output terminal 4. will be sent to. Here, the operation of a conventional device using a phase locked circuit as the narrowband filter 3 will be described in detail with reference to FIGS. 2 and 3.

The output of the head knock extraction circuit 2 is supplied to a tuning amplifier circuit 5 that suppresses pattern jitter and amplifies the signal, and the amplified output is given a constant amplitude by an emitter 6 and then sent to a phase comparator 7.
supplied to In the phase comparator T, the output of the voltage controlled oscillator 9 is phase-compared with the output of the transmitter 6, and the comparison output is supplied to the voltage controlled oscillator 9 as a control signal through the loop filter 8. Phase comparator 7, loop filter 8
, voltage controlled oscillator 9 constitute a phase locked loop. When extracting a clock component from a multilevel or narrowband digital signal, the periodicity of the extracted clock is
The pattern of the digital signal causes a phase shift,
Depending on the disturbance or pattern, a clock component may not be generated, which causes pattern jitter.

Therefore, the former case will be explained in detail below using FIG. 3. FIG. 3A is a simplified eye pattern of a band-limited digital signal with a multilevel number of 4. When this digital signal is supplied to a clock extraction circuit 2 using, for example, a full-wave rectification method, the output of the clock extraction circuit 2 is
As shown in FIG. B, the lock extraction output can be obtained as a solid line, a broken line, or a chain line depending on the pattern of the digital signal. When the lock extraction output as shown in Fig. 3B is supplied to the tuned amplifier circuit 5 and limiter 6, the output is shown in Fig. 3C.
As shown in FIG. 3, outputs of a solid line, a broken line, and a dashed-dotted line are obtained in response to the solid line, broken line, and dashed-dotted line in FIG.
In this example, the output signal phase of the limiter 6 is determined by continuously changing the value between the average phase of the signal θ and the dashed line with a phase shift of −Δθ1, or the dashed line with a phase shift of +Δθ2 of θl, according to the pattern. Take it. Therefore, the output of the voltage controlled oscillator 9 in FIG. 2, ie, the clock signal, is θ. If the phase is θ, the output of the phase comparator 7 in the same figure is θ
1θ. , θi−△θ, one θ. Or θi+△θ2−θ
. Therefore, the original desired output θ1θo
There are different phases. That is, the clock signal includes pattern jitter components due to Δθ1 and Δθ2. SUMMARY OF THE INVENTION An object of the present invention is to provide a clock extraction device that can suppress pattern jitter more than the conventional clock extraction device.

According to this invention, a clock is extracted from a received digital signal by a first clock extraction circuit, and the received digital signal is regenerated by an identification regenerator using the regenerated clock signal, and the regenerated signal is used to generate a clock in the digital signal generation circuit. A local digital signal identical to the digital signal is generated, and a clock is extracted from the local digital signal by a second clock extraction circuit having at least the same phase characteristics as the first clock extraction circuit. The phase of the output clock of the take-out circuit is compared by a phase comparator, and the comparison output is passed through a loop filter to control a voltage controlled oscillator to obtain the above-mentioned regenerated clock signal from the oscillator output.

During the phase comparison, the pattern jitters in the two clocks cancel each other out, eliminating pattern effects. FIG. 4 shows an embodiment in which the present invention is applied to baseband four-value digital signal input.

The baseband 4-level digital signal arriving at the input terminal 1 is branched into two branches, one of which is supplied to the discriminator 10 and the other to the first clock extraction circuit 16 through the delay circuit 17.
This first clock extracting circuit 16 can be a conventional one, and is constituted by, for example, a clock extracting circuit 2, a tuned amplifier circuit 5, and a limiter 6, similar to the one shown in FIG. On the other hand, in the discriminator 10, the received digital signal is identified and reproduced by the reproduced clock signal of the voltage controlled oscillator 9, and the reproduced two series binary digital signals are output to the output terminal 18.
, 19. In the present invention, the reproduction signal of the discriminator 10 is generated in a digital signal generation circuit 21 into a local digital signal that is the same as the digital signal received at the input terminal 1.

In this example, the reproduced output of the discriminator 10 is output from the binary-quaternary converter 1.
4 is converted into a 4-value digital signal, and the 4-value digital signal is passed through a transmission filter 14 that has the same characteristics as the baseband 4-value signal that has passed through the input terminal 1.
A local digital signal is obtained. This local digital signal is supplied to a second clock extraction circuit 22 which has at least the same phase characteristics as the first clock extraction circuit 16. In this example, the second clock extraction circuit 22 is composed of a clock extraction circuit 2, a tuned amplifier circuit 5, and a limiter 6. The clocks taken out from the first clock extraction circuit 16 and the second clock extraction circuit 22 are equivalent, and are applied to the input terminals 12 and 13 of the phase comparator 7.

The phases of the human input signals at input terminals 12 and 13 are matched by a delay circuit 17. Since these clocks simultaneously contain either △θ1 or △θ2 due to the pattern, the two inputs of the phase comparator 7 are θl - △θ1 and θ
o−△θ1 or θl+△θ2 and θ. It becomes +△θ2. Therefore, the output of the phase comparator 7 is -△θ1 or △θ2
The output of the phase comparator 7 controls the voltage controlled oscillator 9 through the loop filter 8 so that the phase error is canceled out and only the original desired phase error θi - θo is left. In this way, the phase jitter component of the clock signal caused by the signal pattern is suppressed. As explained above, according to the clock reproducing apparatus of the present invention, pattern jitter of the clock signal based on the pattern of the input digital signal can be suppressed.

Since pattern jitter increases in proportion to the narrow band or multi-value spectrum shaping, the present invention is particularly effective as a clock regeneration device in a high-efficiency digital transmission system that is characterized by multi-value or narrow band. . When the present invention is applied to clock reproduction of a multi-value digital signal, the binary-to-four-value converter 14 in FIG. 4 is replaced with a binary-to-multi-value converter. Further, by inserting a demodulator and a modulator before and after the discriminator 10 shown in the figure, the present invention can be applied to a carrier signal containing clock information with a similar configuration. Clock extraction circuits 16, 22 may be of other types. Depending on the phase comparator 7 used, if there is a difference in the amplitude of its input, an error may occur; in that case, the clock extraction circuit 16
, 22 also have the same amplitude characteristics.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the general configuration of a conventional clock regeneration device, and FIG. 2 is a block diagram showing a conventional clock regeneration device using a phase synchronization circuit as a narrow band filter.
FIG. 3 is a diagram illustrating how pattern jitter occurs depending on the signal pattern, and FIG. 4 is a block diagram showing an embodiment in which the clock reproducing apparatus according to the present invention is applied to a baseband four-value digital signal. 1: Input terminal, 2: Clock extraction circuit, 3: Narrowband filter, 4: Clock output terminal, 5: Tuned amplifier circuit, 6:
Limiter, 7: Phase comparator, 8: Loop filter, 9:
Voltage controlled oscillator, 10: Discriminator, 17: Delay circuit, 12
, 13° Input terminal of phase comparator 7, 14: Binary-to-four-value converter, 15: Transmission system filter, 16, 22: Clock extraction circuit, 18, 19: Regenerated digital signal output terminal, 2
1: Digital signal generation circuit.

Claims (1)

[Claims] 1. A first clock extracting circuit for extracting a clock from a received digital signal, a discriminator for discriminating and reproducing the received digital signal using a regenerated clock signal, and a local digital signal identical to the received digital signal by the reproduced output from the discriminator. a digital signal generation circuit for generating a signal; a second clock extraction circuit having at least the same phase characteristics as the first clock extraction circuit for extracting a clock from the local digital signal; and the first clock extraction circuit and the second clock extraction circuit. a phase comparator that detects the phase difference between both outputs of the circuit; a loop filter that is supplied with the output of the phase comparator and obtains an average phase error signal; and a loop filter that is controlled by the average phase error signal and outputs the regenerated clock signal. A clock regeneration device comprising a voltage controlled oscillator.