JPS5969828A - Input device of key matrix - Google Patents

Abstract

PURPOSE:To recognize key switches more than the ordinary ones by constituting the key switches by a signal line connected to an electric circuit to be used for both input and output and other signal lines. CONSTITUTION:When a key switch K7 is turned on, I/O signal lines p0, p1 are connected. When a high level signal is outputted from the I/O signal line p0, a current flows into the I/O signal line p1 through the k7 and the signal line p1 is turned to the high level, so that a gate 32a is turned to the high level and gates 38, 39 are also turned to the high level. Since gates 36, 37 are at the low level always, gates 38, 39 have the same state as Q' outputs of FFs 18, 19. When the gate 33 is turned to the high level, a gate 40 finds out OR of the output of the gate 33 and an inversion signal of a reference clock to obtain a data latching pulse. At the rise of a gate 40, the outputs of the gates 34, 35, 38, 39 are written in FFs 27-30 and outputted to output terminals r0-r3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a key matrix input device used in various electronic devices including microcomputers. Input devices are mainly used in electronic devices having multiple keys, such as microcomputers, and identify which key is pressed.

As with other parts, it is desired that the key matrix input device be made smaller and more multifunctional. First, a conventional key matrix input device will be explained with reference to the drawings.

Figure 1 shows a conventional electrical connection of an IJ input device, which can connect 15 to 4x4-16 key switches KO~ by four output signal lines DToNDT3 and four input signal lines KYoNKY3. It is a diagram. and the second
The figure is an equivalent circuit diagram of 16 key switches KO~. The decoder 1 converts the ON information of the key matrix into a binary number and outputs it as 4-bit data from the terminals D○ to D3.

A flowchart of the case where the decoder function is performed by software is shown in FIG. 3. Now, the operation when the key switch 7 is on will be explained according to the flowchart. First, at the branch (7) in FIG. 2, the output signal line DT○ is connected to the output signal line DT○ (hereinafter referred to as H), and the output signal line DT1, DT2 . Set DT3 to low (hereinafter referred to as "L") and check input signals 1%lKY○ to KY30. In this case, if the key switch KO~ is set to 3, it is assumed that there is no input, and the process proceeds to the next branch (a). Next, set the output signal line DT1 to H, the output signal, $51DTo, DT2
, DT3 to L KL, and check the inputs of the input signal lines KYO to KY3.

Here, since the key switch 7 is on, H is input from the input signal line KY3. Therefore, "with input"
and proceed to the next process. In addition, in the case of "no input", branch (2), proceed to (0) Since there was an input from the human power signal line KY3, it is set as DATA1-3 in process (2). Next, process (
Since it was an input to DTl in 2), DATA2=
Set it to 4. Then, in processing (a), DATA1 and DATA2
(DATAI+DATA2=3+4=7) and outputs 7 data (0111 in binary). After that, return to the key human power check again.

FIG. 4 is an electrical wiring diagram showing a conventional example of a logic circuit with a decoder function. When the basic clock is inputted from the clock input CK, the frequency is divided by the flip-flop 2.3, and the output signal is output by the AND gates 4 to 7, 1DTo-D,
Get key scan signal of T4 0 Now, 7 on key switch
If the switch is on, the circuit 8 shown by the broken line is connected, and the output of the output signal line DT1 is input from the input signal line KY3. The presence or absence of the durability signal is obtained from the OR gate 9. (or game) 10.11 obtains the lower two bits of data, and the upper two bits are obtained directly from flip-flops 2 and 3.

The AND gate 12 outputs a data sampling pulse, and the data latch flip-flops 13-16 hold 4-bit data and output it to terminals D○-D3.

Generally, a chattering prevention circuit, a data sample completion signal output circuit, etc. are added to the circuit shown in FIG. 4 and used.

FIG. 5 shows the timing chart of FIG.

Before the time t when key switch 7 is turned on, flip-flops 13 to 16 hold the data of the key switch that was turned on before that time.

Many of the input devices mentioned above are housed in integrated circuits.The degree of integration of integrated circuits has increased due to advances in microfabrication technology, but on the other hand, the pad size has not become smaller due to the physical and mechanical constraints of wire bonding. Therefore, in integrated circuits with a large number of terminals, there is a problem that the chip size cannot be reduced.

OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention provides a key matrix input device that can realize almost the same functions as the conventional example with a reduced number of terminals and can reduce the cost of integrated circuits (hereinafter referred to as IC).

Structure of the Invention In order to achieve the above object, the present invention is such that a signal line connected to an electric circuit for both input and output functions constitutes a key switch with other signal lines.

A signal line connected to an electric circuit that also serves as input and output is another signal line that is connected to an electric circuit that also serves as input and output.

A key switch can be configured with either a signal line connected to an electric circuit with only input functions or a signal line connected with an electric circuit with only output function. Many key switches can be configured. As a result, the IC can be integrated and miniaturized, and costs can also be reduced.

DESCRIPTION OF EMBODIMENTS A key matrix input device according to an embodiment of the present invention will be described below.

FIG. 6 is an electrical wiring diagram of a key matrix input device in an embodiment of the present invention that uses six terminals to obtain 15 types of key input. 0 of the decoder 17 is an output signal line connected to an electric circuit with an output function, po-ps is an input/output signal line connected to an electric circuit with an input/output function, and q is an input/output signal line connected to an electric circuit with an input function. This is the connected input signal line. Convert 15 types of key input into binary numbers, and output the numbers 0000"~111o" to output terminals ro, r1, r2. Output r3.

FIG. 7 shows a flowchart when the decoder 17 is applied to a microcomputer or the like using software.

Processing (→) Outputs "H" from terminal 0 and puts input/output signal lines p○ to p3 in the input state. At the next branch ■, if there is an input of ``H'' from the people signal lines p○ to p3 and the input signal line q, it is assumed that one of the above key switches is on, and the ``input switch'' is turned on. branch to
If there is no input, proceed to the next process (k)'. In processing (b), H is output from input/output signal line p○, output signal line 0 is L, input/output signal line p1. By setting p2+p3 to the input state, 4. 5. 6°K7
You can check whether it is on or off. At branch (b), input/output signal line p1. p2. Depending on the presence or absence of input from p3 and input signal line q, if there is an input, the process branches to a (go to a, otherwise to process). Output signal line 0 and input/output signal Hp○ are set to L, and input/output signal line p1 outputs H. Input/output signal line p
2, p3 is in the input state, and the key switch is 8. 9. You can check whether 10 is on or off. At branch (g), the output of the input/output signal line p1 is connected to the input/output signal line p2. p3, depending on whether it is input from the input signal 11aq, if there is an input, it will be processed (→, otherwise it will branch to processing (S). Output signal line.
Set the input/output signal lines p○ and p1 to L“, and connect the input/output signal line p
2, outputs n.The input/output signal line p3 is in the input state, and it is checked whether the 12°K13 is on or off at the key switch depending on the presence or absence of input from the input/output signal line p3 and the input signal line q. If there is an input at branch ((to), go to processing (→), otherwise go to processing (G). Set output signal line 0, input/output signal line po, p1.p2 to "L" and input/output signal line p3. “
Outputs "H". Check whether 14 is on or off in the key switch depending on the presence or absence of input from input signal line q. Branch (If there is an input, go to processing (G), otherwise all keys are turned off. Assuming that it is off, the process returns to process (to). At branch (g), if the input is from the input/output signal mp○, it is assumed that 11 is on, and the process returns to process (2); otherwise, process (
Proceed to ). When entering the process (G), only 14 switches are on, so the process proceeds to the output process to the terminals ro to r3 with the data 14. When we go to process (a), the number of switches that are on is limited to 11, so we proceed to process (a) with the data 11.

The flow of processing (→, (N), (G)) is the same as in the conventional example.

Finally, after going through the process of outputting the data obtained from the terminal r O% r 3, return to the start process (→
Start again. Now, I will explain the flow when the key switch 7 is turned on. If 7 is on in the key switch, there is an input from the input/output signal line p1 when H is output from the input/output signal line po, and the flowchart progresses from the start to the branch (b), and here, It branches to processing (b) as "input foot". Processing (:→ input/output signal 1p.

Since this is an input to the input terminal, DATA1=4.

processing), the input is from the input/output signal line p1, so
DATA2=3. processing), DATA=4+3
= 7, and in processing), the data 7 is sent to terminal I○~
Output from r3.

FIG. 8 shows an embodiment in which the decoder 17 in FIG. 6 is implemented as a logic circuit, and FIG. 9 is a timing chart thereof. When a basic clock is input from the clock input GK, a hexadecimal counter consisting of flip 70 tabs 18 to 2o and an AND gate 21 is activated, and AND gates 22 to 26 generate a five-phase scanning signal.

The circuits shown in FIGS. 10 and 11 are used for the output stages 32a and 32A so that they can also be used as input terminals. Here, when the transistors 22a, 22A are turned on, they output "H" for the output Y. The transistors 22a, 22
When A is off, terminals 22c, 2 are in resistance.
When there is an H input from 2G, current flows through the resistors 22b and 22B, the terminal voltage becomes H level, and the input of the gate connected to that terminal becomes H level. The explanation will be given below with reference to the timing chart of FIG. Time t.

From tl to tl, all key switches KO to 14 are off, five-phase scanning signals are sequentially output, and the previous data remains in seven lip-flops 27 to 3o for data latching. When the key switch 7 is turned on at time t1,
Input/output signal lines po and pl as shown in broken line 31 shown in FIG.
becomes conductive.

When H is output from the input/output signal line po, current flows into the input/output signal line p1 through the key switch 7 and becomes H, so the AND gate 32a becomes H, and in response, the OR gates 33 to 35 also become H. 0 At this time, AND gates 36 and 37 are always L, so it becomes H (or game) 38.3
9 is the same as the d output of flip 70 tube 18.19.

When the OR gate 33 becomes H, the AND gate 40 performs a logical sum with the inverted signal of the basic clock to obtain a pulse for data latch. Therefore and gate 40
At the rising edge of the output terminal r
o, r1゜r2. 7 outputs each to r3. When the scanning signal H is output from the input/output signal line p1, the input/output signal line po becomes H.
However, since the AND gate 22 is at L, the AND gate 23 also remains at L, and the entire circuit operates in the same way as when the key switch is off. At time t2, when the key switch 7 is turned off υ and the key switch 14 is turned on, the input/output signal line p3 and the input signal line q are brought into conduction as shown by broken m41 in FIG. When the scanning signal is output from the input/output signal line p3, a current flows to the terminal q of the key switch via 14 and becomes H. At this time, G37'
Moor gate 38, 39° 34 becomes H. At the same time, the OR gate 33 also becomes H due to the H input of the input signal line q, and the outputs of the OR gates 34, 35, 38. ro.

Output to rl, 'r2, and r3, respectively. At time t3, all the key switches are turned off, but the flip-flops 27 to 30 and the output terminals ro, r1, r2 and r3 are in the state of data corresponding to key switch 14.

In addition, compared to the conventional key matrix input device, the key matrix input device of the present invention has fewer signal lines when recognizing the same number of key switches, so the wiring of the key matrix input device can be wired using a printed wiring board, etc. If you do this, you will also have the advantage of being able to wire with fewer jumpers.

Effects of the Invention As described above, the present invention allows many key switches to be recognized through a plurality of signal lines, and is effective in integration and miniaturization.

[Brief explanation of the drawing]

Figure 1 is an electrical wiring diagram of a conventional key matrix input device, Figure 2 is an equivalent circuit diagram of a key switch, and Figure 3 is a flowchart when a microcomputer is used in the decoder section of the same key matrix input device. , FIG. 4 is an electrical connection diagram when a logic circuit is used in the decoder section of the key matrix input device, FIG. 5 is a waveform diagram showing the timing of the logic circuit in FIG. 4, and FIG. An electrical wiring diagram of the key matrix input device in one embodiment, FIG. 7 is a flowchart when a microcomputer is used in the decoder section of the key matrix input device, and FIG. 8 is a logic diagram for the decoder section of the key matrix input device. Figure 9 is a waveform diagram showing the timing of the logic circuit in Figure 8. Figures 10 and 11 are configuration diagrams of the output stage of the key matrix input device circuit. be. 0...output signal line, po~p3...input/output signal line, q...input signal line, 17...decoder. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure/ Figure 2 Figure 3 Figure 5 ■-Switch ←Ohura←-N'ltn-H〈-Saifu□
Figure 7 Figure 6 Figure 9 Figure 10

Claims (1)

[Claims] At least one of the multiple signal lines is connected to an electric circuit that also serves as input and output, and the signal line that is connected to the electric circuit that also serves as input and output is connected to other signal lines in a key switch. A key matrix input device that constitutes a key matrix input device.