JPS5969854A - Storage circuit - Google Patents

Abstract

PURPOSE:To make it possible to access to different memory cells by the same input address and to simplify address conversion by connecting the memory cells to plural address decoders. CONSTITUTION:Column addresses 200 are stored in a column address buffer 210 and the output of the buffer 210 is inputted to two column decoders 220, 221 having different decoding rules each other. Row addresses 201 are also inputted to two row decoders 240, 241 having different rules each other. Decoder selecting signals S0, S1 are inputted to a decoder selecting part 260 to select one of the column decoders 220, 221 and one of the row decoders 240, 241. Consequently, the row and column decoders are decided and a memory cell 230 to be accessed is decided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to storage devices used in data processing equipment.

The data width that can be retrieved with one access (access data width) is larger than the data width that is the unit of addressing (address data width), and it is possible to retrieve several pieces of data with one access. In this case, a method is adopted in which a logical address is converted into an actual access address, and the data read out (by this access address) is sorted in the order of the logical address and output.

Conventionally, in the type of memory M circuit of the above type, only one address decoder was connected to one memory cell. In this case, an address conversion circuit (ADD 0O
Nv) 110, each storage unit (MMO~3) 13
In the case of Figure 1 as an access address to 0 to 133,
Remove the lower 2 bits from the logical address Zoo and create the remaining one and add +1 to it, which one is the memory address register (MA RO ~ 3) 120
.about.123 was determined for each memory circuit before data access.

Therefore, address conversion circuit (ADD 0ONv) 11
This has the disadvantage that 0 becomes sloppy and the addition process takes time. Note that the circuit shown in FIG. 1 stores data retrieved from memory in a memory data register (MDR) 14.
0 to 143, atto L/, X conversion circuit (ADD
0ONV) No, the name is searched for, and the shift pupil is sorter (
5ORTE Ding () 1s.

This is an example of rearranging the data in the order of logical addresses.

The purpose of the present invention is to connect a plurality of address decoders with different decoding rules to a memory cell so that the information of each memory cell can be shared by a plurality of input addresses, and to convert an input address into an address to be accessed. It is an object of the present invention to provide a memory circuit which is simple and allows high-speed access.

In order to achieve the above object, a memory circuit according to the present invention converts a logical address into an actual access address, writes 4 out of 4 to this access address, and sorts the data in the order of the logical address. one or more memory cells, a column buffer for logical address information provided corresponding to each memory cell, a logical address information norow buffer, a plurality of column decoders for decoding information stored in the column buffer, and storage in the row buffer. a decoder selection section that selects one column decoder and one row decoder from among the plurality of column decoders and the plurality of row decoders by a decoder selection control signal; and the one or more memories. It consists of a sorter for sorting input or output data for cells.

According to the above configuration, the object of the present invention is completely achieved.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a coordination block diagram showing one embodiment of the memory circuit according to the present invention.

Column addresses (AO to A4') 200 are stored in a column address buffer 210, and the buffer outputs are input to column decoders 220 and 221 having different decoding rules. Also, the row address (A5 to A9) 201 is the row address buffer 2
11, and its buffer output becomes input to row decoders 240 and 241 having two different decoding rules. Two column decoders 220 and 221 are connected to the memory cell 230 in the column direction, and two row decoders 240 and 241 are connected in the row direction.

A decoder selection control signal (S O, S 1 ) 250 is input to the decoder selection section 260 and the column decoder 220
, 221 and one of the row decoders 240, 241. The memory cell 230 to be accessed is determined by the selected row decoder and column decoder. Write data to memory cell 230 (DIN
) 270 is controlled by a write control circuit 280 using a chip select signal (O8) 271 and a write control signal (W8') 272.

Read data (DOUT) 273 is taken out from an output buffer 281 controlled by chip select signal OS 271 and write control signal WE 272.

Reading and writing data to memory cell 230 is controlled by successive write multiplexer 290 .

FIG. 3 shows an example of decoding. To simplify the explanation, the addresses AO-A9 shown in Figure 2 are replaced by XO-X3, YO.
-Y3 is abbreviated.

Column address (XO-X2) 300 is decoder 3
10, and the column decoder 320 further decodes its output. Column decoder 320 is composed of two different decoders. Similarly in the row direction, the row address (Yo-Y2) 3o1 is decoded by the decoder 311, and the output thereof is further decoded by the row decoder 321. Row decoder 321 also 2
It consists of two different decoders.

FIG. 4 shows two decoding rules. The decoder is Xo
−X2 (YO~Y2) decoded exactly as the value (a
) and Xo-X2 (YO~Y2) plus +1.

Decoder selection section 3
30 selects a decoder. For example, when SQ="O", an a-type decoder is selected, and when SO="1", a b-type decoder is selected.

FIG. 5 shows an example of a pit-addressable memory circuit with an access width of 16 bits, which is a combination of the memory circuits shown in FIG. 2. Input address is AO~A9500 and BO-B
35 old.

AO-A9 is a word address when 16 bits are one word, and BO-83 is a pit designation address within the access width. Memory circuit blocks 510 to 5 in FIG.
Of these, AO to A9 are input to 1F. Comparing circuits 530 to 5501 compare pit position designation values 520 to 52F that designate pit positions within the access width of memory circuit blocks 510 to 51F with pit designation addresses BO to B5501.
53F, and the decoder in the memory circuit block is selected according to the rules shown in FIG. BO-8
16-bit data is output continuously from 3 onwards. The retrieved data is also input to a sorter 570. The sorter determines the shift margin based on the signals given from each of the comparison circuits 530 to 53F, and rearranges the data in address order.

When the retrieved data length information 550 is given, the data length control circuit 540 uses the signals from the comparison circuits 530 to 53F to select the memory circuit block that contains the information to be retrieved, and performs chip select on only that memory circuit block. enable. In addition, data output from unnecessary memory circuit blocks is set to 0'' by gates 560 to 56F.
I have to.

In this way, only necessary data is sorted in address order and retrieved to DATA OUT 590.

In the case of writing, DATA IN 580 is developed in the corresponding memory circuit block position by the sorter and DiH
is entered and written to.

As described in detail above, the present invention has a memory cell/l/
f+l By connecting several address decoders, different memory cells can be accessed with the same input address, and part of the complex processing of input addresses (+1 addition processing as in this example) can be replaced by the decoders. This has the effect of simplifying address translation and enabling high-speed access.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of reading out a conventional memory circuit, FIG. 2 is a circuit diagram showing an example of a memory circuit block, FIG. 3 is a circuit diagram showing an example of a memory circuit decoder, and FIG. 4 is a diagram showing an example of a memory circuit block. FIG. 5 is a circuit diagram showing an example of a pit address storage circuit, and FIG. 6 is a diagram showing an example of a decoder selection rule. 100...Logical address 110...Address conversion circuit 120-123...Memory address register 130~
133...Memory cells 140-143...Memory data register 150...
・Sorter 200...Column address 201...
Row address 210...Column buffer 211...
... Row buffers 220, 221... Column decoder 230... Memory cells 240, 241... Row decoder 250... Decoder selection control signal 260... Decoder selection section 270... Write data 271 ...Chip select signal 272...Write control signal 273...Read data 280...Write control circuit 281...Output buffer 290...Read/write multiplexer 300...Column address 301. ... Row address 310, 311 ... Decoder 320 ... Column decoder 321 ... Row decoder 302 ... Decoder selection control signal 330 ... Decoder selection section 500 ... Word address 501 ... Bit address 510-51F...Memory circuit block 520-52F
'...Bit position designation value 530-53F...Comparison circuit 540...Data length control circuit 550...Data length information 560-56F...Gate 570...Sorter 580...Write information 590... Readout information Patent applicant NEC Corporation agent Patent attorney Inoro Hisao I

Claims (1)

[Claims] Convert logical address to actual access address,
A storage circuit that reads and writes to this access address and sorts the data in the order of logical addresses has one or more memory cells and a column buffer for logical address information provided corresponding to each memory cell. , a row buffer for logical address information, an algebraic column decoder for decoding the information stored in the column buffer, a plurality of row decoders for decoding the information stored in the row buffer, and a column for the number of plates according to a decoder selection control signal. The decoder includes a decoder and a decoder selector for selecting one column decoder and one row decoder from among a plurality of row decoders, and a sorter for sorting input and output data for the one or more memory cells. memory circuit.