JPS5980034A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a titled circuit and to facilitate an easy multiplex constitution of a higher order, by providing high-speed and low-speed separating parts at the reception side to convert the reception data into parallel signals at the high-speed separating part to extract the synchronizing signal output the parallel data at the low-speed separating part, respectively. CONSTITUTION:The upper and lower multiplex separating parts Mux1 and Mux2 are provided at the receiving part of a frame synchronizing system. The part Mux1 contains a shift register S-REG, a deocder DEC, a counter COUNT, a timer generating part TIM and a register REG. While the part Mux2 includes a synchronism detector SYNDET. Then the reception data is converted into parallel signals by the REG of the part Mux1. By receiving the parallel signal, the detector SYNDET of the part Mux2 detects the synchronizing signal. The COUNT is advanced to 1 from 0, and a phase separated clock is applied to the REG from the timer TIM. This operation is repeated until a prescribed phase is obtained. Thus the frame synchronism is facilitated with simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION fa) Technical Field of the Invention The present invention relates to an apparatus for communicating data using synchronization flags or synchronization patterns.

(bl Prior Art and Problems) In the conventional frame synchronization method, the transmitting side inserts a synchronizing flag or synchronizing pattern into the synchronizing flag or synchronizing pattern area on the frame format I, and transmits it, and the receiving side In this method, when further multiplexing is required, the upper multiplexer adds a synchronization pattern and sends both the upper and lower synchronization patterns together. There are three possible multiplexing methods, but the former and the latter synchronization flag or synchronization pattern must be detected at the speed of the upper transmission line, and as the speed of the transmission line increases, the speed of the detection circuit must also increase. There is a drawback that it must be done.

(C1 Purpose of the Invention The purpose of the present invention is to increase the speed of the synchronization detection unit, which tends to increase in speed as the speed of the transmission path increases, by 1/n with respect to the speed of the transmission path.
By providing a method that can perform transmission at a speed of The object of the present invention is to make it possible to easily realize a high-grade amplifier at a low cost.

(d) Structure of the Invention According to the present invention, a plurality of low-order group signals including a synchronization signal are time-division multiplexed and transmitted, and the reception side receives the synchronization signal by extracting the synchronization signal from the received data. In a communication system that separates data in synchronization with data, a high-speed separation section and a low-speed separation section are provided on the receiving side, the high-speed separation section converts the received data into parallel signals, and the low-speed separation section converts the received data into parallel signals. This is achieved by providing a frame synchronization method in which the synchronization signal is extracted from the parallel data in the separation section.

(Q1 Embodiment of the Invention The present invention is a low-speed demultiplexing unit. The low-speed demultiplexing unit uses a synchronization flag or a synchronization pattern on a frame form as a means for controlling a high-speed transmission line and a demultiplexing unit. , and the synchronization detection is not performed by the high-speed demultiplexer, but by the low-speed demultiplexer.

The details of the present invention will be explained below with reference to the drawings.

i11H+ is a frame format 1- of 8 Mbps (low speed), F indicates a frame pattern, and D indicates data.

As can be seen from the 3 Mbps frame former shown in Figure 1, a 71/-m pattern is placed in each frame pattern area, and the receiving side uses this pattern to establish synchronization. Let's do it.

FIG. 2 shows a frame format when the present invention is applied when multiplexing from 3 Mbps (low speed) to 32 Mbps (high speed), and D represents data.

Of the frame pattern area shown in Figure 2, only the shaded area is covered by the frame pattern, and this pattern is
This matches the 3 Mbps frame pattern shown in the figure.

FIG. 3 is a block diagram of a receiving section according to the present invention.

In the figure, Muxl is an upper demultiplexing unit, M u x 2 is a lower demultiplexing unit, S and REG are shift registers, and C0U
NT is a counter, DEC is a decoder, TIMER is a timer generator, PEG is a register, 5YN-DET
is a synchronous detector.

In FIG. 3, the upper multiplexer/demultiplexer (Muxl) applies a 32 Mbps signal to shift registers S and REG. Shift register S, REG
At this point, the 32 Mbps signal is converted from serial to parallel. On the other hand, if the binary two-digit counter C0UNT is displaying 0, for example, this output is sent to the decoder DE.
C, is encoded and applied to the timer generator TIMER. The timer generation unit TIMER is the decoder DE
A phase-separated clock is generated from the C signal and a signal obtained by frequency-dividing the 32 Mbps clock, and is input to the register REG.

The data punching position of the register REG changes depending on the phase of the phase separation clock, from phase 0 (#0) to phase 3.
It is possible to shift up to phase (#3). Assuming that the register REG now specifies phase 0 (#0), in response to this, the lower demultiplexer (Mux2) sends only the signal of phase 0 (#O) to the synchronous detector 5YN- In addition to DET, synchronization detection is performed, and if synchronization cannot be achieved within a certain period of time, a synchronization discontinuation signal is sent to the upper multiplexer/demultiplexer (Muxl).

When the upper demultiplexing unit (Muxl) receives the synchronization loss signal, it next selects the synchronization detector 5YN- corresponding to only one phase (#1).
Send to DET. That is, when the upper demultiplexer (Muxl) receives the synchronization loss signal, it starts the binary two-digit counter C0U.
Advance NT from 0 to 1 state. Below, as before, send the phase separated clock to the register REG, add only one phase (#1) to the synchronization detector 5YN-DET), perform synchronization detection, and if synchronization cannot be detected within a certain period of time, the upper multiplex A synchronization loss signal is sent to the separation unit (Muxl).

In this way, 0 phase - 1 phase, 1 phase - 2 phase, 2 phase - 3 phase, 3
It is sent sequentially from phase to 〇 phase. Upper demultiplexer (Muxl)
The lower multiplexer/demultiplexer (Mux2) repeatedly performs this operation, and becomes stable when synchronization is detected.

In this method, the upper demultiplexer (Muxl) has three functions.
It only converts 2 Mbps to 8Mbps, and the lower multiplexer/demultiplexer (Mux2) is the same 8Mbps as before.
Since synchronous detection of Mbps is possible, the circuit configuration can be easily made, and it can be operated with only the lower demultiplexer (MIJX2>), so it is possible to upgrade an 8Mbps device to a 32Mbps device.・It is possible to upload.

ff1 Effects of the Invention As explained in detail above, according to the present invention, the synchronization detection circuit can be made low-speed, so the circuit configuration can be simplified, and the low-speed demultiplexer can perform high-speed demultiplexing. This has the great effect of making it much easier to configure higher-order multiplexing.

[Brief explanation of drawings]

FIG. 1 shows an 8 Mbps frame format. FIG. 2 shows a frame format when the present invention is applied when multiplexing from 8 Mbps to 32 Mbps. FIG. 3 is a block diagram of a receiving section according to the present invention. In the figure, M u x 1 is an upper demultiplexing unit, M u x 2
is the lower demultiplexer, S, REG is the shift register, COUNT is the counter, DEC is the decoder, T
IMER is a timer generator, REG is a register, SY
N-DET is a synchronous detector.

Claims (1)

[Claims] In a communication method, multiple low-order group signals including synchronization signals are time-division multiplexed and transmitted, and the receiving side extracts the synchronization signal from the received data to separate data in synchronization with the received data. A high-speed separation section and a low-speed separation section are provided on the side, the high-speed separation section converts the received data into parallel signals, and the low-speed separation section extracts the synchronization signal from the parallel data. Frame synchronization method.