JPS598076A - Image reduction/enlargement device - Google Patents

Abstract

PURPOSE:To reduce and enlarge a picture at a high speed with a simple circuit constitution, by providing an input buffer, an output buffer, an address counter, a sampling counter, etc. CONSTITUTION:The picture information D1 of a prescribed quantity is fed to an input buffer 10 and transferred for temporary storage to an output buffer 20 in the form of information D2 in response to an input clock signal CK1. These buffers 10 and 20 are addressed by address counters 11 and 21 and driven by clock signals CK1 and CK2, respectively. AND gates 12 and 22 and NAND gates 13 and 23 are connected in series to the counters 11 and 12, respectively, and a sampling counter 30 is connected to the gates 13 and 23. Then a main clock signal MCK is applied to the gates 12 and 22 as well as to the counter 30, and enlarging and reducing commands CC1 and CC2 are supplied to the gates 13 and 23 respectively. At the same time, a preset signal is applied to the counter 30. Thus a picture can be optionally reduced or enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing device, and more particularly to an image reduction/enlargement device for image display, editing, etc.

[Technical background and problems of the invention]

Various methods are known for reducing or enlarging images, but for those that perform reduction or enlargement through software operations, it is difficult to process in real time, and interactive editing cannot be expected. Ta.

Therefore, in the case of reduction using an adder, the magnification is repeated and added, and in the case of enlargement, the i factor is repeated and added, and the carry signal is used as a sampling signal for pixel thinning or duplication. There was something to do. However, according to this method, reduction and expansion of magnification expressed by simple integer ratios such as 1x and 1x are also characterized by a large number of digits. [Purpose and Summary of the Invention] This invention was made in an attempt to eliminate the drawbacks of the prior art as described above. It is an object of the present invention to provide an image reduction/enlargement device that can perform reduction/enlargement processing simply and at high speed.

To achieve this objective, the present invention provides an input buffer for storing a predetermined amount of image information, an output buffer for transferring the information in this manual buffer and preparing it for output, and an output buffer for controlling the reduction rate or and a sampling counter that sets a preset value according to the enlargement ratio and outputs a digit signal according to the preset value, and by thinning out the main black signal with the output of the sampling counter, the output is reduced in the case of reduction. A buffer is driven by the main clock signal and the input buffer is driven by the thinned out clock signal, and in the case of expansion, the input buffer is driven by the main clock signal and the output buffer is driven by the thinned out clock signal. Drive it with a clock signal.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. .

FIG. 1 is a system diagram showing an image reduction/enlargement apparatus according to an embodiment of the present invention. According to the figure, an input buffer 10,
Output buffer 20, address counter //, 2/,
And gate t2, D, Nantes gate/3゜co3
, and sampling counter 30 are shown.

The manual buffer 10 is a temporary storage device for storing image information D/ for one scanning line, and is constituted by, for example, a register.

The output buffer 20 receives the information in the input buffer IO as necessary, is transferred as 2, temporarily stores it, and prepares for output, and is configured with, for example, a register.

These manual buffer 10 and output buffer 20 are address counters //, !, respectively. / and driven by clock signals OK/, OK2. Hereinafter, if necessary, the clock signal OK/ will be referred to as an input clock signal and the clock signal CK2 will be referred to as an output clock signal.

ANDGATE/J, 22 and NANTGATE/3,
J.? together with the sampling counter 30, forms the input clock signal OK/ and the output clock signal OK,2 based on the main clock signal MCK. The sampling counter 30 is operated by the main clock signal MOK and sets a preset value PD according to the reduction rate or expansion rate;
A digit signal BW indicating carry up or down is output according to this preset value PD. For example, when the preset value FD is 2, the digit signal BW is output every third clock signal, and when the preset value is j, the digit signal BW is output every sixth clock signal.

According to such a configuration, the enlargement command CC7 or the reduction command 0
0.2. and input buffer 10 according to the preset value.
Reduction processing is performed by regularly thinning out and transferring the information within, and enlargement processing is performed by regularly transmitting the same data twice.

Next, the operation of this embodiment will be explained.

First, let us consider a case where the image is reduced by a factor of 7. In this case, 7 pixels out of 3 pixels may be regularly thinned out and output. Therefore, the enlargement command OC/-o (low level), the reduction f
fH order OC, 2 = / ()・I level).

Also, the counter 30's output (direct PD-2) is set.
'At this time, the output of Nant Gate/3 is always) -
This is because the enlargement command 00/, which is one input of the Nant gate /3, is always at a low level "O".
This is because it is unrelated to the other input by the sampling counter 30. Therefore, the output of the AND gate 1 is equal to the input clock signal OK/mask clock signal MOK.

On the other hand, one out of every three main clock signals MOK is thinned out from the output of the Nant gate 2. That is, one of the inputs of AND gate n is the main clock signal MOK,
The other is the signal from the Nantes gate 23. One of the human power inputs the reduction command CC to the output signal of Nant Gateco 3,
Since 2=/, the output BW of the sampling counter 30 is followed by 7. Here, the preset value of the counter 30 is PD-2, so the output BW of the counter 30 is synchronized with the main clock signal. Then (o, o, /) is repeated.

Therefore, the output of the Nant gate 3 is (/, /, 0) repeated, and the output of the AND gate 22, that is, the output clock signal OK, is the repetition of 2 digits (/, /, 'o).

Such human clock signal OK/, output clock signal CK2, and these signals OK/, OK! FIG. 2 shows the relationship between the information DJ and the DJ transferred by the DJ. Assuming that the image information D/ of a predetermined song is stored sequentially in the input buffer lO, the input buffer 1 is
The information in 0 is read out as 2 and transferred to the output buffer θ. This information D2 is equal to information D/.

At this time, the output buffer λθ is driven by the output clock signal OK,2 described above and shown in FIG.

Therefore, the human power information i, i+/, i+, 2.1+J.

When 1+2, 1+3.1+ out of 1+v, . . . are output from the manual buffer 10, the output clock signal CK2 does not exist. Therefore, 1+2, 1+t, i
44 emotions are not read out from the output buffer 20, and as a result, 111 pieces of information are transferred from the output buffer Ayu 0, where every 3 pixels are thinned out by 1 pixel, and ! When the line transfer is completed, image information D3 reduced to a size of 1 is obtained.

As an example of the operation in the case of enlargement, in case of enlargement of 5 times! A time chart is shown in Figure 3.

In this case, one of the inputs of Nandogame)/J and J3 in FIG. 1 is the enlargement command 00/-/ and the reduction command aci=
o, and the preset value FD of the sample link counter 30 is assumed to be j. In this way, as shown in Figure 73, the human clock signal CK/, which is thinned out by one every t times, and the output clock signal OK, 2, which is equal to the main clock signal MCH, are obtained. When the input clock signal OK/ is not output, the same information is sent to the output buffer ACO 0, for example, 11- in Fig. 3.
F, i+ri are input twice. When the transfer of the / line is completed, a further enlarged image report D3 is obtained.

In the above, we have explained the process y11 in the main scanning direction, but for the processing in the sub-scanning direction, regular line thinning is performed for each line in the case of reduction, and regular line thinning is performed in the case of enlargement. All you have to do is overlap the lines. In this case, processing is performed line by line, and since there is sufficient processing time, conventional methods such as using a microprocessor can also be used. That is, the present invention can be used alone or in combination with conventional methods.

[Effects of the Invention] By configuring as described above, this invention can easily perform one step of image reduction/enlargement processing at high speed.
An image reduction/enlargement device capable of interactive processing and editing work can be provided.

[Brief explanation of drawings]

Fig. 1 is a system diagram of an embodiment of the present invention, Fig. 2 is a time chart when reduction processing is executed by the apparatus shown in Fig. 1, and Fig. 3 is an enlargement processing executed by the apparatus IIK shown in Fig. 1. This is a time chart of the case. 10...Manual buffer, X...Output buffer, 3θ
・・Sampling Callan p, //,,l・Address counter, /2, . 2.2... and Kate,
/3, u3...Nant gate, MOK...main clock signal, FD...preset value O

Claims (1)

[Claims] An input buffer that stores a predetermined amount of image information. An output buffer 7 to which the information in the manual buffer is transferred and prepared for output, and a sampling counter that is operated by a main clock signal, sets a preset value according to the reduction ratio or enlargement ratio, and outputs a digit signal according to this preset value. decimating the main clock signal with the output of the sampling counter; in the case of reduction, driving the output buffer with the main clock signal and driving the input buffer with the decimated clock signal; Further, in the case of enlargement, the image reduction/enlargement apparatus is configured to drive the input buffer with the main clock signal and drive the output buffer with the thinned out clock signal.