JPS5984697U - Arithmetic circuit - Google Patents
Arithmetic circuitInfo
- Publication number
- JPS5984697U JPS5984697U JP14891183U JP14891183U JPS5984697U JP S5984697 U JPS5984697 U JP S5984697U JP 14891183 U JP14891183 U JP 14891183U JP 14891183 U JP14891183 U JP 14891183U JP S5984697 U JPS5984697 U JP S5984697U
- Authority
- JP
- Japan
- Prior art keywords
- input
- terminals
- output
- constant bias
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
- Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係る演算回路の原理図、第２図、第３
図は本考案の演算回路を適用した具体的−実施例図であ
る。
１・・・演算器、２・・・出力端子、３・・・第１共通
端子、４・・・バイアス電源、５，６・・・第２共通端
子、Ｘ０゛〜Ｘｎ・・・入力端子。Figure 1 is a principle diagram of the arithmetic circuit according to the present invention, Figures 2 and 3.
The figure is a diagram showing a specific embodiment to which the arithmetic circuit of the present invention is applied. DESCRIPTION OF SYMBOLS 1... Arithmetic unit, 2... Output terminal, 3... First common terminal, 4... Bias power supply, 5, 6... Second common terminal, X0゛~Xn... Input terminal .
Claims (1)
力端子、出力端子およびこれら入出力端子の第１共通端
子とを有する端子構成の演算器と、第２共゛通端子と、
前記両共通端子間に接続された前記一定のバイアス信号
骨と等しい値の一定バイアス電源とを具備し、前記一定
のバイアス信号を含んだ複数の入力信号を前記複数の入
力端子と前記第２共通端子間に入力すると共に、前記出
力端子と前記第２共通端子間から演算信号を出力するよ
うにしたことを特徴とする演算回路。an arithmetic unit having a terminal configuration having a plurality of input terminals, output terminals, and a first common terminal of these input/output terminals that handle input/output signals containing a constant bias signal; a second common terminal;
a constant bias power supply having a value equal to the constant bias signal connected between both the common terminals, and a plurality of input signals including the constant bias signal connected to the plurality of input terminals and the second common terminal; An arithmetic circuit characterized in that an arithmetic signal is input between terminals and is output from between the output terminal and the second common terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14891183U JPS6022479Y2 (en) | 1983-09-28 | 1983-09-28 | Arithmetic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14891183U JPS6022479Y2 (en) | 1983-09-28 | 1983-09-28 | Arithmetic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5984697U true JPS5984697U (en) | 1984-06-07 |
| JPS6022479Y2 JPS6022479Y2 (en) | 1985-07-03 |
Family
ID=30330710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14891183U Expired JPS6022479Y2 (en) | 1983-09-28 | 1983-09-28 | Arithmetic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6022479Y2 (en) |
-
1983
- 1983-09-28 JP JP14891183U patent/JPS6022479Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6022479Y2 (en) | 1985-07-03 |
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