JPS5985194A - Picture encoding system - Google Patents

Abstract

PURPOSE:To reduce the detrioration in picture quality due to a transmission error by assigning a code of sample number information so as to detect one-bit error in this information and controlling the readout of a buffer memory. CONSTITUTION:A data received from an input terminal 13 is stored once in the buffer mory 15. Further, a counter 23 receives an output of a clock regenerating circuit 22, counts it for one line period and the result is applied to a buffer readout control circuit 24. The control circuit 24 compares the output of a sample number information detecting circuit 17 with an output of the counter 23, and when the both are coincident, the decoding is done normally and when dissident, the buffer memory readout control from a variable length decoding circuit 18 is inhibited, a synchronizing pattern detecting circuit 16 is controlled to decode the next synchronzing pattern, and the decoding is stopped during that time. If an output of the detecting circuit 17 shows an impossible pattern, the control of the memory 15, the detecting circuit 16 and the decoding circuit 18 is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image encoding system that is resistant to transmission errors. It is something.

A typical method for converting both images A1 and F'1 is a predictive coding method. This method subtracts the 1,000 values obtained from the encoded pixel Tsukuda from the current Buddhist name, and obtains tL/ζ 1ll1
1 Error A1: The bow is computerized, and the output of the child's hanger is made into a flash.

Normally, quantified output has a bias in the frequency of occurrence of output values, so by using this property, f
By assigning a short code 71 and assigning a long code to an output value that occurs only occasionally, the average codeword length is shortened and the coding efficiency is reduced to 1. It's spreading. However, since the information generation is uneven, the oJ variable-length encoded output is temporarily stored in the Tsunoa memory for speed smoothing, and the stored data is read out at a constant speed and sent to the digital transmission line. Sending out.

However, when an error occurs in the digital transmission path, predictive coding causes significant deterioration in the decoded image.

That is, when data containing a transmission error is decoded on the receiving side, it is treated as a different code from the code sent on the transmitting side. In this case, unless a variable length code is used, the code may be interpreted as a code of a different length and decoded, which may disrupt subsequent word synchronization.

In order to eliminate the effect of this error at a certain point, there is a method of transmitting a synchronization signal at the beginning of an image line. This synchronization button allocates a code that cannot occur at the moment of time. In r41tllI, subsequent word synchronization is restored by detecting this synchronization pattern.

However, if the other dip code coincides with the above synchronization button due to a transmission path error, the receiving (i+ side) sets the point at which it is decoded as 1-1 with the beginning of the line, and from then on In order to decode the data, the operation of the buffer memory for the speed down/1' on the receiving side becomes inconsistent with the operation of the buffer memory for the speed '/i' of the transmission +1111.As a result,
In the receiving side speed smoothing/toso memory, the input information exceeds the storage capacity of the buffer memory (h) and overflows (referred to as -I1), or the back-r memory is empty. The image may not be reproduced correctly (referred to as a/da flow).

In order to eliminate such inconveniences, conventional methods of this type have been adopted, as shown in one or more of the following methods.

In other words, if information representing the number of samples per line is inserted and transmitted next to the synchronization button as described above, and the number of samples detected on the receiving side differs from the number of samples actually decoded, Considering the effect of the error,
The subsequent decoding is stopped for 111 hours and the data at the next synchronization button 1 is ignored.

FIG. 1 shows an example of a conventional freight configuration.

The synchronous bang is “100000000001” (D
The number of samples per line is expressed as 1 chit. II between these
II has a simplified device configuration so that it can process in units of 4 hits.

The sample number information is +110111, which is 5.
Suppose that 83 samples are decoded, but the number of samples actually decoded is 580. In this case, it is assumed that an error has occurred, and the code is temporarily stopped. Ignore the data at the age of 1.

With this decoded sample number information and actually decoded) r
The difference between , =J and the number occurs in the following cases.

0) An error has occurred in the data representing sample number information ■ An error has occurred in the image data 1. ■ An error = occurred in the data before the synchronization slam, causing the sword synchronization to be disrupted and the number of decoded samples to be out of order ■, In the case of c3), an error occurred before the synchronization button. Synchronization is also disrupted, or in the case of O), word synchronization is in a state where it is difficult to stop.

In this way, in the conventional method, the word 1υ] is not disturbed (even in the case of 70, data for one line is ignored).
This has the disadvantage that the reproduced image deteriorates more than necessary.

In order to eliminate such drawbacks, the present invention improves the influence of errors by assigning one person to the number of data representing sample number information, thereby reducing the quality deterioration caused by errors by one person.
1. The present invention will be explained in detail with reference to the drawings. 1. Figure 2 shows an embodiment of the present invention, 1. is the image input terminal,
2 digits A/I) ``4j conversion circuit, ; 3('' predictive coding circuit, 4 ui 'nJ variable length saving - bow conversion circuit 5 k masu 31
'Synchronization detection circuit, 6 beams, knock generation circuit, 7.23 is counter, 81 multiplication circuit, 1.15 is buffer memory, Hl, 14 is buoy/tal ink face, 11 is data output terminal A, 12 - Digital transmission line, 1; 3 is a data input terminal, 16 is a synchronous bang detection circuit, 17 is a sample full number information detection circuit, J8 is a variable length decoding circuit, 19d is a predictive decoding circuit, 20 is a D/A conversion circuit, Reference numeral 21 designates both image outputs Q:A: output, 22 a single-track reproduction circuit, and 24 a buffer readout control circuit.

The signal input from the image input terminal 1 is sent to the A/D conversion circuit 2.
After being converted from an analog signal to a digital signal in the predictive encoding circuit 3, a predetermined naturalization process is performed in the predictive encoding circuit 3, and furthermore, in the variable length encoding circuit 4, codes of different lengths are assigned.

The horizontal synchronization detection circuit 5 detects the water ΔF synchronization Buddhist symbol of the input image signal, generates a horizontal synchronization signal "+00000 (l O old 101") at the start point, and supplies it to the multiplexing circuit 8. .It also supplies the reset 1 signal to the non-tough force.

The knock generation circuit 6 generates one thump ring and supplies it to each circuit necessary for I-bow formation.
It counts for 101 times, and resets the counter output by the ringing signal for one line or more.

The multiplexing circuit 8 configures a frame A for each line and multiplexes the outputs of the variable length comparison circuit 4, the horizontal synchronization detection circuit 5, and the counter 7. FIG. 3 shows an example of the frame structure in the case of . Synchronous data is expressed in 12 bits, and sample number information is expressed in 4 bits. One of these four people
If an error occurs in a sample, a code is assigned so that it is not interpreted as another sample number error.

After the output of the multiplexing circuit 8 is smoothed in speed in the d-buffer memory 9, it is converted into the signal format of the transmission line 2 in the digital interface 10, and then sent to the data output terminal J1.
The signal is outputted to the digital/tal feeding path 12 through the shaft.

On the receiving side, the data received via the data input terminal 13 is terminated in the digital interface 1 and then supplied to the buffer memory 15 and the buffer memory 15.
is the same jυj slam detection circuit 16,
sample number information detection circuit] 7 and variable length decoding circuit J
8 controls the read speed. The read /ζ data is detected and branched as a synchronization pattern by the synchronization pattern detection circuit J6, and other data passes through and is supplied to the one-sequence number information detection circuit 17.

As shown in FIG. 3, the Zamburu class information detection circuit 17 detects (4c) following the 12 synchronization hits (- branches this, and performs variable length decoding on the other b) variable length r] codes. Supplied to circuit 18.

The data decoded by the variable length decoding circuit 18 is subjected to predetermined encoding processing in the decoding circuit 19, and then sent to the /A conversion circuit 20 where it is converted into a real analog signal. and is output to the image output terminal 21.

On the other hand, the clock regeneration circuit 22 receives the output of the digital interface 14, regenerates the knock signal, and outputs an output signal to each circuit as necessary to the input signal 23 and the decoding circuit.
(Supply.

The counter 2:3 receives the output of the one-click reproducing circuit 22, outputs it for one line period, supplies the result to the buffer readout control circuit 24, and then outputs the output of the synchronization/loss of tanning detection circuit 16. Reset 1.

In the present invention, the readout control circuit 24 compares the output of the full number information detection circuit 17 and the output of the counter 23, and determines if the two match.
rK decoding, and in case of mismatch, variable length TM encoding circuit 18
It is prohibited to read buffer memory from
3. Controls the slam detection circuit 16 to read the next 1υ top button jv1, and controls the opening length change production circuit 18 to read the next synchronous slam (1). Interval decryption (/
? 111-Suru 3, Sunda, Dumbul number information detection circuit 17
Since the output of -r shiller is shown in Figure 13, it is different from [7ta・ζtan (I not・ζtan or 11−+I
] When representing III, l/:t ) ,,,
, 1.1 buffer memory] 5, synchronization butter> detection circuit] 6 and variable length decoding circuit 18 limit 1 is prohibited II
do.

In addition, in the description of the embodiment 1- below, the power ρ, which configures the synchronous slam detection circuit 16, the -reipple number information detection circuit 17, and the variable length decoding circuit 18 in series,
However, it is clear that they can be arranged in parallel to form a real sister.

As explained above, the present invention is based on sample number information.
The code is assigned so that one error in this information can be detected, and if an error is detected in this part,
Since the configuration is such that backup memory read control is prohibited, there is an advantage that image quality deterioration due to transmission errors can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows an example of a conventional frame structure, FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows an example of the frame structure in the present invention. 1...Image input terminal, 2...A/D conversion circuit, 3...Predictive coding circuit, 4...Mountain/variable length coding circuit, 5...Water 3V synchronous detection circuit,
6... Song clock generation circuit, 7.23... Counter, 8... Multiplexing circuit,! 1.15 ・、
・・Haso・End Memo'）, IC1, 14... Di/
shoes

[-Interface 1-, ]1 ・To...-1-Reoutput terminal r-112-・I,! Tal transmission line, 13...
・・Data person 'J:;'':l I'-'i...Synchronization・(Tan detection circuit, 17 1, 'Information detection circuit, 18
...Variable length encoding circuit, 19... Preliminary! l
I decoding circuit, 20. l'l/A conversion circuit, 21
......Picture r3 14 power end Iha 22... Clock regeneration circuit, 24...Buffer read fl+! I inn j circuit.

Claims (1)

[Claims] Transmission signal ri11[lI is an encoding circuit that encodes an input image signal based on a predetermined encoding algorithm, and a variable length encoding circuit that assigns a variable length code to the encoded output. , a horizontal synchronization detection circuit that detects a horizontal L1 signal in an input image signal and generates a synchronization bang signal representing the beginning of a video line; a counter that counts the number of samples per J line and outputs sample number information; a counter, the horizontal synchronization detection circuit;
and a multiplexing circuit that time-division multiplexes the output of the encoding circuit, and a buffer memory that smoothes the speed of the output of the multiplexing circuit and sends it out at a constant speed, and the receiving side temporarily stores the received data. and a buffer memory that reads out the stored received data according to the decoding speed.
A synchronization bang detection circuit that detects a synchronization pattern in received data output from the sofa memory, a sample number information detection circuit that detects sample number information in the received data, and a variable length code that decodes the variable length code in the received data. A long decoding circuit, a decoding circuit that receives the output of the variable length decoding circuit and reproduces an image based on a predetermined decoding algorithm, and a decoding circuit that receives the output of the variable length decoding circuit and reproduces an image based on a predetermined decoding algorithm. In an image encoding method including a counter for counting the number of ripples, and a buffer readout control circuit that compares the output of the counter with the output of the sample gauze information detection circuit and controls the readout of the buffer memory when the two do not match. , the code is assigned to the sample number information so that a one-hit error in this information can be detected, and when an error is detected in this part, the buffer memory read control from the buffer read control circuit is prohibited. A special image encoding method.