JPS5985977A - Display device for preparation of submarine map - Google Patents

Abstract

PURPOSE:To obtain a submarine map in a wide range with an easy judgement on the undulation of the sea bottom depending on the color of the screen by displaying information on the undulation of the sea bottom in a wide range of sea area as viewed from above (sea surface) after it obtained by execution of continuous searching and memorized sequentially. CONSTITUTION:Signals from the various direction of receiving waves are written sequentially into addresses of a memory 10 as specified by output counts of an azimuth counter 5 and a range counter 7 via an amplification detecting circuit 8 and an A/D conversion circuit 9. The memory 10 has a memory capacity (n) rows in the azimuth and (l) lines in the depth to memorizes a received signal based on the one transmission. The received signals thus written are introduced into a signal processing circuit 11 to process. The signals read from the memory 10 is limited to the fixed depth range. This enables the reading of only received signals near the projection depth of the preset sea bottom for efficient processing and a processing thereof is performed to detect the line address where sea bottom signals exist. The projected depth of the sea bottom is set manually with a gate depth setting device 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus that scans an ultrasonic beam to detect the depth of the seabed in each direction, and creates a seafloor map based on this.

A technology has been proposed to search for the seabed relief near the vicinity of a ship and display it in a cross-sectional form (Japanese Patent Laid-Open No. 52-558).
However, with such a cross-sectional display method, for example, it is not possible to know in relation to the net that is towed behind the boat during seine fishing and the seabed state in the vicinity.

The present invention has been devised in view of the importance of knowing the seabed conditions at points other than the immediate vicinity of the ship. The present invention provides an apparatus for creating and displaying a seabed map by displaying it over a wide range of sea areas as if viewed from above (sea surface).

The following description will be made based on the embodiments shown in the drawings.

In FIG. 1, T1 to Tn are transducers arranged at equal intervals on the same plane, and ultrasonic pulses are transmitted from each transducer based on the transmission trigger from the transmission trigger generation circuit 1. . The waves transmitted from each of the above-mentioned transducers are delayed by a predetermined amount by the delay circuit 2 and are carried out under a predetermined phase relationship. As a result, a fan-shaped wave having a predetermined directivity angle ψ (see Fig. 2) is transmitted. A transmission beam is obtained.

The transmitted pulses having the above-mentioned directivity angle ψ are reflected on the seabed, return, and are received by the transducers T1 to Tk. The above vibrators T1 to T
Each of the k received signals is guided to each phase shift circuit P to Pk.

Each of the phase shift circuits P to Pk generates the transducers T to Tk based on a phase shift control signal sent from the phase shift/control signal generation circuit 3 to each of the phase shift circuits P to Pk. The phase of each received signal is changed. Reference numeral 4 denotes an adder circuit that adds the above-mentioned phase change signals.

This phase control means control of the receiving direction as described below.

That is, when the received beam is directed in the θ direction with respect to the direct direction as shown in the figure, the received signals arriving at each adjacent transducer are sequentially divided by a time corresponding to Δt (==dslnθ), for example. Better to delay it.

This is equivalent to sequentially changing the phase shift amount of each phase circuit by 2πΔt/λ. However, the interval between each transducer is d1, and the wavelength of the ultrasonic wave used is λ. And the transducers T1 to T
If the pointing direction of the received beam formed by k is set as ψ/n, the phase shift control signal generation circuit 3 generates n types of control signals in which the pointing direction sequentially changes by ψ/n, which will be described later. The information is transmitted based on the output count value of the azimuth counter 5.

As a result, reception is performed with the transmission beam width divided into n equal parts.

Reference numeral 5 denotes an azimuth counter with a counting capacity n, which repeatedly counts clock pulses of a predetermined frequency from 0 to n-1, taking into account the distance resolution of the clock pulse generation circuit 6. or,
The transmission trigger generation circuit 1 is configured to start counting operation from the value O when the transmission trigger is triggered. Based on the output count values O to n-1 of the azimuth counter 5, the phase shift control signal generating circuit 3 sends corresponding phase shift control signals to the respective phase sum circuits P1 to Pk to sequentially change the receiving direction. In this case, for example, the leftmost corner 971 minutes of the transmission angle ψ corresponds to the count value O, the next corner 971 minutes corresponds to the count value 1, and the last rightmost corner 971 minutes corresponds to the count value n - 1. The count value and the receiving direction are associated in advance so as to correspond to each other.

Reference numeral 7 denotes a distance counter that counts return pulses sent out every time the output count value of the azimuth counter 5 returns to O from O to t-1. Further, the counting operation is performed from the value O upon each transmission trigger.

In this way, the signals from each receiving direction pass through the amplification/detection circuit 8 and the A/D conversion circuit 9, and are then stored at the address of the memory 10 specified by the output count value of the azimuth color/reference 5 and the distance counter 7. Written sequentially. The memory 10 has a storage capacity of n columns in the azimuth direction and 4 rows in the depth direction, and stores received signals based on one wave transmission.

The received signal written in this manner is read out as described below, and guided to the signal processing circuit 11 for processing. The signals read from memory 10 are limited to signals with a constant depth width. That is, in order to perform efficient processing, only received signals near a predetermined predicted depth of the ocean floor are read out and processing is performed to detect the row address where the ocean floor signal exists. This predicted depth of the seabed is manually set by the gate depth setter 12. Now, as shown in Figure 2,
Gate depth. , the gate width is set to ΔL.

13 is a control signal generation circuit, as described above. The row address of memo January O corresponding to ΔL is formed and sent. Incidentally, in the memo IJIO, as the column address approaches both left and right ends from the center, the row address increases at a rate of 1/-.theta. even at the same depth.

Therefore, in order to make the gate match the depth L0 and width ΔL at all column addresses, the change coefficient 1/
A transformation that multiplies by -θ is required. For example, the row address at the center column address of the memory 10 for the depth L0 is t as shown in the figure. If so, the depth of the adjacent column. The row address for is t. /-ψ/n, and in the next column it becomes 16/as 2π/n. Such row address conversion is based on each column address, with gate depth. and L0+ΔL in the control signal generation circuit 13. and a gate depth based on a count value from 0 to n-1 for column designation and each column address for reading out the memory contents of the memo IJIO from the control signal generation circuit 13; Continuous values from the value of the row address corresponding to depth L0+ΔL to the value of the row address corresponding to depth L0+ΔL are transmitted. The above two-hand numerical value is led to the memory 10 via the 1/inclusive readout changeover switch 14, and the received signal in the seabed prediction gate is read out. The above reading is executed using the free time until one wave is transmitted. In other words, the 15 enters the waiting state when the output count value of the azimuth counter 5 reaches n-1, then sends out a signal with the first output count value t-1 from the distance counter 7, and returns to the original state with the next transmission trigger. In the signal generating circuit that is returned to the state, the control signal generating circuit 13 is driven by the signal sent out during this idle time. or,
- This signal is also led to the changeover switch 14, and the changeover switch 14 is switched to the readout side only during the above-mentioned idle time.

In this way, the received signals within the seabed prediction gate are sequentially read out for each column address and sent to the signal processing circuit 11.

The signal processing circuit 11 determines the row address where the submarine signal exists. In other words, first memorize the row address and peak value when the signal level in the submarine prediction gate read in a certain column reaches its peak, and then read out the same received signal again to obtain the peak value that was first stored. , for example 2/3
The first row address at (or above) the level of (now,
tl) is regarded as the location of the ocean floor and extracted.

Then, the gate depth of the read column address from the row address t□. The row address to/cas I corresponding to A1-1
Subtract like -o/-θ and then (zt to/-〇)
It is converted into a square θ and sent to the shift register 16. Here, (tl-t0/-θ)ctv5θ is expressed as a numerical value indicating the position within the set seafloor prediction gate, from a minimum of 0 to a maximum of 1/ (however, t' is the center of the memory 10). (row address corresponding to the depth L0+ΔL at the column address). Note that the above-mentioned reading of the received signal within the seabed prediction gate may be performed twice for each column address, or may be performed again after reading all the areas. Based on the generation method of the read address to be generated. In this way, the numerical values extracted for each column address are extracted each time, or collectively after all numerical values at all column addresses are extracted, based on the n write clock pulses from the control signal generation circuit 13. The data are temporarily stored in the shift register 16 in the order of column addresses. When the control signal generation circuit 13 finishes sending out the above-mentioned n-cooking pulses, it sends a counting clock pulse to a write address generation circuit 17 consisting of a counting circuit in order to transfer the contents of the shift register 16 to the display memory 19. N reading clock pulses having different timings are sent to the shift register 16, and the clock pulses decrease as they are sent out. The write address generation circuit 17 is the control signal generation circuit 13
An addition counter for specifying the column address of the counting capacity n that counts the counting clock pulses from 0 to n-1, and a return that sends γ every time the count value of the addition counter returns from n-1 to 0. A subtraction counter for specifying a row address with a counting capacity m that counts the numbers m-1 to 0 (both not shown)
It consists of Then, the above-mentioned two-hand value is led to the display memory 19 via the one-inclusive readout changeover switch 20, and the address corresponding to the counted value is designated. Note that the counting clock pulse sent from the control signal generation circuit 13 to the 1:include address generation circuit 17 is generated by the following shift register 16.
n clock pulses are transmitted between the start and end of the reading clock pulse. Then, using these n counting clock pulses, the extracted numerical values are sequentially written in columns 0 to n-1 of one row of the display memory 19.

Incidentally, the read clock pulses for the shift register 16 have different pulse intervals as described above, and this is for the following reason. When the beam widths (=ψ/n) are equal, the larger the beam orientation direction θ (0° to 90°), the larger the horizontal distance component at the same depth.

That is, in FIG. 3, rθ is It is expressed as

Therefore, the period of the n clock pulses is changed in accordance with the ratio of rθ/r to the change in θ, and the sending time of the n pulses is set in advance to match the sending time of the n counting clock pulses. It is determined. The circuit shown in FIG. 4 is an example of this read clock pulse generation circuit.

That is, in the same figure, 40 is a counter that subtracts and counts relatively high-frequency clock pulses from the clock pulse generation circuit 41 from the following initial setting value to 0, and sends out a matching pulse every time the counted value matches 0. do. and,
This coincidence pulse functions as the aforementioned read clock pulse. Now, the coincidence pulse serves as a reading clock pulse and is also sent to the counter 42, and is used as a readout clock pulse.
The argument is up to 1, and the counted value serves as the read address of the ROM 43.

43 is a ROM in which a value corresponding to the ratio of rθ/r is written in advance for each value of the counter 42, and the value at the address designated by the counter 42 is set as the initial value of the counter "40". Therefore, the time required to count from each initial value set in the 40 to 0 corresponds to the above ratio.In this way, the time required to count from each initial value set in the color 40 to 0 corresponds to the above ratio. Signals can be written.

Reference numeral 18 denotes a ROM for dividing and converting the values 0 to t' sequentially sent from the shift register 16 into, for example, 8 stages.
The values of ys to ty4-1 are set as shown in the drawing.

Then, the divided and converted values of each stage are stored in the write address generation circuit 1.
The data are sequentially written into the display memory 19 based on the address designation from 7 onwards. The eight stages described above correspond to eight-color display on the display 21, as described later.

The ROM 18 may be connected to the previous stage of the shift register 16, and in this case, the storage capacity of the shift register 16 can be reduced to 3
The amount of pit can be reduced.

Reference numeral 22 denotes a read address generation circuit which has an addition counter (not shown) for specifying a column address of counting capacity n and for specifying a row address of counting capacity m, and the count value for specifying the row address is the write address. The count value for specifying the row address of the generating circuit 170 is added by the adding circuit 23, and the count value for specifying the column address is directly led to the display memory 19. In addition, in synchronization with the generation of the column read address, the deflection circuit 2 of the X-Y raster
4, the display 21 is scanned. As a result, indicator 2
1, m rows are always read in order from the most recently written row address in the older direction.

Reference numeral 25 denotes a clock pulse generation circuit for sending out pulses at a relatively high frequency and switching the changeover switch 20 alternately to the write side and the read side. 26 is a ROM that converts the values of each stage read from the display memory 19 into corresponding colors;
This is a color conversion circuit consisting of the following.

As explained above, according to the present invention, the seafloor line that appears in the seafloor prediction gate is represented in color, so a seafloor map covering a wide range can be obtained in which the undulations of the seafloor can be easily determined based on the color of the screen.

In this embodiment, the direction of the detection signal received by each vibrator was controlled via a phase shift circuit, but this technique was previously proposed by the applicant (Japanese Patent Application No. 57-121439). It is also possible to use a method using a mixer. In other words, by mixing local oscillation signals with different phases (detection signals received by each oscillator) and adding the outputs of each mixing circuit, it is possible to determine 1%. It can be equivalent to pointing the pointing direction in the direction.

In such a case, the phases of the local oscillator signals to each mixing circuit may be made to differ by a certain amount sequentially in advance.

Further, in this embodiment, the gate depth can be adjusted manually using the gate depth setting device 12. , the gate width △L was set, but the gate depth increased due to the following effect. can be set automatically. That is, for example R,0M18
The column address of the row in which the latest information is sent from or written in the display memory 19, and the number of items in the first row is
For example, if it is 2n/3 or more, the gate depth L0
is changed to Lo (ΔL/2), and conversely, if the number of elements in the 8th stage becomes 2n/3 or more, the gate depth is increased. Ori. Change it to 10 (ΔL/2).

This uses a counting circuit to send out a match signal when the numbers in the first and eighth stages match 2n/3, and change the gate depth by (Δx'2) based on the match signal. Just do it like this. As a result, the actual sea floor is gate width ΔL
If there is a tendency to deviate from this, the gate width will be automatically changed in the depth direction to track this.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a diagram for explaining the relationship between the transmission beam width and the seabed prediction gate of the present invention.

Claims (1)

[Claims] A plurality of transducers are arranged to transmit ultrasonic pulses with a transmitting beam width ψ into the sea, and the reflected waves from the seabed are received as receiving beams with a receiving beam width ψ/n. a first memory having a storage capacity for multiple rows in the depth direction and n columns in the reception direction for storing the received signal; and a first memory storing the received signal in a scanning manner; a first write address generation circuit that starts and forms the row and column write addresses of the first memory in synchronization with the scanning of the receiving beam; and a gate setting circuit that sets the seafloor prediction gate and gate width. and a first read address generation circuit that reads out the received signal in the depth direction row address corresponding to the set gate from the first memory based on the gate setting value for each column address, and each of the above read addresses. Extracting means for extracting the seabed existing row address at each column address from the column address signal, and moving the extracted seabed existing row address to a value based on the start address of the depthwise row address corresponding to the setting gate. The means of transportation and the maximum possible value of the means of transportation are divided in advance into multiple stages,
a converting means for converting the output value of the moving means for each column address into a value for the corresponding stage; a second memory for storing the moving means output value (or the converting means output value) for each column address; reading means for reading out the stored contents of the second memory in column address order at a time timing proportional to a change in the horizontal distance component corresponding to a change in the beam pointing direction; ), the third memory has a storage capacity of multiple rows in the temporal direction and n columns in the direction of wave reception direction, and a second write address generation forming the row and column Toyogome addresses of the third memory. circuit, and the row address information of the 20th write address generation circuit described above.
By forming a read row address of the memory, a second read address is generated that forms a row and column read address in which reading is always performed from the row address where new information is stored in the direction of the older row address. a color signal conversion circuit that converts a third memory output value into a color signal; a display having pixels corresponding to the number of rows and columns of the third memory; and a second read address generation circuit. A submarine map creation and display device comprising a deflection circuit that performs a raster sweep of rows and columns in synchronization with row and column readout address formation and displays the output of the color signal conversion circuit on the display.