JPS5994885A - Photoelectric conversion device - Google Patents

Photoelectric conversion device

Info

Publication number
JPS5994885A
JPS5994885A JP57206806A JP20680682A JPS5994885A JP S5994885 A JPS5994885 A JP S5994885A JP 57206806 A JP57206806 A JP 57206806A JP 20680682 A JP20680682 A JP 20680682A JP S5994885 A JPS5994885 A JP S5994885A
Authority
JP
Japan
Prior art keywords
electrode
photoelectric conversion
conversion device
semiconductor
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57206806A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP57206806A priority Critical patent/JPS5994885A/en
Priority to US06/554,762 priority patent/US4529829A/en
Priority to US06/554,763 priority patent/US4593152A/en
Priority to US06/554,807 priority patent/US4527006A/en
Priority to GB08331396A priority patent/GB2133214B/en
Priority to AU21658/83A priority patent/AU553135B2/en
Priority to GB08331330A priority patent/GB2133213B/en
Priority to KR1019830005594A priority patent/KR900004823B1/en
Priority to EP83307192A priority patent/EP0113959B1/en
Priority to GB08331397A priority patent/GB2133215B/en
Priority to EP83307191A priority patent/EP0111402B1/en
Priority to DE83307191T priority patent/DE3382709T2/en
Priority to DE8383307192T priority patent/DE3382695T2/en
Priority to AU21659/83A priority patent/AU554459B2/en
Priority to GB08331398A priority patent/GB2133617B/en
Priority to KR1019830005552A priority patent/KR900004824B1/en
Priority to US06/555,317 priority patent/US4518815A/en
Publication of JPS5994885A publication Critical patent/JPS5994885A/en
Priority to US06/620,177 priority patent/US4710397A/en
Priority to US06/620,171 priority patent/US4670294A/en
Priority to US06/620,098 priority patent/US4586241A/en
Priority to US06/620,462 priority patent/US4528065A/en
Priority to US06/760,873 priority patent/US4638108A/en
Priority to US06/760,957 priority patent/US4593151A/en
Priority to US06/776,806 priority patent/US4631801A/en
Priority to US06/846,514 priority patent/US4686760A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/107Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays

Landscapes

  • Light Receiving Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は、P工NまたはPN接合を少なくとも1つ有
するアモルファス半導体を含む非単結晶半導体を透光性
絶縁基板上に設けられた光電変換素子(単に素子ともい
う)を複数個直列接続して、病い電圧の発生が可能な光
電変換装置およびその作製方法に関する。
Detailed Description of the Invention The present invention provides a photoelectric conversion element (also simply referred to as an element) in which a non-single crystal semiconductor including an amorphous semiconductor having at least one P-N or PN junction is provided on a light-transmitting insulating substrate. The present invention relates to a photoelectric conversion device capable of generating an abnormal voltage by connecting a plurality of photoelectric conversion devices in series, and a method for manufacturing the same.

この発明は、複数の素子間の連結に必要な面積を従来の
マスク合わせ方式の1/10〜1/100にするため、
レーザスクライブ方法を用いたことを特徴としている。
This invention reduces the area required for connecting multiple elements to 1/10 to 1/100 of the conventional mask alignment method.
It is characterized by using a laser scribing method.

この発明は、連結部での電気的接合t−電極を構成する
被膜の載面ではなく、側面を用いることにより、連結部
での必要面積全減少せしめたことを特徴としている0 この発明では、従来マスク合わせ方式においてその連結
部は5〜1mmを必要としていたが、これをその1/1
0〜1/100の350〜30μ好ましくは変換装置と
して用いられる全パネルの光起電力見上せしめたことを
特徴とする。
This invention is characterized in that by using the side surface of the coating constituting the electrical connection t-electrode at the connection portion, rather than the mounting surface, the total area required at the connection portion is reduced. In the conventional mask alignment method, the connection part required 5 to 1 mm, but this has been reduced to 1/1 of that.
It is characterized in that the photovoltaic power of the entire panel used as a conversion device is preferably 0 to 1/100 350 to 30μ.

この発明ではレーザビームスクライブ方式を用いること
によシ、合せマークを基準としてこのスクライブ’% 
24N ’+アドレスをあらかじめコンピュータ(マイ
クロ・コンピュータ)のメモリに記憶させておくtとに
よム従来よシ知らbたマスク合わせ方式で必要なマクス
の1れ、そシ、合せ精度に対する製造歩留シの低下等の
すべての製造での価格増、歩留シ減の原因を一気に排除
せしめたことを特徴とする。
In this invention, by using a laser beam scribing method, this scribe'% is calculated based on the alignment mark.
By storing the 24N '+ address in the memory of a computer (microcomputer) in advance, the mask alignment required in the conventionally known mask alignment method, and the manufacturing yield for alignment accuracy. It is characterized by eliminating all causes of price increases and yield reductions in manufacturing at once, such as reductions in yield.

従来、光電変換装置(以下単に装置という)即ち同一基
板上に複数の素子を配置し、それを集積化またはハイブ
リッド化した装置はその実施例が多く知られている。
Conventionally, many examples of photoelectric conversion devices (hereinafter simply referred to as devices), that is, devices in which a plurality of elements are arranged on the same substrate and are integrated or hybridized, are known.

例えば特開昭55−4994、特開昭55−12427
4さらに本発明人の出願になる特願昭54−90097
/90098/90099 (昭和54. ’/、 ’
16出願)が知られている。特にこの本発明人の出願は
、半導体を5iO−8117)へテロ接合とし、単に他
のアモルファスシリコン半導体を用いる場合と異ならせ
ておシさらにこの半導体として、アモルファス構造以外
に微結晶構造を含む水素またはハロゲン元素が添加され
たPNまたはPIN接合を少なくとも1つ有する非単結
晶半導体であるという特徴を有する。
For example, JP-A-55-4994, JP-A-55-12427
4 Furthermore, patent application No. 54-90097 filed by the present inventor
/90098/90099 (Showa 54. '/, '
16 applications) are known. In particular, this application by the present inventor uses a 5iO-8117) heterojunction as a semiconductor, which is different from the case where other amorphous silicon semiconductors are used. Alternatively, it is characterized by being a non-single crystal semiconductor having at least one PN or PIN junction to which a halogen element is added.

しかしこれら従来の発明においては、第1図にそのたて
断面図を示すが、すべてマスク合せ方式であシ、合せ精
度が不十分であり、また連結部に大きな面積を必要とし
ていた。
However, in these conventional inventions, as shown in FIG. 1, which is a vertical cross-sectional view, all of them are based on the mask alignment method, and the alignment accuracy is insufficient, and a large area is required for the connecting portion.

例えば金属マスクを用い、直接選択的に導電層または半
導体層を作製する方式においては、この選択性を与えた
マスクが被膜形成中K O,5〜3mmずれてしまう場
合がある。さらにこのマスク上に被膜成分が形成される
ため、マスクが汚染され、またマスクがそって形成され
る被膜の側埠部が明瞭でなくなる等多くの欠点を有する
For example, in a method of directly and selectively manufacturing a conductive layer or a semiconductor layer using a metal mask, the mask that provides this selectivity may shift by 5 to 3 mm during film formation. Furthermore, since a coating component is formed on the mask, there are many disadvantages such as contamination of the mask and obscurity of the side walls of the coating formed by the mask.

さらにスクリーン印刷法等の基板上に全体的に形成され
た導体または半導体を独立に選択的にマスクを用いてエ
ツチング除去する方法が知られている。しかしかかる方
法においては、スクリーン印刷用のマスクの位置合わせ
の工程、レジストのコーティング工程、ベーク固化工程
、導体または半導体のエツチング工程、レジストの除去
工程等きわめて工程に時間がかかシ、そのため製造価格
上昇がまぬがれ得なかった。
Further, a method such as a screen printing method is known in which conductors or semiconductors formed entirely on a substrate are independently and selectively etched away using a mask. However, in this method, the process is extremely time consuming, such as the process of aligning the mask for screen printing, the process of coating the resist, the process of baking and solidifying, the process of etching the conductor or semiconductor, and the process of removing the resist. The rise was inevitable.

しかし本発明の光電変換装置特に薄膜型の光電変換装置
にあっては、それぞれの薄膜層である電極用導電性層、
また半導体層はともK 500X〜1μでアシ、レーザ
スクライブ方式を用いることにより、全くマスク合わせ
を必要としないことが判明した。
However, in the photoelectric conversion device of the present invention, particularly in the thin film type photoelectric conversion device, the conductive layer for electrodes, which is each thin film layer,
Furthermore, it has been found that by using a laser scribing method in which the semiconductor layers are both reeded at K500X to 1μ, mask alignment is not required at all.

その結果従来のマスク合わせ工程のかわシに本発8Aに
おいてはマスクを全く用いないためスクライブ工程とい
うが、このスクライブ工程がきわめて簡単でちるため、
装置の製造コストの低下金もるというきわめて画期的な
光電変換装置を提供することKある。
As a result, in contrast to the conventional mask alignment process, this 8A does not use any masks at all, so it is called a scribing process, but since this scribing process is extremely simple and easy,
It is an object of the present invention to provide an extremely innovative photoelectric conversion device that reduces the manufacturing cost of the device and saves money.

さらに本発明はこのレーザスクライブ工程を用いるに加
えて、そのスクライブラインの合せ精度に冗長(余裕)
度をもたせたことが重要である。
Furthermore, in addition to using this laser scribing process, the present invention has a redundancy (margin) in the alignment accuracy of the scribe line.
It is important to have a degree of precision.

そのため隣シ合った素子間の第1の電極(下側)と他の
素子の第2の電極(上側電極)とが第1の電極の側面に
おいて電気的に連結されることによシ、スクライプライ
ンの開溝の位置に冗長度をもたせることができた。
Therefore, the first electrode (lower side) between adjacent elements and the second electrode (upper electrode) of the other element are electrically connected on the side surface of the first electrode, thereby making it possible to scrub. It was possible to provide redundancy in the position of the opening groove of the pipeline.

以下に図面に従って従来例および本発明の構造を記す。A conventional example and the structure of the present invention will be described below according to the drawings.

第1図は従来より知られたマスク合せ方式の光電変換装
置のたて断面図である。
FIG. 1 is a vertical sectional view of a conventionally known photoelectric conversion device using a mask alignment method.

図面において透光性基板(例えばガラス板)(1)上に
第1の電極を構成する透光性導電膜(○TFと略記する
)を第1のマスク合わせ工程によシ選択的に形成させる
。さらに半導体層(3)を第2のマスク合わせ工程によ
υ同様に選択的に形成させる。
In the drawings, a transparent conductive film (abbreviated as ○TF) constituting the first electrode is selectively formed on a transparent substrate (for example, a glass plate) (1) by a first mask alignment step. . Further, a semiconductor layer (3) is selectively formed in the same manner as υ by a second mask alignment step.

さらに第3のマスク合せ工程によυ第2の電極りが設け
られている0 第1図において素子α11(31)との間に連結部(2
)を有し、連結部においてはOTFの一方の側面α→を
mm例えは3mmのす門まを必要とする。さらに第1の
電極(3’7)と第2の電極(38)はHの表面で電気
的に連結するが、この部分をG59)の第2の電極がマ
スクのぼけで発生するひるがシをも含めてショートシて
はいけないため1〜5mm例えば3mmの間隙(6)を
必要とする0これら3つのマスクには全くのセルファラ
イン性がないため、連結部(ロ)においては1〜8mm
代表的には4mmを必要としτしまうOさらにこれに’
1mm以下とすると、そのマスク合わせ精度はきわめて
唇鴛でちゃ、歩留シが極端に低下してしまう。この連結
部(6)の間隙”t 5mm以上とすると、例えば20
cmX60cm K巾15mmの素子有効面積は周辺部
を考慮すると75%Oでとどまってしまっていた。
Further, in the third mask alignment process, a υ second electrode is provided. In FIG. 1, a connecting portion (2
), and in the connection part, one side α→ of the OTF requires a gate with a diameter of mm, for example, 3 mm. Furthermore, the first electrode (3'7) and the second electrode (38) are electrically connected on the surface of H, but this part is connected to the second electrode of G59) to prevent flickering caused by blurring of the mask. A gap (6) of 1 to 5 mm, for example 3 mm, is required to avoid short-circuiting including
Typically, 4 mm is required, and furthermore,
If it is less than 1 mm, the mask alignment accuracy will be extremely poor and the yield will be extremely reduced. If the gap "t" of this connecting part (6) is set to 5 mm or more, for example, 20
The effective area of a device of cm x 60 cm and K width of 15 mm remained at 75% O when the peripheral area was taken into consideration.

本発明はかかる工程の複雑さを排除し、有効面積が85
〜9フチ例えば92%にまで高めることができるという
きわめて画期的な光電変換装置を提供することKある。
The present invention eliminates such process complexity and reduces the effective area to 85.
It is an object of the present invention to provide an extremely innovative photoelectric conversion device that can increase the conversion rate by up to 92%, for example.

以下に図面に従ってその詳細を示す。The details are shown below according to the drawings.

第2図は本発明の製造工程を示すたて断面図である。FIG. 2 is a vertical sectional view showing the manufacturing process of the present invention.

図面において透光性基板(1)例えばガラス板(例えば
厚さ1.2 m m>長さく図面では左右方向)60c
m。
In the drawing, a transparent substrate (1), for example, a glass plate (for example, thickness 1.2 mm, length in left and right direction in the drawing) 60c
m.

巾20am)を用いた。さらにこの上面に全面にわたっ
て透光性導電膜例えば工To(1500λ)+SnO□
(200〜400 X)またはハロゲン元素が添加され
た酸化スズを主成分とする透光性導電膜(1500〜2
000 K)を真空蒸着法、LFOVD法−1次はプラ
ズマOVD法またはスプレー法によシ形成させた。
A width of 20 am) was used. Furthermore, a light-transmitting conductive film is applied to the entire upper surface, for example, To (1500λ) + SnO□
(200 to 400
000 K) was formed by a vacuum evaporation method, and the LFOVD method - the first step was formed by a plasma OVD method or a spray method.

この後この基板の下側″!、たけ上側によシYAGレー
ザ加工J曙(日本レーザl!りKよシ出力5〜8W出力
を加え、スボツ)V30〜70p#代表的にはスクライ
ビングにより形成された開溝は、巾約50μ長さ20c
mとし、各素子(31)、(l])を構成する巾は10
〜20mm例えば15mm (1つのセグメントは’1
5mmX20cmとする)とした0かくして第1の電極
を巻成するO T y (2)を切断分離して開溝を形
成した。この後この上面にプラズマOVD法またはLP
OVD法によ#)FNまたはP工N接合を有する非単結
晶半導体層を0.2〜0.7μ代表的には0.4〜0.
5μの厚さに形成させた。その代表例はP型半導体(S
ixO,−4x=0.250〜150わ−1型アモルフ
ァスまたはセミアモルファスシリコン半導体(0,4〜
0.5μ)−N型の微結晶(100〜200λ)を有す
る半導体よりなる1つのP工N接合を有する非単結晶半
導体、まンtはP型半導体(s 1x cL−J−N型
、P型B1半導体−工型81xGe、、半導体−N型8
1半導体よりなる2つのP工N接合と1つのPN接合を
有するタンデム型のPINP工N・・・・PIN接合の
半導体である。
After this, YAG laser processing is performed on the lower side of this substrate and the upper side. The opened groove is approximately 50μ in width and 20cm in length.
m, and the width of each element (31), (l]) is 10
~20mm e.g. 15mm (one segment is '1
Thus, O T y (2) forming the first electrode was cut and separated to form an open groove. After that, apply plasma OVD or LP to this upper surface.
A non-single crystal semiconductor layer having an FN or P-N junction is formed by the OVD method to a thickness of 0.2 to 0.7μ, typically 0.4 to 0.0μ.
It was formed to a thickness of 5μ. A typical example is a P-type semiconductor (S
ixO,-4x=0.250~150W-1 type amorphous or semi-amorphous silicon semiconductor (0,4~
0.5μ) - A non-single crystal semiconductor with one P-N junction consisting of a semiconductor with N-type microcrystals (100-200λ), Mant is a P-type semiconductor (s 1x cL-J-N type, P type B1 semiconductor - type 81xGe,, semiconductor - N type 8
A tandem type PINP-N having two P-N junctions and one PN junction made of one semiconductor is a PIN junction semiconductor.

かかる非単結晶半導体層(3)を全面に均一の膜厚で形
成させた。さらに第2図(B) K示される如く、第1
の開溝の在方向に第2の開溝Q8を第2のV −ザスク
ライブ工程により形成させた。このレーザはガラス(1
)の下方向またはこの基板の上方のいずれから行なって
もよい。
Such a non-single crystal semiconductor layer (3) was formed to have a uniform thickness over the entire surface. Furthermore, as shown in Figure 2 (B) K, the first
A second open groove Q8 was formed in the direction of the open groove by a second V-za scribing step. This laser is made of glass (1
) or above the substrate.

かくして第2の開溝0枠は第1の電極の側面を暢(9)
を露出させた。この第2の開溝の側面(9)は第1の電
極0Qの側面Hよりl側であればよく、その極端な例と
して、図面に示される如く、第1の電極(31)の内部
に入ってしまってもよい。さらに従来例に示される如く
、第1の電極の表面α喧を露呈させることは必ずしも必
要ではなく、レーザ光が5〜IOWで多少はtq−15
、このOTFをすべて除去してしまりt側面(第2図(
B))であっても何ら実用上問題はない。即ちレーザ光
の出力パルスの強さに余裕を与えることができることが
本発明の工業的応用の際きわめて重要である。
Thus, the second open groove 0 frame extends along the side surface of the first electrode (9).
exposed. The side surface (9) of this second groove may be on the l side from the side surface H of the first electrode 0Q, and as an extreme example, as shown in the drawing, the side surface (9) of the second groove may be located inside the first electrode (31). It's okay to go in. Furthermore, as shown in the conventional example, it is not necessarily necessary to expose the surface α of the first electrode;
, this OTF is completely removed and the t side (Fig. 2 (
B)) There is no practical problem. That is, it is extremely important for the industrial application of the present invention to be able to provide a margin for the intensity of the output pulse of the laser beam.

第2図において、さらにこの上面に第2図(0)K示さ
れる如く、裏面電極を形成し、さらに第3のレーザスク
ライブ法の切断分離用の開nに)を設けた0 この第2の電極は透光性導電膜をフOO〜1400^工
TO(酸化インジュームスズ)を形成し、さらにその上
面に銀を300〜3000″にの厚さに形成し、さらに
その上面にアルミニュームまたはアルミニュームとニッ
ケルとの二層膜を形成させた。例えば工Toを1050
1、銀を1000^、さらにニッケルの長波、光を有効
え光査、換す、えゎ。も、鷲する。さらにニッケルは外
部引出し電極(2)との密着性を向上させるためのもの
である。これらは電子ビーム蒸着法またはプラズマ気相
法を用いて半導体層を劣化させる3 00’O以下の温
度で形成させた。
In FIG. 2, a back electrode is further formed on this top surface as shown in FIG. The electrodes are made by forming a transparent conductive film of FOO~1400~TO (indium tin oxide), then forming silver to a thickness of 300~3000'' on the upper surface, and then coating aluminum or aluminum on the upper surface. A double layer film of aluminum and nickel was formed.For example, 1050
1. Convert silver to 1000^, then nickel's long wave, effectively scan and convert it. Also, eagle. Furthermore, nickel is used to improve adhesion to the external lead electrode (2). These were formed using an electron beam evaporation method or a plasma vapor phase method at a temperature of 300'O or less, which degrades the semiconductor layer.

この工TOは半導体とifhそIiとの反応による−)
性の向上にも役立っている。
This TO is due to the reaction between the semiconductor and ifhsoIi-)
It also helps improve sexuality.

かくの如き裏面電極をレーザ光を上方よシ照射した場合
を以上においては示している。このレーザ光は半導体層
を少しえぐり出し喝7 J Jわ素子(31)ノ 0璋間の開溝部での残存金属によるリークの発生を防止
した。このえぐシ出しは第1の電極用のOTFある。
The above example shows a case in which such a back electrode is irradiated upward with laser light. This laser beam slightly gouged out the semiconductor layer to prevent leakage due to residual metal in the groove between the elements (31) and 0. This ejector is an OTF for the first electrode.

かくして第2図(c) K示される如く、複敬の素子(
3υ、(2)を連結部(2)で直列接続する光電変換装
置を作ることができた。
Thus, as shown in Fig. 2(c), the double-respect element (
We were able to create a photoelectric conversion device in which 3υ, (2) were connected in series at the connecting part (2).

第2図(9)はさらに本発明を光電変換装置として完成
させんとしたものであシ、即ちパッシベーション膜とし
てプラズマ気相法によりm化珪素膜Q)を500〜2o
ooiの厚さに形成した。さらに外部引出し端子(至)
を周辺部(5)Kて設けた。これらにボリミイド、ポリ
アミド、カプトンまたはエポキシ等の有機樹脂に)を充
填した。
FIG. 2 (9) shows the attempt to further complete the present invention as a photoelectric conversion device. That is, as a passivation film, a silicon oxide film Q) of 50 to 2
It was formed to a thickness of ooi. In addition, external extraction terminal (to)
was provided at the peripheral part (5)K. These were filled with organic resins such as bolimide, polyamide, kapton or epoxy).

かくして照射光(1o)K対しこの実施例の如き基板(
60cmX20cm) において各素子を14.35m
m。
Thus, for the irradiated light (1o) K, the substrate (
60cm x 20cm), each element is 14.35m
m.

連結部150μ外部引出し電極部10mm周辺部4nu
nによシ実質的K 580mmX19gmm内に40段
を有し有効面積(19YmmX14.3ommx4oa
−xxo84倉m即ち91.s%)を得ることができf
Coその結果セグメントが10.6%の変換効率を有す
る場合、パネルにて9.7%(AM l (100mW
/a a) Kて11.6Wの出力電力を有せしめるこ
とができた。
Connection part 150μ External extraction electrode part 10mm Peripheral part 4nu
Effective area (19Ymm x 14.3omx 4oa) with 40 stages within 580mm x 19gmm
-xxo84 warehouses, ie 91. s%) can be obtained f
If the resulting Co segment has a conversion efficiency of 10.6%, then at the panel 9.7% (AM l (100 mW
/a a) K was able to provide an output power of 11.6W.

これは従来のマスク合せ方式で行なった場合のパネルの
製造工程において何らの工業上の支障がなく、大電力発
生用の大面積低価格大量生産用にきわめて適している。
This does not cause any industrial problems in the panel manufacturing process when carried out using the conventional mask matching method, and is extremely suitable for large-area, low-cost mass production for generating large amounts of power.

さらに第2図@において、レーザ出力を強めにすると、
開溝部の周辺の切れがよいが、この際下部を多少損傷し
ても実用上全く問題はない。
Furthermore, in Figure 2 @, if the laser output is increased,
The cutting around the opening groove is good, but there is no practical problem even if the lower part is slightly damaged.

特に第1の電極と第2の電極との電気的連結を第1の電
極の側部で行なうことができるため、このコンタクト部
の面積を十分少なくさせることができた。
In particular, since the first electrode and the second electrode can be electrically connected at the side of the first electrode, the area of the contact portion can be sufficiently reduced.

また第2図(B) K示しであるが、半導体層(3)の
レーザスクライブを1本の開溝線とすると、電極は(3
2)のみとなるが、これに問史的にぢ工【 Ω3)の電
流をさらに有効に利用することも可能である0第3図、
第4図、第6図は3回のレーザスクライブの位置関係を
示したたて断面図およびたく平面図でおる。番号等は第
2図と同様である。
In addition, as shown in FIG. 2(B) K, if the laser scribe of the semiconductor layer (3) is one groove line, the electrode will be (3
2), but historically it is also possible to use the electric current of Ω3 more effectively.
FIGS. 4 and 6 are a vertical sectional view and a vertical plan view showing the positional relationship of three laser scribes. Numbers etc. are the same as in FIG. 2.

第3図は連結部(6)において第2のレーザスフ2イプ
工程を基板の上方より行ない、開溝部りにおいて第1の
電極のOTFの一部を残存させた場合である。溢に図(
B)の平面図においては、半導体層(場が第1の電極(
2)、第2の電極よシも周辺部で大きくな林第1の電極
をおおいかくシ、それらの電極間でのリーク電流の発生
を防止している。
FIG. 3 shows a case where the second laser swiping step is performed from above the substrate at the connecting portion (6), leaving a portion of the OTF of the first electrode at the open groove portion. Overflowing diagram (
In the plan view of B), the semiconductor layer (the field is connected to the first electrode (
2) The second electrode also covers the large first electrode at the periphery to prevent leakage current between these electrodes.

第4図は第1の開溝部α埠、第2の開溝部Q樟とが部に
必要なロス面積を最少にしたもので)100μまたは6
0μの連結部を有せしめることができた。
In Figure 4, the loss area required for the first open groove part α and the second open groove part Q is minimized (100μ or 6).
It was possible to have a connection portion of 0μ.

第5図は第3図、第4図の中間で、一般的な連結部のた
て断面図を示している。この図面において第1、第2の
開溝部50〜30μ、第3の開溝部75〜50μにおい
て、160μ〜100μの連結部の巾を有せしめること
ができた。
FIG. 5 is located midway between FIGS. 3 and 4, and shows a vertical sectional view of a typical connecting portion. In this drawing, the width of the connecting portion was 160 μ to 100 μ in the first and second open groove portions 50 to 30 μ and the third open groove portion 75 to 50 μ.

以上のYAGレーザのスポット層をその出力3〜の連結
部をよシ小さく、ひいては光電変換装置としての有効面
積を向上させることができた0第6図は外部引出し電極
部を拡大して示したものである。
The spot layer of the YAG laser as described above can be made smaller than the connecting part between its outputs 3 and 3, thereby improving the effective area as a photoelectric conversion device.0 Figure 6 shows an enlarged view of the external extraction electrode part. It is something.

第6図(4)は第2図に対応しているが、外部引出し電
極(5)はハンダ付(42)Kよシ土側電極(4)と連
結している。さらに第6図φ)は下側の第1の電極に連
結したジヨイント04)が第2の電極材料によシ設けら
れ、ハンダ02)を介して外部引出し電極(43)によ
シ設けられ1いる。本来の第2の電極(4)は第3の開
溝部(イ)によシ切断され、その切断面は窒化珪素膜に
よりパッシベーションされている。
FIG. 6(4) corresponds to FIG. 2, but the external lead electrode (5) is connected to the soldered electrode (42) and the ground side electrode (4). Further, in Fig. 6 φ), a joint 04) connected to the first electrode on the lower side is provided on the second electrode material, and is provided on the external lead electrode (43) via solder 02). There is. The original second electrode (4) is cut by the third groove (a), and the cut surface is passivated with a silicon nitride film.

鉱憶樹脂モールド(2)は引出し電極(5)、(4り固
定用におおわれておシ、さらにこのパネル例えば40(
+mX240amまたは60cmX20amを6ケまた
は4ケ直1fq Kアルミサツシ枠によシパッケージさ
れ、120cmX40cm +7) NID0規格のパ
ネルを設けることが可能である。
The mineral memory resin mold (2) is covered with a lead electrode (5), (4) for fixing, and this panel is further covered with, for example, 40 (40).
It is possible to package +mX240am or 60cmX20am into 6 or 4 straight 1fq K aluminum sash frames, and provide a 120cmX40cm +7) NID0 standard panel.

またとのNBDO規格のパネルはシーフレックスにより
他のガラス板を!置の上側には知1′)ぜた合わせガラ
スとし、その間に光電変換装置を配置ω し、葛1等に対しすへ禎゛強度の増加をはかることを有
効である。
Also, the NBDO standard panel can be used with other glass plates by Seaflex! It is effective to use laminated glass on the upper side of the structure and place a photoelectric conversion device between them to increase the strength of the structure.

第2図〜第6図において光入射は下側のガラス板よシと
した。しかし本発明はその光入射側を下側に限定するも
のではない。
In FIGS. 2 to 6, light was incident through the lower glass plate. However, the present invention does not limit the light incident side to the lower side.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の光電変換装置のたてめi面図である0 第2図は本発明の光電変換装置の製造工程を示すたて断
面図である。 第3図〜第6図は本発明の光電変換装置の部分の拡大図
である。 0 犀1(刀
FIG. 1 is a vertical i-plane view of a conventional photoelectric conversion device. FIG. 2 is a vertical sectional view showing the manufacturing process of the photoelectric conversion device of the present invention. 3 to 6 are enlarged views of portions of the photoelectric conversion device of the present invention. 0 Sai 1 (sword)

Claims (1)

【特許請求の範囲】 1、絶縁基板上に透光性導電膜よシなる第1の−電極と
、該電極をおおってPNまたはP工N接合を少なくとも
1つ有する非単結晶半導体と、該半導体上に第2の電極
とを有する光電変換装置を複数個電気的に連結せしめて
前記絶縁基板上に配設した光電変換装置において、隣シ
に配置した第1および第2の光電変換装置における第1
の光電変換装置の第2の電極は連結部をへて第10光電
変換装置の第1の電設けられたことを特徴とする光電変
換装置。 2、特許請求の範囲第1項において、連結部は350〜
30μの巾を脣することを特徴とする充電変換装置。 (1)
[Claims] 1. A first electrode made of a transparent conductive film on an insulating substrate, a non-single crystal semiconductor having at least one PN or P-N junction covering the electrode; In a photoelectric conversion device in which a plurality of photoelectric conversion devices each having a second electrode on a semiconductor are electrically connected and arranged on the insulating substrate, the first and second photoelectric conversion devices are arranged next to each other. 1st
A photoelectric conversion device characterized in that the second electrode of the photoelectric conversion device is connected to the first electrode of the tenth photoelectric conversion device through a connecting portion. 2. In claim 1, the connecting portion is 350~
A charging conversion device characterized by having a width of 30μ. (1)
JP57206806A 1982-11-24 1982-11-24 Photoelectric conversion device Pending JPS5994885A (en)

Priority Applications (25)

Application Number Priority Date Filing Date Title
JP57206806A JPS5994885A (en) 1982-11-24 1982-11-24 Photoelectric conversion device
US06/554,762 US4529829A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
US06/554,763 US4593152A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
US06/554,807 US4527006A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
AU21659/83A AU554459B2 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
KR1019830005552A KR900004824B1 (en) 1982-11-24 1983-11-24 Photoelectric conversion device and manufacturing method thereof
GB08331330A GB2133213B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and method of manufacturing the same
KR1019830005594A KR900004823B1 (en) 1982-11-24 1983-11-24 Photo electronic conversion device and manufacturing method thereof
EP83307192A EP0113959B1 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
GB08331397A GB2133215B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and its manufacturing method
EP83307191A EP0111402B1 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
DE83307191T DE3382709T2 (en) 1982-11-24 1983-11-24 Photovoltaic converter.
DE8383307192T DE3382695T2 (en) 1982-11-24 1983-11-24 PHOTOVOLTAIC CONVERTER.
GB08331396A GB2133214B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and its manufacturing method
GB08331398A GB2133617B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and method of manufacture
AU21658/83A AU553135B2 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
US06/555,317 US4518815A (en) 1982-11-24 1983-11-25 Photoelectric conversion device
US06/620,177 US4710397A (en) 1982-11-24 1984-06-13 Photoelectric conversion device and its manufacturing method
US06/620,171 US4670294A (en) 1982-11-24 1984-06-13 Photoelectric conversion device and its manufacturing method
US06/620,098 US4586241A (en) 1982-11-24 1984-06-13 Photoelectric conversion device manufacturing method
US06/620,462 US4528065A (en) 1982-11-24 1984-06-14 Photoelectric conversion device and its manufacturing method
US06/760,873 US4638108A (en) 1982-11-24 1985-07-31 Photoelectric conversion device
US06/760,957 US4593151A (en) 1982-11-24 1985-07-31 Photoelectric conversion device
US06/776,806 US4631801A (en) 1982-11-24 1985-09-17 Method of making photoelectric conversion device
US06/846,514 US4686760A (en) 1982-11-24 1986-03-31 Method of making photoelectric conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57206806A JPS5994885A (en) 1982-11-24 1982-11-24 Photoelectric conversion device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP62281674A Division JPS63146473A (en) 1987-11-07 1987-11-07 Photoelectric conversion device
JP62281675A Division JPS63146474A (en) 1987-11-07 1987-11-07 Manufacture of photoelectric conversion device

Publications (1)

Publication Number Publication Date
JPS5994885A true JPS5994885A (en) 1984-05-31

Family

ID=16529393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57206806A Pending JPS5994885A (en) 1982-11-24 1982-11-24 Photoelectric conversion device

Country Status (1)

Country Link
JP (1) JPS5994885A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210681A (en) * 1986-02-20 1986-09-18 Sanyo Electric Co Ltd Manufacture of photovoltaic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130777A (en) * 1980-03-18 1981-10-13 Copyer Co Ltd Transfer device of copying machine
JPS57176778A (en) * 1981-03-31 1982-10-30 Rca Corp Solar battery array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130777A (en) * 1980-03-18 1981-10-13 Copyer Co Ltd Transfer device of copying machine
JPS57176778A (en) * 1981-03-31 1982-10-30 Rca Corp Solar battery array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210681A (en) * 1986-02-20 1986-09-18 Sanyo Electric Co Ltd Manufacture of photovoltaic device

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