JPS599552U - Hybrid thick film integrated circuit - Google Patents

Hybrid thick film integrated circuit

Info

Publication number
JPS599552U
JPS599552U JP10326982U JP10326982U JPS599552U JP S599552 U JPS599552 U JP S599552U JP 10326982 U JP10326982 U JP 10326982U JP 10326982 U JP10326982 U JP 10326982U JP S599552 U JPS599552 U JP S599552U
Authority
JP
Japan
Prior art keywords
thick film
integrated circuit
circuit boards
clip
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10326982U
Other languages
Japanese (ja)
Inventor
矢萩　覚
角田　完爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10326982U priority Critical patent/JPS599552U/en
Publication of JPS599552U publication Critical patent/JPS599552U/en
Pending legal-status Critical Current

Links

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の混成厚膜集積回路の断面図、第２図は本
考案による混成厚膜集積回路の一実施例の断面図を示す
。 １・・・表基板、１′・・・裏基板、２．２′・・・搭
載部品、５・・・樹−コート、７，７′・・・半田又は
導電性接着剤、８・・・クリップ式リード。FIG. 1 is a sectional view of a conventional hybrid thick film integrated circuit, and FIG. 2 is a sectional view of an embodiment of the hybrid thick film integrated circuit according to the present invention. DESCRIPTION OF SYMBOLS 1...Top board, 1'...Back board, 2.2'...Mounted components, 5...Tree coat, 7,7'...Solder or conductive adhesive, 8...・Clip type lead.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）セラミック基板上に、導体、抵抗を印刷焼成した
２個の厚膜回路基板、該厚膜回路基板上に取付けられた
部品、背合せにされた前記２個の厚膜回路基板を挟着す
るクリップ式リード、該クリップ式リードのクリップ部
と前記厚膜回路基板との接触部に設けられた半田又は導
電性接着剤、および前記２個の背合せにされた厚膜回路
基板を包む樹脂コートを具備したことを特徴とする混成
厚膜集積回路。(1) Two thick film circuit boards with conductors and resistors printed and fired on ceramic substrates, parts mounted on the thick film circuit boards, and the two thick film circuit boards placed back to back. a clip-on lead to be attached, a solder or conductive adhesive provided at a contact portion between the clip portion of the clip-on lead and the thick film circuit board, and the two thick film circuit boards placed back to back. A hybrid thick film integrated circuit characterized by having a resin coat. （２）　　前記２個の厚膜回路基板は、前記クリップ式
リードで回路的に接続されていることを特徴とする前記
実用新案登録請求の範囲第１項記載の混成厚膜集積回路
。(2) The hybrid thick-film integrated circuit according to claim 1, wherein the two thick-film circuit boards are circuit-connected by the clip-type leads.
JP10326982U 1982-07-09 1982-07-09 Hybrid thick film integrated circuit Pending JPS599552U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10326982U JPS599552U (en) 1982-07-09 1982-07-09 Hybrid thick film integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10326982U JPS599552U (en) 1982-07-09 1982-07-09 Hybrid thick film integrated circuit

Publications (1)

Publication Number Publication Date
JPS599552U true JPS599552U (en) 1984-01-21

Family

ID=30243035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10326982U Pending JPS599552U (en) 1982-07-09 1982-07-09 Hybrid thick film integrated circuit

Country Status (1)

Country Link
JP (1) JPS599552U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS614463U (en) * 1984-06-15 1986-01-11 富士通テン株式会社 hybrid integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5747043B2 (en) * 1978-05-10 1982-10-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5747043B2 (en) * 1978-05-10 1982-10-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS614463U (en) * 1984-06-15 1986-01-11 富士通テン株式会社 hybrid integrated circuit

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