JPS5999877A - Agc system of receiving amplifier - Google Patents
Agc system of receiving amplifierInfo
- Publication number
- JPS5999877A JPS5999877A JP57209014A JP20901482A JPS5999877A JP S5999877 A JPS5999877 A JP S5999877A JP 57209014 A JP57209014 A JP 57209014A JP 20901482 A JP20901482 A JP 20901482A JP S5999877 A JPS5999877 A JP S5999877A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- stage
- attenuation
- amplifier
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Receiver Circuits (AREA)
- Details Of Television Systems (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
本発明(はテレビ共同受信等に用いられる受信増幅器の
AGC方式に関するもので、その目的とするところは、
入力材−弓のレベルが変動しても常に一定のレベルの出
力信号を送出すあというAGC動作に加えて、人力信号
のしレベルが低くて信号対雑音比(高周波信号の搬送波
レベルと雑音レベルとの比、以下CN比という)が小さ
い場合でも増幅器内部で発生する雑音をできイ)たけ少
なくしだ状1態で増幅できるようにした受信増幅器のA
G C方式を:提供ずつにある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AGC system for a receiving amplifier used in television communal reception, etc., and its purpose is to
Input material - In addition to the AGC operation that always sends out an output signal at a constant level even if the bow level fluctuates, the input level of the human input signal is low and the signal-to-noise ratio (carrier level and noise level of high-frequency signal A of the receiving amplifier that can amplify the noise generated inside the amplifier as much as possible even when the ratio (hereinafter referred to as the CN ratio) is small.
GC method: provided one by one.
以上−図面(を二より本願の実施例についで説明する。The embodiments of the present application will be described below from the drawings.
第1図は受信増幅器を用いたテレビ共同受信/ステノ・
の系統図金星すもので、■はテレビ電波を受信するアン
テナである。2は広帯域型の受信増幅器で、3i−1:
その入力端子、4は出力端子を示す〇尚受信増幅器2と
しては、チャンネル専用型のものも用いらrLる。5は
増幅部で、l−入力端、7は出力端を示す。増幅部5の
構成は後に詳述する08は幹線分岐増幅器で、9はその
入力端子、10は出力端子、11は分岐出力端子を示す
。12は分岐器を示す。13は伝送線で、同軸ケーブル
が用いられる。14はテレビ受像機を示す。Figure 1 shows joint television reception/steno reception using a reception amplifier.
In the system diagram Venus Sumono, ■ is the antenna that receives television waves. 2 is a wideband receiving amplifier, 3i-1:
The input terminal and 4 indicate the output terminal.As the receiving amplifier 2, a channel-dedicated type may also be used. Reference numeral 5 indicates an amplifying section, an l-input end, and 7 an output end. The configuration of the amplifier section 5 will be described in detail later. 08 is a main branch amplifier, 9 is an input terminal thereof, 10 is an output terminal, and 11 is a branch output terminal. 12 indicates a turnout. 13 is a transmission line, and a coaxial cable is used. 14 indicates a television receiver.
次に第2図は第1図で示した増幅部の構成を示すブロッ
ク図で、第1図と同一のものには同一の符号を付して示
す。15 、1.6 、17はそれぞれ前段。Next, FIG. 2 is a block diagram showing the configuration of the amplifying section shown in FIG. 1, and the same parts as in FIG. 1 are denoted by the same reference numerals. 15, 1.6, and 17 are in the previous stage, respectively.
中段、後段の増幅回路を示すもので、テレビ信号等の高
周波信号を増幅する。18は前段増幅回路15と中段増
幅回路J6との間に設けられた前段減衰回路を、また1
9は中段増幅回路16と後段増幅回路17との間に設け
られた後段減衰回路をそれぞれ示す。This shows the middle-stage and rear-stage amplifier circuits, which amplify high-frequency signals such as television signals. 18 is a front-stage attenuation circuit provided between the front-stage amplifier circuit 15 and the middle-stage amplifier circuit J6;
Reference numeral 9 indicates a post-stage attenuation circuit provided between the middle-stage amplifier circuit 16 and the post-stage amplifier circuit 17, respectively.
20は増幅された信号の出力レベルを検出するための検
出回路で、周知の分岐回路等が用いられる。20 is a detection circuit for detecting the output level of the amplified signal, and a well-known branch circuit or the like is used.
21は検波回路で、高周波信号を直流に変換するだめの
ものである。22は比較回路で、検波回路21の出力を
用いて、高周波信号の出力レベルが標準よりも高いか低
いか比較し、その結果を出力する。Reference numeral 21 denotes a detection circuit, which serves to convert a high frequency signal into direct current. 22 is a comparison circuit that uses the output of the detection circuit 21 to compare whether the output level of the high frequency signal is higher or lower than the standard, and outputs the result.
例えば出力レベルの大きさに対応した大きさの自流電圧
を出力する。23.24はそれぞれ前段減衰制御回路、
後段減衰制御回路である。前段減衰制御回路23は前段
減衰回路180減哀特性全制御するもので、例えば第3
図(A)の実線の如くになるよう制御する。尚横軸は比
較回路22の出力端P点での出力電圧の一例を示してい
る。後段減衰制御回路24は後段減衰回路19の減衰特
性を制御−するもので、例えば第3図(B)の実線の如
くになるよう制御する。尚横軸は出力端P点での出力電
圧の一例である。1だ比較のために、減衰制御回路23
.24が無い場合の前段減衰回路18.後段減衰回路1
9の減衰特性を、それぞれ第3図(A)、第3図(B)
に破線で示した。For example, it outputs a self-current voltage whose magnitude corresponds to the magnitude of the output level. 23 and 24 are respectively the front stage attenuation control circuit,
This is a post-stage attenuation control circuit. The pre-stage attenuation control circuit 23 controls all the damping characteristics of the pre-stage attenuation circuit 180.
Control is performed so that the result is as shown by the solid line in Figure (A). Note that the horizontal axis indicates an example of the output voltage at the output terminal P point of the comparator circuit 22. The second-stage attenuation control circuit 24 controls the attenuation characteristics of the second-stage attenuation circuit 19, for example, as shown by the solid line in FIG. 3(B). Note that the horizontal axis is an example of the output voltage at the output end point P. For comparison, the attenuation control circuit 23
.. Pre-stage attenuation circuit 18 without 24. Post-stage attenuation circuit 1
The attenuation characteristics of 9 are shown in Fig. 3 (A) and Fig. 3 (B), respectively.
is indicated by a broken line.
以」二の構成の増幅部5の動作につい−C1第4図のレ
ベルダイヤグラムを用いて説明−ノ゛る。第4図には横
軸に第2図の各ブロック回路と対応する位置全台ブロッ
ク回路を示す符号にカッコ全村した符号で示し、縦軸に
はその位置でのレベルを示しである。尚、このレベルダ
イヤグラム・は減衰回路18.19の減衰量が一定の値
に落ち着いた後の状態を示すものである。The operation of the amplifying section 5 having the second configuration will now be explained using the level diagram shown in FIG. 4 of C1. In FIG. 4, the horizontal axis shows the block circuits in positions corresponding to the respective block circuits in FIG. 2, with all the blocks in parentheses, and the vertical axis shows the level at that position. Note that this level diagram shows the state after the attenuation amount of the attenuation circuits 18 and 19 has settled down to a constant value.
まず入力信号のし・ベルが50 dBμ程度と低い場合
には第4図の折線Xで示すように、前段減衰回路18で
の減衰量、後段減衰回路19での減衰量の両方共がほと
んど零である。(これは第3図においてP点での出力電
圧が0の場合に相当する)次に入力信号のレベルが60
dBμ程度の標準レベルの場合には、折線Yで示すよ
うに、前段減衰回路↑8での減衰量はほとんど零で、後
段減衰回路19での減衰量は約1.0dBとなり出力レ
ベルは前の場合と変わらない。(これは第3図において
P点での出力電圧がVo/2の場合に相当する)更に入
力信号のレベルが70dBμ程度の高い場合には、折線
Zで示すように、前段減衰回路18.後段減衰回路19
での減衰量が両方共に約10 dBとなり、この場合も
出力l/ベルは変わらない。(これは第3図においてP
点での出力電圧がVoの場合に相当する)
こΩように入力信号のレベルが標準より低い状態からそ
のレベルが増加するにつれて後段減衰回路J9の減衰量
が先に増え始め、標準より高い状態になると後段減衰回
路19の減衰量は飽和して前段増幅回路18の減衰量が
増え始めるようにしであるから人力信号のレベルの高低
にかかわらず常に一定の標準の出力で信号が出力端7か
ら送出される。First, when the input signal has a low level of about 50 dBμ, as shown by the broken line X in FIG. It is. (This corresponds to the case where the output voltage at point P in Figure 3 is 0) Next, the level of the input signal is 60
In the case of a standard level of about dBμ, as shown by the broken line Y, the amount of attenuation in the front-stage attenuation circuit ↑8 is almost zero, and the amount of attenuation in the rear-stage attenuation circuit 19 is about 1.0 dB, and the output level is the same as that of the previous stage. No different than the case. (This corresponds to the case where the output voltage at point P in FIG. 3 is Vo/2) Furthermore, when the level of the input signal is as high as about 70 dBμ, as shown by the broken line Z, the pre-stage attenuation circuit 18. Post-stage attenuation circuit 19
The amount of attenuation in both cases is approximately 10 dB, and the output l/bel remains unchanged in this case as well. (This is P in Figure 3.
(This corresponds to the case where the output voltage at point is Vo) As the input signal level increases from a state lower than the standard, the attenuation amount of the post-stage attenuation circuit J9 begins to increase first, and the state becomes higher than the standard. When this happens, the amount of attenuation in the second-stage attenuation circuit 19 is saturated and the amount of attenuation in the first-stage amplification circuit 18 begins to increase, so that the signal is always output from the output end 7 at a constant standard output regardless of the level of the human input signal. Sent out.
次に増幅部5の内部で発生する雑音fat示すパラメー
タである雑音指数について説明する。前段増幅回路15
.中段増幅回路16.後段増幅回路17のそれぞれの電
力利得をG+ 、 G2 、 G3 とし、丑だそれ
ぞれの雑音指数をF+ 、 F2 、 F3 と
する。Next, the noise figure, which is a parameter indicating the noise fat generated inside the amplifier section 5, will be explained. Pre-stage amplifier circuit 15
.. Middle stage amplifier circuit 16. The respective power gains of the post-stage amplifier circuit 17 are assumed to be G+, G2, and G3, and the respective noise figures are assumed to be F+, F2, and F3.
また前段減衰回路18.後段減衰回路19での減衰量を
それぞれLl 、 L2 とすると、増幅部5にお
りる総合的な雑音指数ト1は次式で示される。Also, the front stage attenuation circuit 18. Assuming that the attenuation amounts in the post-stage attenuation circuit 19 are Ll and L2, respectively, the overall noise figure T1 in the amplifier section 5 is expressed by the following equation.
3−1
十 ・ ・
・ ・ ・ ・(1)Gl―G2/ (Ll・L2)
(1)式における減衰量Ll + L2 に対して
、第3図の実線で示された特性の関係式を代入すれば、
総合的な雑音指数Fが求まることになる。3-1 Ten ・ ・
・ ・ ・ ・(1) Gl−G2/ (Ll・L2) If we substitute the relational expression of the characteristics shown by the solid line in Fig. 3 for the attenuation amount Ll + L2 in equation (1), we get
The overall noise figure F will be found.
第5図は入力し・ベルに対する増幅部5の総合的な雑音
指数の特性の一例を示す図表である。図において実線は
本願実施例のものを示し、破線は減衰制御回路23.2
4が設けられない従来のものの特性を示す。本願のもの
は、入力信号のし・ベルが標準より低くても高くても、
壕だ標準であっても、全般的に、N音指数を小さくする
ことができる0このことは、入力端6に加わる信号のC
NJ+′Jをさほど劣化させずに伝号を出力端7かも送
出できるということを意味する。FIG. 5 is a chart showing an example of the overall noise figure characteristics of the amplifying section 5 with respect to the input signal. In the figure, the solid line indicates the embodiment of the present application, and the broken line indicates the attenuation control circuit 23.2.
4 shows the characteristics of the conventional one in which the number 4 is not provided. The device of this application can be used even if the input signal level is lower or higher than the standard.
Even if the standard is very low, it is possible to reduce the N index in general. This means that the C of the signal applied to the input terminal 6
This means that the signal can also be transmitted at the output terminal 7 without significantly deteriorating NJ+'J.
以上のような増幅部5を設けた受信増幅器2を用いた第
1図のデし/ビ共同受信ンステノ・においては、アンテ
ナ1で受信されるテレビ信号のし・ベルが季節の変化や
フェージング等により変動しても、受信増幅器2の出力
端子・1からは常に一定の標準のレベルでテレビ信号を
送出することかできる。In the digital/video joint reception system shown in FIG. 1 using the reception amplifier 2 equipped with the amplification section 5 as described above, the signal strength of the television signal received by the antenna 1 is affected by seasonal changes, fading, etc. Even if the output terminal 1 of the reception amplifier 2 changes, the television signal can always be sent out at a constant standard level.
−まだ受信増幅器2の入力端子3に加わる信号のCN比
をさほど劣化させずに出力端子4から送出できるから、
後段に接続されたフーレビ受像機14においては、スノ
ーノイズの少ないくっきりした画像でテレビを楽1〜む
ことができる。- Since the signal applied to the input terminal 3 of the receiving amplifier 2 can be sent from the output terminal 4 without significantly deteriorating the CN ratio,
In the FTV receiver 14 connected to the rear stage, it is possible to easily watch television with clear images with little snow noise.
次に第6図は増幅部5の一部の具体的な構成を示す回路
図で、第2図と対応するものには同一の符号を例し2て
示し重複する説明を省略する。減衰回路18.19+は
それぞれ橋絡T型で構成されている。Next, FIG. 6 is a circuit diagram showing a specific configuration of a part of the amplifying section 5. Components corresponding to those in FIG. 2 are designated by the same reference numerals as 2, and redundant explanation will be omitted. The attenuation circuits 18, 19+ are each constructed in the form of a bridge T-type.
25、26.39.40は減衰量可変素子としてのPI
Nダイオード、27.28.41.42は定抵抗要素と
しての抵抗をそれぞれ示す。29.30.31 、32
.43.44゜45.46はP I Nダイオードバイ
アス用の抵抗を示す。33.47はチョー クコイル、
34.35.36.37゜38、48.49.50.5
]、 52はそれぞれ高周波を通過させ直流を阻止“す
るコンデンサを示す。尚、端子18a、19aには↑れ
ぞれ比較回路22からの出力信号(直流電圧)が加わり
、また端7−18bと18cの間、および端子]、9b
と19cの間には各PINダイオード動作用の電圧が加
わるようにされる。次VC前段減衰制御回路2;3は図
示の様にツェナーダイオード53と、電源(+B1)、
抵抗54とにより構成される。電源(−1−Bl)は第
3図で説明した電圧Vo を各回路へ供給する。また
ソ1ナーダイオード53は基準電圧がVo / 2のも
のが用いらノしる。25, 26.39.40 are PI as variable attenuation elements
N diodes, 27, 28, 41, and 42 respectively indicate resistances as constant resistance elements. 29.30.31, 32
.. 43.44° and 45.46 indicate resistors for biasing the PIN diode. 33.47 is choke coil,
34.35.36.37゜38, 48.49.50.5
] and 52 indicate capacitors that pass high frequencies and block direct current. Note that output signals (DC voltage) from the comparator circuit 22 are applied to terminals 18a and 19a, and terminals 7-18b and 52 are connected to terminals 18a and 19a, respectively. between 18c and terminal], 9b
A voltage for operating each PIN diode is applied between and 19c. The next VC pre-stage attenuation control circuit 2; 3 includes a Zener diode 53, a power supply (+B1),
It is composed of a resistor 54. The power supply (-1-Bl) supplies the voltage Vo explained in FIG. 3 to each circuit. The sonar diode 53 has a reference voltage of Vo/2.
後段減衰制御回路24は、ツェナーダイオード55と電
源(十82)と抵抗56とにより構成される。電源(+
B2)の電圧およびダイオード55の基準電圧はそれぞ
れ電源(十B1)の電圧およびダイオード530基準電
圧と同じである。The latter-stage attenuation control circuit 24 includes a Zener diode 55, a power supply (182), and a resistor 56. Power supply (+
The voltage of B2) and the reference voltage of diode 55 are the same as the voltage of power supply (10B1) and the reference voltage of diode 530, respectively.
尚第6図において、端子23cと2・1bと全接続しツ
ェナダイオード53丑たは55のいずれか一方を取り去
っても、第6図のものと同様の制御効果が得られる。In FIG. 6, even if the terminals 23c and 2.1b are all connected and one of the Zener diodes 53 and 55 is removed, the same control effect as in FIG. 6 can be obtained.
次に第7図(liS′I+−々る構成の受信増幅器%:
>11 ’−、J“ブロック回路図で、第1図と同一
あるい(佳均等機能のものには同一の符けにアルファベ
ットのe、あるいiJ、e’、e″・・・を付して重複
する説明を省略する。図示のものはチャンネル専用型の
受信増幅器を示しており、57.57’、 ・・・、
57″は各テレビチャンネルあるいはFM局専用のバン
ドパスフィルタを示−す。58は混合回路を示す。Next, Fig. 7 (Receiving amplifier % of liS'I + - ru configuration:
>11 '-, J" Block circuit diagrams that are the same as those in Figure 1 or have equivalent functions are indicated by the letter e, iJ, e', e", etc. The redundant explanation will be omitted.The illustrated one shows a channel-dedicated type receiving amplifier, and 57, 57', . . .
57'' represents a bandpass filter dedicated to each television channel or FM station. 58 represents a mixing circuit.
以」二のように本発明にあっては、入力信号のレベルが
変動しても常に一定の標準レベルに丑で増幅した出力信
号を送出する受信増幅器を提供できるO
しかも入力信号のレベルが低くCN比が小さい場合でも
増幅器内部で発生する雑音をできるだけ少なくして増幅
し、出力信号のCNN合金ほど劣化さぜずに送IJJT
きるという効果がある。As described above, the present invention can provide a receiving amplifier that always sends out an output signal amplified to a constant standard level even if the input signal level fluctuates.Moreover, the input signal level is low. Even when the CN ratio is small, the noise generated inside the amplifier is minimized and amplified, and the output signal is transmitted without deterioration as much as the CNN alloy.
It has the effect of being able to
図面は本発明の実施例に関するもので、第1図は受信増
幅器を用いたテレビ共同受信/スデムの系統図、第2図
は増幅部の構成金星tブロック図、第3図(A>、 C
B>はそれぞれ前段減衰回路、後段減衰回路の減衰特性
金示す図、第4図は増幅部のレベルダイヤグラム、第5
図は入力l/ベルに勾する増幅部の総合的な雑音指数の
特性の一例を示−ノー図表、第6図は増幅部の一部の具
体的な構成金示す回路図、第7図は異なる構成の受信増
幅器金示すブロック回路図。
3・・・入力端子、4・・・出力端イ、15・・・前段
増幅回路、16・・・中段増幅回路、17・・・後段増
幅回路、18・・・前段減衰回路、19・・・後段減衰
回路、20・・・検出回路、23・・・前段減衰制御回
路、24・・・後段減褒制御回路。
特蔚出願人 マスプロ″IL工株式会社代表者
端 山 孝
第5図
4(The drawings relate to embodiments of the present invention, and Fig. 1 is a system diagram of TV joint reception/Sudem using a reception amplifier, Fig. 2 is a block diagram of the configuration of the amplifier section, and Fig. 3 (A>, C).
B> is a diagram showing the attenuation characteristics of the front-stage attenuation circuit and the rear-stage attenuation circuit, respectively. Figure 4 is the level diagram of the amplification section.
The figure shows an example of the characteristics of the overall noise figure of the amplification section that slopes to the input l/bell. Block circuit diagrams illustrating receiver amplifiers of different configurations. 3... Input terminal, 4... Output terminal A, 15... Pre-stage amplifier circuit, 16... Middle-stage amplifier circuit, 17... Post-stage amplifier circuit, 18... Pre-stage attenuation circuit, 19... - Post-stage damping circuit, 20... Detection circuit, 23... Pre-stage damping control circuit, 24... Post-stage reward reduction control circuit. Special applicant Maspro “IL Engineering Co., Ltd. Representative
Takashi Hayama Figure 5 4 (
Claims (1)
路、中段増幅回路、後段減衰回路、後段増幅回路を縦続
状に介設し、上記後段増幅回路と上記出力端子との間に
は出力信号のレベル金検出するだめの検出回路を設け、
しかも」ニー記前段減表回路は前段減衰側φ1j回路で
減衰量の制御ヲ、丑〆ζ上gL後段減衰回路りよ後段減
衰制御回路て(7#、哀111の制御を行なうようにし
7た受信増幅器にj・・いて、′上記検出回路で検出し
た出力信号のレベルが標準よりも低い状態から標準の状
態にあるときは上記前段減衰回路の減衰量を変化させず
に」二記後段減衰回路の減衰量を増減して出力レベルが
−・定になるようにし、1だ上記検出回路での上記出力
信号のレベルが標準の状態から標準よりも高い状態にあ
るときは上記後段減衰回路の減衰@を変化させずにL記
前段減衰回路の減衰量全増減しで出力レベルが一定にな
るようにしたこと全特徴とする受信増幅器のAGC方式
。A front-stage amplifier circuit, a front-stage attenuation circuit, a middle-stage amplifier circuit, a rear-stage attenuation circuit, and a rear-stage amplifier circuit are interposed in cascade between the input terminal and the output terminal f-, and between the rear-stage amplifier circuit and the output terminal. A detection circuit is provided to detect the output signal level.
Moreover, the first-stage reduction circuit controls the attenuation amount with the first-stage attenuation side φ1j circuit, and the second-stage attenuation control circuit (7#, 111) controls the attenuation amount by the first-stage attenuation side φ1j circuit. In the amplifier, when the level of the output signal detected by the above detection circuit changes from a state lower than the standard to the standard state, the attenuation amount of the above-mentioned front-stage attenuation circuit is not changed. When the level of the output signal in the detection circuit is from the standard state to a state higher than the standard, the attenuation amount of the latter stage attenuation circuit is increased or decreased so that the output level becomes constant. An AGC method for a receiving amplifier characterized in that the output level is made constant by fully increasing or decreasing the amount of attenuation of the pre-stage attenuation circuit L without changing the @.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57209014A JPS5999877A (en) | 1982-11-29 | 1982-11-29 | Agc system of receiving amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57209014A JPS5999877A (en) | 1982-11-29 | 1982-11-29 | Agc system of receiving amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999877A true JPS5999877A (en) | 1984-06-08 |
Family
ID=16565838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57209014A Pending JPS5999877A (en) | 1982-11-29 | 1982-11-29 | Agc system of receiving amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999877A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60112306A (en) * | 1983-11-22 | 1985-06-18 | Nec Kansai Ltd | Electronic attanuator |
| JPS62122309A (en) * | 1985-11-21 | 1987-06-03 | Nec Corp | High frequency reception circuit |
| JPS62207016A (en) * | 1986-03-07 | 1987-09-11 | Nec Corp | Attenuation circuit |
| JPS63119388A (en) * | 1986-11-07 | 1988-05-24 | Sanyo Electric Co Ltd | Automatic gain control circuit |
| JPH0377416A (en) * | 1989-08-19 | 1991-04-03 | Aichi Denshi Kk | Automatic gain control circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54117659A (en) * | 1978-03-03 | 1979-09-12 | Nec Corp | High frequency gain control circuit |
-
1982
- 1982-11-29 JP JP57209014A patent/JPS5999877A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54117659A (en) * | 1978-03-03 | 1979-09-12 | Nec Corp | High frequency gain control circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60112306A (en) * | 1983-11-22 | 1985-06-18 | Nec Kansai Ltd | Electronic attanuator |
| JPS62122309A (en) * | 1985-11-21 | 1987-06-03 | Nec Corp | High frequency reception circuit |
| JPS62207016A (en) * | 1986-03-07 | 1987-09-11 | Nec Corp | Attenuation circuit |
| JPS63119388A (en) * | 1986-11-07 | 1988-05-24 | Sanyo Electric Co Ltd | Automatic gain control circuit |
| JPH0377416A (en) * | 1989-08-19 | 1991-04-03 | Aichi Denshi Kk | Automatic gain control circuit |
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