JPS6010262B2 - sampling device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention divides the frequency of an original oscillator to create a measurement signal, and the signal is a signal to be measured that has passed through an object to be measured, or a signal to be measured that is generated using the measurement signal as a trigger. The present invention relates to a sampling device that samples a signal using a pulse train whose cycle is longer or shorter than the repetition cycle of the signal under test by a fixed sampling interval.

In the sampling method used in conventional sampling oscilloscopes, the down ratio of the input and output waveforms changes depending on the bevel of the high-speed ramp waveform used to generate the sampling pulse, resulting in a high-speed ramp waveform with good linearity. It has been impossible to measure time with high accuracy using the sampled waveform.

In order to improve this inadequacy in performance, there is a sampling method in which the signal under test is stepped down at a constant ratio using a pulse train obtained by frequency-dividing the original oscillator. Since the present invention is an improvement on this conventional system, this conventional system will first be explained with reference to FIGS. 1 and 2. The signal of period T generated by the original oscillator 1 is divided by 1/N by the frequency divider 2,
From the output terminal 3 to the object to be measured 4, and further to the input terminal 5.
The signal is then input to the sampler 7. The waveform of the signal to be measured that is input to the sampler 7 is, for example, a waveform with a repetition period N·T as shown in FIG. 2A. (N is an integer)
On the other hand, the frequency of the output of the original oscillator 1 is reduced to 1/(N+) by the frequency synthesis circuit 6, and the output is as shown in FIG.
As shown in the figure, the pulse is input to the sampler 7 as a sampling pulse with a repetition period (N·T1S). S is the sampling interval, not the sampling period, but the interval between adjacent sampling points when the periods of the periodic signal under measurement are overlapped. The sampler 7 samples the waveform A at the repetition period of the waveform B and outputs it to the output terminal 8. For example, the waveform after sampling will be as shown in Figure 2C.
One cycle of FIG. 2A is reproduced by sampling S times. Therefore, the period after sampling becomes X(NT+S). As explained above, according to this conventional sampling device, the precision of the sampling interval is determined by the frequency stability and accuracy of the original oscillator 1, so that it is possible to produce a device with very high precision.

However, since the sampling gap S is narrow and the repetition period NT of the input signal to be sampled is long, the repetition period of the sampling machine x (NT + S) becomes very long, so when observing with a cathode ray tube, etc. The image flickered and became difficult to see, and it was not possible to follow rapid changes in input. The present invention eliminates these drawbacks.

Rather than observing the entire period of a signal under measurement, there are cases where only a part of the period is enlarged and observed in detail. Therefore, in this invention, when only a necessary part of the oscillator is to be observed, the output of the original oscillator is divided to obtain the sampling pulse. ) and preset a value M (M is an integer where OSM<N) in a cylinder divider to divide the output of the original oscillator and obtain a measurement signal to be supplied to the device under test using the divided output. By changing the phase of the signal under test, the repetition period after sampling is shortened, and the sampling interval S is narrow, so that a part of the signal under test can be seen in detail and stably.Third. The figure shows an example of a sampling device according to the present invention, and parts corresponding to those in FIG. The column for output voltage and frequency divider 9 of circuit 6 is performed.

This frequency-divided output is frequency-divided by the programmable frequency divider 101 to 1/n set by the setter 211. n is I
It is an integer with the condition Sn<N. Each time an output is obtained from the frequency divider 10, the gate circuit 11 is opened, and the numerical value M set in the setting circuit 22 is preset in the tube divider 2'. M is an integer that satisfies the condition OSM<N, and T/S is also an integer. Here, the presetting operation of the 1/N frequency divider 2' will be explained, including the operation of the gate circuit 11.

FIG. 4 shows a concrete 1/N frequency divider 2' and a gate circuit 11.
An example of the configuration is shown below. The count value of 1/N frequency divider 2' is 0.
It is made by an N-ary ring counter up to (N-1), counts the output of the original oscillator 1 as a clock, and the carry when the count changes from (N-1) to 0 is sent to terminal 3.
Output to.

Each bit of this ring counter has a set terminal ts and a reset terminal tr, respectively.
When s (or reset terminal tr) becomes “1”,
Becomes ``1'' (or ``0'') regardless of the clock, other bits, and previous state.Gate circuit 11
is multiple AND gates Gs, Gr and inverter ln
Each digit of ``1'' or ``0'' of the numerical value M expressed in binary digits is directly connected to the gate GS corresponding to each bit of the ring counter 2', and is connected to the gate Gr through the inverter ln. Each is always given as input. While the preset signal which is the output of the t frequency divider 10 is "1", the output of the gate circuit 11 is
is connected to give "1" to the set terminal ts or reset terminal tr of each bit of the 1/N frequency divider 2' corresponding to each bit. Therefore, the preset signal is “0”.
”, the output period of the 1/N divider 2' is N × clock period, but if a preset signal of “1” shorter than the clock period is applied to the gate circuit 11 in synchronization with the clock, the output period at that moment The count value of ring counter 2' becomes M,
Since counting starts from the next clock, the time from when the preset signal is applied until the output of the 1/N frequency divider 2' appears is (N - 1-M)×(clock period).

In this way, the phase of the output of the 1/N frequency divider 2' is changed digitally. FIG. 5 shows waveforms at each point in FIG. 3, and the operation of FIG. 3 will be explained.

When the gate circuit 11 is not operating, FIGS. 1 and 2
A sampling waveform is obtained at the output of the sampler 7 in the same manner as in the case explained in the figure. The 1/(T/S) frequency divider 9 divides the output of the frequency synthesis circuit 6 by 1/(T/S), and the output period becomes TX (N-Shoju・), which is the output of the original oscillator 1. (Fig. 5a) is an integral multiple of the period.

Next, this output is inputted to the programmer map powder machine 101, and the output shown in FIG. 5e is applied to the gate circuit 11 as a preset signal. Therefore, as mentioned above, the time from when the gate circuit 11 operates until the output of the next 1/N divider 2' is output is (N-1-M)×T, which is determined by M. It has a constant value, and the closer M is to N-1. This time will be small. Also, since the brisset signal e is in phase with the sampling pulse (Fig. 5c),
The phase difference between the sampling pulse and the output of the 1/N frequency divider 2' is calculated by (N-Y-M) x every time the preset signal e is output.
It becomes T. Therefore, by varying M, the sampling starting point can be varied over the entire range of repetitions of the signal under test (FIG. 5b). On the other hand, n of the voice programmable frequency divider 10 determines the range from the sampling start point to the sampling end point, and the number of samplings/~res in that range becomes Xn. FIG. 6 shows an actual configuration example, with the same reference numerals attached to parts corresponding to those in FIG. 3.

In this example, the frequency synthesis circuit 6 is constituted by a ./(N-S+.) tube divider 6 and a multiplier 6b, and a 1/(T/S) frequency divider 9 shown by a broken line is required. It's gone and it's 1 again
A waveform shaping circuit 12 was added to use the output of the /N frequency divider 2' as a measurement signal. As explained above, this invention makes it possible to obtain a repetitive waveform of only a part of the signal under test by changing the phase of the measurement signal (signal under test), and to change the amount of change in the phase of the signal under test. This allows you to sample any part.

This phase change shortens the repetition period of the sampling output d, and even if the sampling interval S is narrowed, the image can be displayed stably without flickering. Since these are done digitally, they can be done accurately and easily, and no adjustments are required. Furthermore, since this device has a constant sampling period and a constant down-down ratio of input and output waveforms, it is very effective for devices intended for digital signal processing. This device is a fault location measuring device using impulse reflection method, TDR (
Needless to say, this method is effective for time domain reflector making and measuring devices. Also, with this device, if the frequency division ratio of the frequency divider 6 in FIG.
In other words, the same results can be obtained even if the period of the sampling pulse is made shorter than the period of the signal under test.

Furthermore, by making the frequency synthesis circuits 6 and 9 programmable, the sampling interval can be made variable.
It can be precisely controlled from the outside.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional sampling device, FIG. 2 is a diagram showing waveforms at each point in FIG. 1, FIG. 3 is a block diagram showing an example of a sampling device according to the present invention, and FIG. , a block diagram showing a specific configuration example of the Kiyoshi frequency divider 2' and gate circuit 11 in FIG. 3, FIG. 5 is a diagram showing waveforms at each point in FIG. 3, and FIG. FIG. 3 is a block diagram showing another example of the device. 1: Original oscillator, 2: 1N frequency divider, 2': Presettable 1/N frequency divider, 3: Measurement signal source output terminal, 4: DUT, 5: Sampler measurement signal input terminal, 6:1
/(N+main) frequency synthesis circuit, 7: Sampler, 8
: Sampler output terminal, 9:1/(T/S) frequency divider, l
o: three programmable frequency dividers, 11: gate circuit, 12
: Waveform shaping circuit, 21: Setting circuit, 22: Numeric value setting circuit. Dropping figure No. 2 Drawing side No. 4 Illustration history 5 Illustration 6

Claims (1)

[Claims] 1. An original oscillator that oscillates at a frequency of 1/T, a presettable frequency divider that divides the output of the original oscillator by N (N is an integer) and uses the output as a measurement signal, and A frequency synthesis circuit that divides the frequency so that the period is (NT±S) (S is the sampling interval), a frequency divider that divides the output of the frequency synthesis circuit by T/S×n (n is an integer), A gate circuit presets the numerical value M in the 1/N frequency divider using the output of the frequency divider, and the output of the frequency synthesis circuit is used as a sampling pulse, and the measurement signal or the measurement signal is applied to the object to be measured. and a sampler that samples the output of the sample.