JPS601048U - phase accumulator - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram for explaining an example of the use of a phase accumulator, Fig. 2 is a circuit diagram of a conventional phase accumulator,
FIG. 3 is a circuit diagram showing an embodiment of the phase accumulator according to this invention. 11: Reference frequency oscillator, 13: Phase comparator, 14: Low-pass wave generator, 15: Voltage controlled oscillator, 16: Signal cancellation circuit, 17: Frequency divider, 18: Phase accumulator, 21
: Setting device, 22: Phase register, 23, 34: Frequency register, 24. 35: full adder, 31 near address counting circuit, 32: upper digit address selection circuit, 33: control circuit, 36: carry register, 37: timing control circuit, 39: signal sending circuit.

Claims (1)

[Claims for Utility Model Registration] A. A clock signal source; B. A phase register; C. A frequency register having a capacity multiple times that of the phase register and divided into the same capacity as the phase register by the upper digit address; D. an upper digit address selection circuit that selects an upper digit address of the frequency register; F. a full adder that adds the contents of the phase register and the frequency register read by the address counting circuit; and G the contents of the phase register read by the address counting circuit. A control circuit supplies H to the full adder and performs the calculation, and then writes the calculation result to the same address of the phase register. A phase accumulator comprising: a signal sending circuit that sends out a carry signal when the scale value is exceeded;