JPS6010751A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6010751A JPS6010751A JP11913583A JP11913583A JPS6010751A JP S6010751 A JPS6010751 A JP S6010751A JP 11913583 A JP11913583 A JP 11913583A JP 11913583 A JP11913583 A JP 11913583A JP S6010751 A JPS6010751 A JP S6010751A
- Authority
- JP
- Japan
- Prior art keywords
- regions
- aluminium
- type
- contact
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 7
- 229910045601 alloy Inorganic materials 0.000 abstract description 5
- 239000000956 alloy Substances 0.000 abstract description 5
- 150000004767 nitrides Chemical class 0.000 abstract description 3
- 239000004411 aluminium Substances 0.000 abstract 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000967 As alloy Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路装置に係シ、特に拡散層配線等
の拡散層領域と、上層の金属配線との電気的接続方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a method for electrically connecting a diffusion layer region such as a diffusion layer wiring to an upper layer metal wiring.
一般に１拡散層配線に対して電気的接続を行う配線材料
としてアルミニウムが使用されているが、近年の高密度
集積化、ウェハー製造工程における拡散層のシャロー化
が進んでくるとコンタクト抵抗や拡散層中へのアルミニ
ウム浸透（アロイスパイク）等の問題が、更に多層配線
構造を採った場合にはアルミニウム配線の断線問題等が
発生してくる。これらの解決法としてアロイスパイク防
止法について述べるとアルミニウム配線層と拡散層配線
層との接続には、接続すべき拡散層と同一導電型の不純
物を含んだ多結晶シリコンを介して接続する方法がある
。又、コンタクト抵抗やアルミ配線の断線の問題に対し
てはコンタクト段部や各種層間段部でのアルミニウムス
テップカバレッジを向上する目的でスパッタアルミｆ、
使用する方法がある。しかし、これらの解決法でも基本
的には、コンタクト構造が段差を持っているためアルミ
ニウム配線は信頼性上問題が起りやすい。そこでコンタ
クト開口内部にシリコンを選択的にエピタキシャル成長
する方法が考えられる。この方法によればアロイスパイ
ク及びアルミ断線等の問題が解決できる。しかしコンタ
クト開口内部に直接シリコンを設けるととＫよりて絶縁
用酸化膜とシリコン基板の界面状態が不規則にな夛この
領域において、電流リークを発生してしまい実用的では
なかった。Aluminum is generally used as a wiring material to make electrical connections to one diffusion layer wiring, but as the density of integration in recent years and the shallowing of diffusion layers in the wafer manufacturing process progresses, contact resistance and diffusion layer In addition to problems such as aluminum penetration into the interior (alloy spikes), problems such as disconnection of aluminum wiring occur when a multilayer wiring structure is adopted. Regarding the alloy spike prevention method as a solution to these problems, there is a method for connecting the aluminum wiring layer and the diffusion layer wiring layer through polycrystalline silicon containing impurities of the same conductivity type as the diffusion layer to be connected. be. In addition, in order to solve the problem of contact resistance and disconnection of aluminum wiring, sputtered aluminum f,
There is a way to use it. However, even with these solutions, since the contact structure basically has a step difference, reliability problems tend to occur with aluminum wiring. Therefore, a method of epitaxially growing silicon selectively inside the contact opening can be considered. This method can solve problems such as alloy spikes and aluminum disconnections. However, if silicon is provided directly inside the contact opening, the interface between the insulating oxide film and the silicon substrate becomes irregular due to K, and current leakage occurs in this region, making it impractical.
本発明の目的は上記したコンタクト抵抗、アロイスパイ
ク、アルミ断線及び電流リークの発生を防止した構造を
提供するものである。An object of the present invention is to provide a structure that prevents the occurrence of the above-mentioned contact resistance, alloy spikes, aluminum disconnection, and current leakage.
本発明によれは一導電型不純物を含む拡散層領域と上層
の金属配線とを結ぶためのコンタクト開口領域において
、開口側面に窒化シリコン膜を設けた後、更にこの内部
に拡散層領域同じ導電型のシリコンをたとえば選択的に
エピタキシャル成長して設けた半導体集積回路装置が得
られる。According to the present invention, in a contact opening region for connecting a diffusion layer region containing impurities of one conductivity type and an upper layer metal wiring, a silicon nitride film is provided on the side surface of the opening, and then a diffusion layer region of the same conductivity type is provided inside the contact opening region. A semiconductor integrated circuit device is obtained in which silicon is selectively grown epitaxially.
次に図を用いて本発明の構成を一実施例を用いて説明す
る。第１図には、Ｐ型シリコン基体１１上のフィールド
用酸化膜によシ周囲を囲まれた領域にＡ８によるＮ型不
純物をイオン注入してＮ型拡散層１：ｌ形成し、その後
１．５μの酸化膜１４を形成し更に前記Ｎ型拡散層１３
上の酸化膜１４の一部を開口した図を示す。次に０゜１
μの厚さの窒化膜１５ ’ｉ ＬＰＣＶＤ法やりアクテ
ィブスパッタエツチング法によシ前記酸化膜１４の側壁
にのみ形成した後前記酸化膜１４の開口領域内部ＫＮ型
シリコン１６を選択的にエピタキシャル成長した図を第
２図に更に選択的にアルミニウム配線１７全形成し、第
３図に示すように完成する。Next, the configuration of the present invention will be explained using one embodiment with reference to the drawings. In FIG. 1, an N-type impurity is ion-implanted using A8 into a region surrounded by a field oxide film on a P-type silicon substrate 11 to form an N-type diffusion layer 1:1, and then 1. A 5μ thick oxide film 14 is formed, and the N-type diffusion layer 13 is further formed.
A diagram showing a part of the upper oxide film 14 opened is shown. Next 0°1
A nitride film 15'i with a thickness of μ is formed only on the side walls of the oxide film 14 by LPCVD or active sputter etching, and then KN type silicon 16 is selectively epitaxially grown inside the opening region of the oxide film 14. Further, the entire aluminum wiring 17 is selectively formed as shown in FIG. 2, and the process is completed as shown in FIG.
以上述べたようにコンタクト開口領域において、開口側
面に窒化シリコン膜を設けた後頁にこの内部に接続すべ
き拡散層と同一導電型の不純物を含んだシリコンを選択
的にエピタキシャル成長することによりコンタクト領域
を平坦にすることによって上層のアルミニウム配線に段
差が生ずることがなくなシコンタクト開口部におけるア
ルミ断線及び電流リークが防止できる。又アルミステッ
プカバレッジの問題もなくカシコンタクト抵抗増加の問
題も抑制される。更に、シャロージヤンクションの形成
に際してもアロイスパイク発生の問題は起こらない。尚
、本実施例ではＮ型不純物を含んだシリコンを採用した
場合を説明したが、Ｐ型不純物を含んだシリコンを採用
した場合及び、と １れらを混用した場合でも良い。特
に本発明を相補型半導体装置に採用すると効果的である
。As described above, in the contact opening region, after a silicon nitride film is provided on the side surface of the opening, silicon containing impurities of the same conductivity type as the diffusion layer to be connected inside is selectively grown epitaxially. By making it flat, there will be no step difference in the upper layer aluminum wiring, and aluminum disconnection and current leakage at the contact opening can be prevented. Furthermore, there is no problem with aluminum step coverage, and the problem of increased contact resistance is also suppressed. Furthermore, the problem of alloy spikes does not occur when forming shallow junctions. In this embodiment, a case has been described in which silicon containing N-type impurities is used, but it is also possible to use silicon containing P-type impurities or a mixture of the two. It is particularly effective to apply the present invention to complementary semiconductor devices.
第１図、第２図、第３図は本発明の実施例による半導体
装置の製造工程順の断面図である。
図中、１１・・・・・・Ｐ型シリコン基体、１２−・・
・・・フィールド用酸化膜、１３・・・・・・Ｎ型拡散
層、１４・・・・・・酸化膜、１５−・・・・・窒化膜
、１６・・・・・・Ｎ型シリコン、１７・・・・・・ア
ルミニウム配線。
５−
２／図
ｙ２ ／３FIGS. 1, 2, and 3 are cross-sectional views showing the steps of manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 11...P-type silicon substrate, 12-...
...Field oxide film, 13...N type diffusion layer, 14...Oxide film, 15-...Nitride film, 16...N type silicon , 17... Aluminum wiring. 5-2/Figure y2/3
Claims (1)
ける開口側面に窒化シリコン膜を設け、＃開口の内部に
該−導電型のシリコン層を設けたこと’ｔ％徴とする半
導体集積回路装置。[Claims] A diffusion layer region of one conductivity type on the surface of a silicon substrate. A semiconductor integrated circuit device characterized in that a silicon nitride film is provided on the side surface of a contact opening region for connection to an upper layer metal wiring, and a silicon layer of the - conductivity type is provided inside the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11913583A JPS6010751A (en) | 1983-06-30 | 1983-06-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11913583A JPS6010751A (en) | 1983-06-30 | 1983-06-30 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6010751A true JPS6010751A (en) | 1985-01-19 |
Family
ID=14753797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11913583A Pending JPS6010751A (en) | 1983-06-30 | 1983-06-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010751A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0234930A (en) * | 1988-07-25 | 1990-02-05 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH0371657A (en) * | 1989-08-10 | 1991-03-27 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| US5895948A (en) * | 1996-09-27 | 1999-04-20 | Nec Corporation | Semiconductor device and fabrication process thereof |
-
1983
- 1983-06-30 JP JP11913583A patent/JPS6010751A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0234930A (en) * | 1988-07-25 | 1990-02-05 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH0371657A (en) * | 1989-08-10 | 1991-03-27 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| US5895948A (en) * | 1996-09-27 | 1999-04-20 | Nec Corporation | Semiconductor device and fabrication process thereof |
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