JPS60109228A - Projection exposing device - Google Patents

Projection exposing device

Info

Publication number
JPS60109228A
JPS60109228A JP58216165A JP21616583A JPS60109228A JP S60109228 A JPS60109228 A JP S60109228A JP 58216165 A JP58216165 A JP 58216165A JP 21616583 A JP21616583 A JP 21616583A JP S60109228 A JPS60109228 A JP S60109228A
Authority
JP
Japan
Prior art keywords
reticle
pattern
wafer
exposure
projection exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58216165A
Other languages
Japanese (ja)
Inventor
Yoshio Shintani
新谷 義夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58216165A priority Critical patent/JPS60109228A/en
Publication of JPS60109228A publication Critical patent/JPS60109228A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は投影露光技術に関し、特に半導体装置の製造に
際してレチクルパターンを被露光体へ高速に投影露光す
るために用いて好適な投影露光装置に関す゛るものであ
る。
[Detailed Description of the Invention] [Technical Field] The present invention relates to projection exposure technology, and more particularly to a projection exposure apparatus suitable for use in high-speed projection exposure of a reticle pattern onto an exposed object during the manufacture of semiconductor devices. It is.

〔背景技術〕[Background technology]

半導体装置の製造工程に利用されるホ) IJソグラフ
ィ技術では、例えば所定のパターンに形成したレチクル
を縮小して半導体ウェーハ上に投影露光する技術が必要
とされる(特開昭51−111076号公報)。また、
同様の技術は密着用のホトマスクを形成する際にも、レ
チクルパターンを縮小してホトマスク基板上に投影露光
する技術として必要とされている。そして、この縮小投
影露光の場合には、縮小したレチクルパターンをウェー
ハやホトマスク基板上に順序的にかつ繰返して複数回の
露光を行ない、ウェーハやホトマスク原板に多数個の縮
小レチクルパターンを桝目状に整列して形成するように
なっている。
In the IJ lithography technology used in the manufacturing process of semiconductor devices, for example, a technology is required in which a reticle formed in a predetermined pattern is reduced and projected onto a semiconductor wafer for exposure (Japanese Patent Application Laid-Open No. 111076/1983). ). Also,
A similar technique is also required when forming a photomask for close contact, as a technique for reducing the size of a reticle pattern and projecting it onto a photomask substrate for exposure. In the case of this reduction projection exposure, the reduced reticle pattern is sequentially and repeatedly exposed multiple times on the wafer or photomask substrate, and a large number of reduced reticle patterns are formed in a square pattern on the wafer or photomask original plate. They are arranged to form.

ところで、この投影露光には所甜プロジェクションアラ
イナが使用され、被露光体としてのウェーハ(又はホト
マスク基板)とレチクルとを1枚づつアライナ内にセッ
トし、ウェーハを間欠的に移動させながら縮小レチクル
ノくターンを1チップ分毎に投影する方法で露光を行な
って(・る。このため、ウェーッル上に形成する数十〜
数百のチップ数に等しい数の投影作業が必要とされ、露
光全体に必要とされる時間は1チップに対する投影時間
とウェーッ・上に形成するチップ数とσつ積となる。
By the way, a projection aligner is used for this projection exposure, and the wafer (or photomask substrate) as the object to be exposed and the reticle are set one by one in the aligner, and the wafer is moved intermittently while the reduced reticle is moved. Exposure is performed by projecting a turn for each chip.
A number of projection operations equal to the number of hundreds of chips are required, and the time required for the entire exposure is the product of the projection time for one chip and the number of chips formed on the wafer.

したがって、ウェーッ・上に形成するチップ数の増大に
伴なって露光作業時間カー増大し、し力・もこの露光作
業はホ) IJソグラフイ技術を使用する種々の段階の
工程で行なろれるために、全工程時間に対する露光作業
時間の占める割合カー大きくなり半導体装置の製造時間
の短縮の障害σ〕一つになっている。
Therefore, as the number of chips formed on the wafer increases, the exposure work time increases, and the exposure work can be performed at various stages of the process using IJ lithography technology. , the ratio of exposure work time to the total process time has increased, becoming one of the obstacles to shortening the manufacturing time of semiconductor devices.

〔発明の目的〕[Purpose of the invention]

本発明の目的はウェーッ・やホトマスク基板へσ〕縮小
投影に要する全露光時間の短縮を図り、これによりホト
リソグラフィ技術工程はもとより半導体装置の製造工程
時間の短縮を達成すること力1できる投影露光技術を提
供するごとにある。
An object of the present invention is to shorten the total exposure time required for reduction projection onto a photomask substrate, and thereby to shorten not only the photolithography technology process but also the manufacturing process time of semiconductor devices. Each technology is provided.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、投影露光装置内に2以上のレチクルパターン
結像系を内装し、これらの結像系によってレチクルパタ
ーンをウェーッ・等の被露光体の複数個所に夫々結像さ
せかつ同時に露光を行な(・得るよう構成することKよ
り、被露光体への全露光作業時間をレチクルパターン結
像系の数で除した時間にでき、これKより露光作業時間
ないし半導体製造時間の短縮を達成するものである。
That is, two or more reticle pattern imaging systems are installed in a projection exposure apparatus, and these imaging systems form images of the reticle pattern on multiple locations on an object to be exposed, such as a wafer, and simultaneously perform exposure. - From K, the total exposure work time for the object to be exposed can be divided by the number of reticle pattern imaging systems, and from this K, the exposure work time or semiconductor manufacturing time can be shortened. be.

〔実施例1〕 第1図は本発明の一実施例の投影露光装置1の正面構成
図を示しており、図においてWは被露光体としての半導
体ウェーッ・、2はこの半導体ウェーハWをX方向、Y
方向に間欠的に移動させるXYステージである。2この
XYステージ20両側には夫々同一パターンに形成しf
s2枚のレチクル3゜4をテーブル5上に保持している
。そして、これらレチクル3.4の下側にはレチクル3
,4を照明する照明系6.7を配置し、上側圧は結像光
学系8,9を配置している。前記照明系6,7は光源ラ
ンプ10,11および図外の光学素子によって前記レチ
クル3,4の全面を照明する。前記結像光学系8,9は
夫々3枚の平面鏡12.13゜14と15.16.17
、各1枚の凹面鏡18と19および凸面鏡20と21で
構成し、レチクル3.4の各パターンを1=10の縮小
率で前記ウェーハW上に夫々独立して投影結像できる。
[Embodiment 1] FIG. 1 shows a front configuration diagram of a projection exposure apparatus 1 according to an embodiment of the present invention, in which W indicates a semiconductor wafer as an object to be exposed, and 2 indicates this semiconductor wafer Direction, Y
This is an XY stage that moves intermittently in the directions. 2 The same pattern is formed on both sides of this XY stage 20.
Two reticles 3°4 are held on a table 5. Below these reticles 3.4 are reticles 3.
, 4 are disposed, and imaging optical systems 8, 9 are disposed on the upper side. The illumination systems 6 and 7 illuminate the entire surface of the reticles 3 and 4 using light source lamps 10 and 11 and optical elements not shown. The imaging optical systems 8 and 9 each include three plane mirrors 12.13°14 and 15.16.17.
, one each of concave mirrors 18 and 19 and convex mirrors 20 and 21, each pattern of the reticle 3.4 can be independently projected and imaged onto the wafer W at a reduction ratio of 1=10.

そして、各結像光学系8.LKよろ結像パターンPA。Each imaging optical system 8. LK wobbling imaging pattern PA.

pBは第2図に示すよ5に、ウェーハWの平面位置にお
いてY方向には同一でX方向には略ウェーハWの半径寸
法だけ離間された位置に設定している。
As shown in FIG. 2, pB is set at a position on the plane of the wafer W that is the same in the Y direction and spaced apart by approximately the radial dimension of the wafer W in the X direction.

゛ 以上の構成によれば、ウェーハW上に投影されるレ
チクル3,4の縮小パターンPA、PBKより、ウェー
ハW表面には各レチクルパターン3゜4が夫々同時に露
光される。そして、次にウェーハWがX方向(図示左方
向)に1チップ分移動されると、各パターン K、p’
は前記FA、PBの隣りに投影され、同様に各パターン
Pa、psは同時に露光される。以下、これを繰返し、
ウェーハWを略半径寸法だけX移動した後はY方向に1
チップ分移動させ今度は右X方向に間欠移動させながら
同様の露光を完了させる。この結果、第2図のように、
ウェーハWの右半分にはレチクル3のパターンが、左半
分圧はレチクル4のパターンが夫々露光される。
According to the above configuration, from the reduced patterns PA and PBK of the reticles 3 and 4 projected onto the wafer W, the reticle patterns 3 and 4 are simultaneously exposed on the surface of the wafer W, respectively. Then, when the wafer W is moved by one chip in the X direction (left direction in the figure), each pattern K, p'
are projected next to the FA and PB, and similarly each pattern Pa and ps are exposed simultaneously. Repeat this below,
After moving the wafer W by approximately the radial dimension X, it moves 1 in the Y direction.
After moving by the amount of the chip, the same exposure is completed while moving intermittently in the right X direction. As a result, as shown in Figure 2,
The pattern of the reticle 3 is exposed on the right half of the wafer W, and the pattern of the reticle 4 is exposed on the left half.

したがって、この投影露光装置によればウェーハWに対
して同時に2チツプの露光が行なわれることになり、全
チップに相当するパターンの露光は全チップ数の半分に
なる。これにより、同一チップ数のパターン露光時間は
従来の半分でよく、その分ホトリソグラコイエ程ないし
半導体製造工程ないし半導体製造工程に必要とされる時
間の短縮を図ることができる。
Therefore, according to this projection exposure apparatus, two chips are exposed simultaneously on the wafer W, and the exposure of a pattern corresponding to all the chips becomes half of the total number of chips. As a result, the pattern exposure time for the same number of chips can be half that of the conventional method, and the time required for photolithography, semiconductor manufacturing process, or semiconductor manufacturing process can be shortened accordingly.

〔実施例2〕 第3図は本発明の他の実施例である投影露光装置の正面
構成図を示す。本実施例の投影露光装置30は1枚のレ
チクル31とこれを照明する1個の照明系32を有する
一方、互いに近接配置された2個の結像光学系33.3
4を有し、同一レチクル31のパターンを各結像光学系
33.34で夫々独立してウェーハW上に結像している
。各結像光学系33.34を構成する平面鏡35,36
゜37と38.39,40、凹面鏡41と42、凸面鏡
43,44はY方向に隣設されかつX方向に若干ずれた
配置にしている。
[Embodiment 2] FIG. 3 shows a front configuration diagram of a projection exposure apparatus which is another embodiment of the present invention. The projection exposure apparatus 30 of this embodiment has one reticle 31 and one illumination system 32 for illuminating the reticle, while two imaging optical systems 33.3 are arranged close to each other.
4, and the pattern of the same reticle 31 is imaged onto the wafer W by each imaging optical system 33, 34 independently. Plane mirrors 35 and 36 forming each imaging optical system 33 and 34
37, 38, 39, 40, concave mirrors 41 and 42, and convex mirrors 43, 44 are arranged adjacent to each other in the Y direction and slightly shifted in the X direction.

したがって、この実施例によれば、各結像光学系33.
34により結像されるレチクル31の縮小パターンは、
第4図にパターンPa、Pbで示すように、ウェーハW
の平面上においてX方向に同一でY方向にウェーハの略
半系寸法だけ離間された位置に夫々結像される。これK
より、ウェーハWのX方向、Y方向の間欠移動によって
同図のようにウェーハWはパターンPa、Pbによって
上、下半分づつ露光が完了される。本例においても、ウ
ェー ハは同時に2チツプづつ露光が行なわれるため、
全チップの露光時間を従前の半分圧でき、製造工程時間
の短縮を達成できる。
Therefore, according to this embodiment, each imaging optical system 33.
The reduced pattern of the reticle 31 imaged by 34 is
As shown by patterns Pa and Pb in FIG.
The images are respectively formed on the plane at positions that are the same in the X direction and spaced apart by approximately half the size of the wafer in the Y direction. This is K
Therefore, by intermittent movement of the wafer W in the X direction and the Y direction, exposure of the upper and lower halves of the wafer W is completed according to the patterns Pa and Pb, as shown in the figure. In this example as well, since the wafer is exposed two chips at a time,
The exposure time for all chips can be reduced to half of the previous exposure time, achieving a reduction in manufacturing process time.

〔効 果〕〔effect〕

(1)被露光体に対して複数個のパターン結像系を設け
、夫々の結像パターンを独立して被露光体上に投影しか
つ露光を行なっているので、被露光体上に同時にパター
ン結像系に応じた分のパターン露光を行なうことができ
、これにより被露光体の露光部の全てを露光する時間を
従来より大巾に短縮でき、しいては半導体製造工程時間
の短縮を達成できる。
(1) A plurality of pattern imaging systems are provided for the exposed object, and each imaged pattern is independently projected onto the exposed object and exposure is performed. It is possible to perform pattern exposure according to the imaging system, and as a result, the time to expose the entire exposed area of the exposed object can be significantly shortened compared to conventional methods, thereby achieving a reduction in semiconductor manufacturing process time. can.

(2)1枚のレチクルと2個の光学系で同一レチクルパ
ターンをウェーハ上の異なる2個所に同時に結像できる
ので、全く同一のパターン露光を従来の半分の時間で完
了できる。
(2) Since the same reticle pattern can be imaged at two different locations on the wafer at the same time using one reticle and two optical systems, exposure of exactly the same pattern can be completed in half the time compared to conventional methods.

(3)2個のパターン結像系を一体的に組み入れて1個
の投影露光装置を構成しているので、2台の露光装置を
並置する場合に比較して占有スペースの低減を図り、ま
たXYステージや照明系等の要素の兼用化による低コス
ト化を図ることができる。
(3) Since two pattern imaging systems are integrated into one projection exposure device, the space occupied is reduced compared to when two exposure devices are placed side by side. Cost reduction can be achieved by using elements such as the XY stage and illumination system.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、前記第1図
と第3図の実施例を組合わせることによりウェーハ上に
同時[4個のパターンを投影することができ、これ罠よ
り露光時間を4分の1にすることも可能である。また、
それ以上の数のパターンを同時に露光する構成も可能で
ある。なお、結像光学系の構成は実施例のミラー光学系
に拘らずレンズを使用した光学系であってもよい。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, by combining the embodiments shown in FIGS. 1 and 3, it is possible to simultaneously project four patterns onto a wafer, and it is also possible to reduce the exposure time to one fourth. be. Also,
A configuration in which more patterns than that are exposed simultaneously is also possible. Note that the configuration of the imaging optical system is not limited to the mirror optical system of the embodiment, but may be an optical system using lenses.

〔利用分野〕[Application field]

以上の説明では主として本発明者圧よってなされた発明
をその背景となった利用分野である半導体装置の製造工
程におけるウェーハへのレチクルパターンの投影露光の
場合について説明したが、せれに限定されるものではな
く、ホトマスク基板への投影露光やその他のホトリソグ
ラフィ技術の全般に適用できる。
In the above explanation, the invention, which was made attributable to the present inventor, has mainly been explained in relation to the field of application in which it is applied, which is projection exposure of a reticle pattern onto a wafer in the manufacturing process of semiconductor devices. Rather, it can be applied to projection exposure onto photomask substrates and other photolithography techniques in general.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例である投影露光装置の正面構
成図、 第2図は露光方法を説明するためのウェーハ平面図、 第3図は本発明の他の実施例である投影露光装置の正面
構成図、 第4図はその露光方法を説明するためのウェーハ平面図
である。 1・・・投影露光装置、2・・・XYステージ、3,4
・・・レチクル、6,7・・・照明系、8,9・・・結
像光学系、30・・・投影露光装置、31・・・レチク
ル、32・・・照明系、33.34・・・結像光学系、
W・・・ウェーハ、PA、 PA、 PB、 PB’、
 Pa、 Pb ・”投影パターン。 第1図 第 2 図 第 3 図 第4図 βi
Fig. 1 is a front configuration diagram of a projection exposure apparatus which is an embodiment of the present invention, Fig. 2 is a plan view of a wafer for explaining the exposure method, and Fig. 3 is a projection exposure apparatus which is another embodiment of the invention. A front configuration diagram of the apparatus, and FIG. 4 is a wafer plan view for explaining the exposure method. 1... Projection exposure device, 2... XY stage, 3, 4
... Reticle, 6,7... Illumination system, 8,9... Imaging optical system, 30... Projection exposure device, 31... Reticle, 32... Illumination system, 33.34. ...imaging optical system,
W...Wafer, PA, PA, PB, PB',
Pa, Pb ・” Projection pattern. Fig. 1 Fig. 2 Fig. 3 Fig. 4 βi

Claims (1)

【特許請求の範囲】 1、被露光体上にレチクルパターンを縮小して投影露光
する投影露光装置において、前記レチクルのパターン結
像系を複数個設け、前記被露光体上に各パターン結像系
によるレチクルパターンを夫々独立して投影露光し得る
よう構成したことを特徴とする投影露光装置。 2、パターン結像系は複数枚のレチクルと、各レチクル
に対応して設けた投影光学系とを有する特許請求の範囲
第1項記載の投影露光装置。 3、パターン結像系は1枚のレチクルと、このレチクル
を夫々独立してパターン結像する複数個の投影光学系と
を有する特許請求の範囲第1項記載の投影露光装置。
[Scope of Claims] 1. In a projection exposure apparatus for projecting and exposing a reduced reticle pattern onto an object to be exposed, a plurality of reticle pattern imaging systems are provided, and each pattern imaging system is provided on the object to be exposed. 1. A projection exposure apparatus characterized in that the projection exposure apparatus is configured to be able to independently project and expose reticle patterns according to the invention. 2. The projection exposure apparatus according to claim 1, wherein the pattern imaging system includes a plurality of reticles and a projection optical system provided corresponding to each reticle. 3. The projection exposure apparatus according to claim 1, wherein the pattern imaging system includes one reticle and a plurality of projection optical systems each independently forming a pattern image on the reticle.
JP58216165A 1983-11-18 1983-11-18 Projection exposing device Pending JPS60109228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58216165A JPS60109228A (en) 1983-11-18 1983-11-18 Projection exposing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58216165A JPS60109228A (en) 1983-11-18 1983-11-18 Projection exposing device

Publications (1)

Publication Number Publication Date
JPS60109228A true JPS60109228A (en) 1985-06-14

Family

ID=16684303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58216165A Pending JPS60109228A (en) 1983-11-18 1983-11-18 Projection exposing device

Country Status (1)

Country Link
JP (1) JPS60109228A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6362231A (en) * 1986-09-02 1988-03-18 Nippon Telegr & Teleph Corp <Ntt> X-ray reduction stepper
JPH03179723A (en) * 1989-12-07 1991-08-05 Matsushita Electric Ind Co Ltd Projection aligner
USRE33836E (en) * 1987-10-22 1992-03-03 Mrs Technology, Inc. Apparatus and method for making large area electronic devices, such as flat panel displays and the like, using correlated, aligned dual optical systems
US5298365A (en) * 1990-03-20 1994-03-29 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
JPH07135165A (en) * 1993-11-11 1995-05-23 Nikon Corp Scanning exposure device
JPH07183188A (en) * 1993-12-22 1995-07-21 Nikon Corp Scanning exposure device
JPH09306826A (en) * 1996-05-10 1997-11-28 Semiconductor Energy Lab Co Ltd Aligner
US6480262B1 (en) 1993-06-30 2002-11-12 Nikon Corporation Illumination optical apparatus for illuminating a mask, method of manufacturing and using same, and field stop used therein
JP2015207566A (en) * 2015-07-23 2015-11-19 ウシオ電機株式会社 Polarized light irradiation method for optical orientation

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6362231A (en) * 1986-09-02 1988-03-18 Nippon Telegr & Teleph Corp <Ntt> X-ray reduction stepper
USRE33836E (en) * 1987-10-22 1992-03-03 Mrs Technology, Inc. Apparatus and method for making large area electronic devices, such as flat panel displays and the like, using correlated, aligned dual optical systems
JPH03179723A (en) * 1989-12-07 1991-08-05 Matsushita Electric Ind Co Ltd Projection aligner
US6794118B2 (en) 1990-03-20 2004-09-21 Renesas Technology Corp. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US6153357A (en) * 1990-03-20 2000-11-28 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US5298365A (en) * 1990-03-20 1994-03-29 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US5455144A (en) * 1990-03-20 1995-10-03 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US5667941A (en) * 1990-03-20 1997-09-16 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US6309800B1 (en) 1990-03-20 2001-10-30 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US5753416A (en) * 1990-03-20 1998-05-19 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US6795169B2 (en) 1993-06-30 2004-09-21 Nikon Corporation Exposure apparatus, optical projection apparatus and a method for adjusting the optical projection apparatus
US6480262B1 (en) 1993-06-30 2002-11-12 Nikon Corporation Illumination optical apparatus for illuminating a mask, method of manufacturing and using same, and field stop used therein
US6509954B1 (en) 1993-06-30 2003-01-21 Nikon Corporation Aperture stop having central aperture region defined by a circular ARC and peripheral region with decreased width, and exposure apparatus and method
US6556278B1 (en) 1993-06-30 2003-04-29 Nikon Corporation Exposure/imaging apparatus and method in which imaging characteristics of a projection optical system are adjusted
US7023527B2 (en) 1993-06-30 2006-04-04 Nikon Corporation Exposure apparatus, optical projection apparatus and a method for adjusting the optical projection apparatus
US7088425B2 (en) 1993-06-30 2006-08-08 Nikon Corporation Exposure apparatus, optical projection apparatus and a method for adjusting the optical projection apparatus
JPH07135165A (en) * 1993-11-11 1995-05-23 Nikon Corp Scanning exposure device
JPH07183188A (en) * 1993-12-22 1995-07-21 Nikon Corp Scanning exposure device
JPH09306826A (en) * 1996-05-10 1997-11-28 Semiconductor Energy Lab Co Ltd Aligner
JP2015207566A (en) * 2015-07-23 2015-11-19 ウシオ電機株式会社 Polarized light irradiation method for optical orientation

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