JPS60114955A - Decentralized processing computer system - Google Patents
Decentralized processing computer systemInfo
- Publication number
- JPS60114955A JPS60114955A JP58221489A JP22148983A JPS60114955A JP S60114955 A JPS60114955 A JP S60114955A JP 58221489 A JP58221489 A JP 58221489A JP 22148983 A JP22148983 A JP 22148983A JP S60114955 A JPS60114955 A JP S60114955A
- Authority
- JP
- Japan
- Prior art keywords
- computer
- level
- order computer
- input
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は分散処理計算機システム、特に機能の分散処
理を行う複数の計算機のうち任意の計算機が故障した場
合の処理に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a distributed processing computer system, and particularly to processing when any one of a plurality of computers that perform distributed processing of functions fails.
従来、この種のシステムとして第1図に示すものが公知
である。同図において、1は上位計算機、2A〜2Cは
下位計算機、3は下位計算機の共通予備計算機、4八〜
4Cは下位計算機2八〜2Cの入出力装置、5A〜5C
は下位計算機2A〜2Cから共通予備計算機3に入出力
装置4八〜4Cの接続を切替える切替スイッチである。Conventionally, as this type of system, the system shown in FIG. 1 is known. In the figure, 1 is the upper computer, 2A to 2C are the lower computers, 3 is the common spare computer for the lower computers, and 48 to 2C are the lower computers.
4C is the input/output device for lower-level computers 28-2C, 5A-5C
is a changeover switch that switches the connection of the input/output devices 48 to 4C from the lower-level computers 2A to 2C to the common spare computer 3.
このような構成の分散処理計算機システムの動作につい
て説明する。下位計算機2A〜2Cはそれぞれの入出力
装置4A〜4Cで接続されたプロセスからの入力信号を
処理し、プロセスに対して指示出力を出したり、あるい
は上位計算機1に入力信号を送信する。上位計算機1は
下位計算機2A〜2Cから送信されてくる信号を用いて
管理機能を処理し、あるいは共通的な機能を処理する。The operation of the distributed processing computer system having such a configuration will be explained. The lower-level computers 2A to 2C process input signals from processes connected to each other through their respective input/output devices 4A to 4C, and output instructions to the processes, or transmit input signals to the higher-level computer 1. The higher-level computer 1 processes management functions or common functions using signals transmitted from the lower-level computers 2A to 2C.
また、上位計算機1から下位計算機2八〜2Cに対して
指令信号が送信され、それに基づく処理を下位計算機2
A〜2Cが実行し、入出力装置4A〜4Cを介してプロ
セスへ指示出力が出されることもある。ここで、複数の
下位計算機のうちの例えば下位計算1,132 Aの1
台が故障した場合、それに属する切替スイッチ5Aが働
き、入出力装置4Aは共通予備計算機3に切替え接続さ
れる。そして下位計算機2Aの計算処理は共通予備計算
機3で実行され、システム全体の機能は損なわれずに続
行されるようになっている。In addition, a command signal is transmitted from the higher-level computer 1 to the lower-level computers 28 to 2C, and the lower-level computers 2 perform processing based on the command signal.
A to 2C may be executed and instructions may be output to the process via the input/output devices 4A to 4C. Here, among the plurality of lower-level computers, for example, one of lower-level calculations 1,132 A
When a machine fails, the changeover switch 5A belonging to it is activated, and the input/output device 4A is switched and connected to the common spare computer 3. The calculation processing of the lower-level computer 2A is executed by the common spare computer 3, so that the functions of the entire system can be continued without being impaired.
しかしながら、従来の分散処理計算機システムは以上の
ように構成されているので共通予備計算機3を設けねば
ならず、また、2台以上の下位計算機が同時に故障した
場合には、共通予備計算機3に接続された入出力装置に
対応する下位計算機1台の機能がバックアップされるの
みで、その他の下位計算機の機能はバックアップされず
、その機能が停止する欠点があった。この欠点を除くた
めには共通予備計算機3の台数を増せばよいのであるが
、それに伴って切替スイッチの制御回路構成も複雑にな
るという欠点があった。However, since the conventional distributed processing computer system is configured as described above, it is necessary to provide a common spare computer 3, and if two or more lower-level computers fail at the same time, they are connected to the common spare computer 3. This has the disadvantage that only the functions of one lower-level computer corresponding to the input/output device that has been installed are backed up, but the functions of other lower-level computers are not backed up and their functions stop. In order to eliminate this drawback, it would be sufficient to increase the number of common spare computers 3, but this would result in a drawback that the control circuit configuration of the changeover switch would also become complicated.
〔発明の概要〕
本発明は、上記のような従来の欠点を取除くためになさ
れたものであって、上位計算機によって下位計算機のハ
ックアップを行うようにするものであり、以下実施例を
用いて本発明の詳細な説明する。[Summary of the Invention] The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology, and is to allow a higher-level computer to hack up a lower-level computer. The present invention will now be described in detail.
第2図は本発明による分散処理計算機システムの実施例
を示す回路図であり、第1図と同しもの相当部分には同
一符号を用いている。同図において、10八〜10Cは
切替スイッチであり、リレー11を励磁することにより
可動接点12.13を固定接点14.15から固定接点
16.17に切替え動作するもので、これによりいずれ
の下位計算ta2A〜2Cに属する入出力装置4A〜4
Cも切替スイッチIOA〜IOCによって上位計算機1
に直接接続させることができる。したがって例えば下位
計算tJlt 2 A ]台が故障した場合には、その
入出力装置4Aが切替スイッチIOAによって上位計算
機1に直接接続され、その機能のバンクアンプが行われ
る。また、この状態でさらに別の下位計算機が故障した
場合にも、その下位計算機に所属する入出力装置が上位
計算機1に接続され、同様にその機能のバンクアップが
なされる。FIG. 2 is a circuit diagram showing an embodiment of the distributed processing computer system according to the present invention, and the same reference numerals are used for the same parts as in FIG. 1. In the figure, reference numerals 108 to 10C are changeover switches, which operate by energizing the relay 11 to switch the movable contact 12.13 from the fixed contact 14.15 to the fixed contact 16.17. Input/output devices 4A to 4 belonging to calculation ta2A to 2C
C is also connected to host computer 1 by switching switch IOA to IOC.
can be directly connected to. Therefore, for example, if the lower-level computer tJlt 2 A fails, its input/output device 4A is directly connected to the higher-level computer 1 by the changeover switch IOA, and bank amplification of its function is performed. Furthermore, even if another lower-level computer fails in this state, the input/output device belonging to that lower-level computer is connected to the higher-level computer 1, and its functions are similarly upgraded.
なお、上記実施例では上位計算機と複数の下位計算機の
間の接続は1対1の信号ラインによる接続を行っている
が、ループ状で伝送を行うようにしても同様の効果が得
られる。In the above embodiment, the upper computer and the plurality of lower computers are connected by one-to-one signal lines, but the same effect can be obtained even if the transmission is performed in a loop.
また、上位計算機は1台の場合について説明したが、上
位計算機が2台で相互にバックアンプできる構成になっ
ているシステムの場合も、本発明を適用でき、このよう
なシステムではさらにシステム全体の信頼性を向上させ
ることができる。Furthermore, although the case where there is one host computer has been described, the present invention can also be applied to a system in which two host computers are configured to back-amplify each other. Reliability can be improved.
このように本発明による分散処理計算機システムによれ
ば、1台の下位計算機のみならず、複数台の下位計算機
が故障した場合でも1台の上位計算機によってそれらの
機能を残らずバンクアンプできる。As described above, according to the distributed processing computer system according to the present invention, even if not only one lower-order computer but a plurality of lower-order computers fail, all of their functions can be bank-amplified by one higher-order computer.
また、共通予備計算機が不要となり、低コスト化が図れ
、また信頼性を向上できる。Furthermore, a common spare computer is not required, which reduces costs and improves reliability.
第1図は従来の分散処理計算機システムの一例を示す回
路図、第2図は本発明による分散処理計算機システムの
一実施例を示す回路図である。
1・・・上位計算機、2八〜2C・・・下位計算機、3
・・・共通予備計算機、4A〜4C・・・入出力装置、
5A〜5C,IOA〜IOC・・・切替スイッチ。
図中、同一または相当部分には同一符号を用いている。
代理人 大 岩 増 雄(ほか2名)FIG. 1 is a circuit diagram showing an example of a conventional distributed processing computer system, and FIG. 2 is a circuit diagram showing an embodiment of the distributed processing computer system according to the present invention. 1...Upper computer, 28~2C...Lower computer, 3
... common spare computer, 4A to 4C ... input/output device,
5A to 5C, IOA to IOC...selector switch. In the figures, the same reference numerals are used for the same or corresponding parts. Agent Masuo Oiwa (and 2 others)
Claims (1)
る複数の下位計算機と、各下位計算機の管理機能あるい
は共通機能を処理する上位計算機とから成る分散処理計
算機システムにおいて、上記上位計算機に下位計算機の
パンクアンプ機能をもたせ、各下位計算機の入出力装置
を上位計算機に切替接続する切替手段を設け、上位計算
機によって、故障した下位計算機の機能をバンクアップ
するようにしたことを特徴とする分散処理計算機システ
ム、。In a distributed processing computer system consisting of a plurality of lower-level computers that process functions specific to each process via input/output devices, and a higher-level computer that processes the management functions or common functions of each lower-level computer, The present invention is characterized in that the lower computer has a puncture amplification function and is provided with a switching means for switching and connecting the input/output device of each lower computer to the higher level computer, so that the higher level computer can bank up the functions of the failed lower level computer. Distributed processing computer system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58221489A JPS60114955A (en) | 1983-11-25 | 1983-11-25 | Decentralized processing computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58221489A JPS60114955A (en) | 1983-11-25 | 1983-11-25 | Decentralized processing computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60114955A true JPS60114955A (en) | 1985-06-21 |
Family
ID=16767511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58221489A Pending JPS60114955A (en) | 1983-11-25 | 1983-11-25 | Decentralized processing computer system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60114955A (en) |
-
1983
- 1983-11-25 JP JP58221489A patent/JPS60114955A/en active Pending
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