JPS60128639A - Low step difference wiring layer and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a low step difference wiring layer making a wiring layer almost flat by a method wherein silicon films almost at the same level are formed around silicide wiring made of polysilicon. CONSTITUTION:A specified wiring pattern Si3N4 4 is selectively etched and a polysilicon film 3 below the film 4 is also thinly etched and then the lower polysilicon film 3 is selectively oxidized utilizing the residual Si3N4 as a mask for selective oxidation. The part of polysilicon film 3 to be the wiring pattern other than the part directly below the Si2N4 film is formed into an SiO2 film 5. Next the SiO2 film 5 is properly etched to remove the Si3N4 film 4. After sputtering Pt, the polysilicon film 3 is silicified to form a Pt silicide 6. Through these procedures, a low resistant contact may be assured by a doped polysilicon layer 7 with further increased impurity concentration due to the impurity rising up from a diffusion resistor 2.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an electrode formation technique and a technique that is particularly effective when applied to multilayer wiring, for example, a technique that is effective when used for flattening electrode formation in a semiconductor device. It is related to.

[Background Art] For example, in conventional wiring technology used in semiconductor devices and the like, aluminum, polysilicon, or the like is selectively etched to leave a pattern that should become a wiring.

However, with this method, a step corresponding to the height of the wiring pattern inevitably remains, which is a major drawback in terms of planarization and becomes an obstacle to miniaturization of elements, high integration, and high density wiring.

In other words, the coverage of the upper layer deteriorates due to the step difference, making it difficult to reduce the upper layer pattern, for example, the wiring pitch and wiring width of the upper wiring layer, which limits miniaturization, high integration, and high density wiring. Ta.

[Object of the Invention] An object of the present invention is to provide a planarized low-level wiring layer and a method for manufacturing the same.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, by forming a silicon oxide film of approximately the same height around the polysilicon silicide wiring, the wiring layer becomes approximately flat and a low-level difference wiring layer is achieved.

In addition, since the silicide wiring and the silicon oxide film are formed by selective oxidation and silicidation of the same polysilicon film, the thickness of the silicide wiring and the silicon oxide film after completion can be easily made to be approximately the same height, resulting in a low level difference. A method for manufacturing a wiring layer is achieved.

[Example] Hereinafter, the case where the low level difference wiring layer and the manufacturing method thereof of the present invention are applied to the first wiring layer of a semiconductor device,
This will be explained with reference to FIGS. 1 to 4.

FIG. 1 shows a diffusion resistor formed in a semiconductor substrate 1, for example, a P-type impurity silicon semiconductor substrate, for example, an N+
A cross-sectional view for explaining the present invention in a case where an electrode is drawn out from the impurity diffusion layer 2 is shown. First, a properly doped polysilicon film 3 is deposited on the entire upper surface of the semiconductor substrate 1 using a CVD method (Chemical Vapor Dep.
position method). Next, an oxidation-resistant film, for example, a silicon nitride film (Si3N4 film)
4 is similarly formed on the polysilicon film 3 by the CVD method. This Si3N4 film 4 is used as a mask for selective oxidation of the polysilicon film 3, as will be described later.

In Figure 2, a Si3N4 film 4 is applied to the required wiring pattern.
selectively etched. At this time, the underlying polysilicon film 3 is also etched thinly. Next, the remaining Si3
Selective oxidation of the underlying polysilicon film 3 is performed using the N4 film 4 as a mask for selective oxidation.

In this selective oxidation, heat treatment at a considerably high temperature is required.
By implanting oxygen ions in the process, the heat treatment time can be shortened and the influence on the diffusion layer 2 can be kept to a minimum. In this way, the Si3N which becomes the wiring pattern is
The polysilicon film 3 other than directly under the fourth film 4 is changed to a silicon oxide film (Si02 film) 5 in FIG.

Next, the 5i02 film 5 is etched to an appropriate degree, and the Si3
The N4 film 4 is removed. Etching is 5i by selective oxidation.
This is a measure against an increase in the thickness of the 02 film 5 or flattening against bird's head, and is optimized to balance the increase in the thickness of the polysilicon film 3 due to silicidation, which will be described later.

Thereafter, after sputtering, for example, Pt on the entire surface, the polysilicon film 3 is silicided to form Pt silicide 6. In this case, by taking into account the margin for impurities rising from the diffused resistor 2, a low-resistance contact can be ensured by the doped polysilicon layer 7 having a higher impurity concentration.

Then, P on the 5i02 film 5 is removed by sintering. Note that when a silicide other than Pt is formed, sintering can be replaced by another suitable metal vapor deposition film removal process. The wiring layer thus completed, shown in FIG. 4, has few steps and good coverage of the upper layer, and since there is no etching for wiring electrodes, there is no fear of short circuits due to overetching or etching residue.

The low level difference wiring layer according to the present invention has a level difference reduced to about 25% or less of the level difference formed by conventional etching.

[Effects] As explained above, since a silicon oxide film having approximately the same height as the silicide wiring is formed around the silicide wiring, there is an effect that the wiring layer can be flattened with almost no step difference.

Furthermore, since a flat, low-level wiring layer is formed by selective oxidation and silicidation of polysilicon, there is no etching of the wiring pattern as in the conventional method, and there is no short circuit due to over-etching or etching residue.

Therefore, for example, in semiconductor devices, miniaturization,
This has the effect of contributing to higher integration or higher speed.

Hereinafter, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, electrodes 6 and 7 may be formed as interconnects on a thick field SiO2 film on the substrate.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application of the invention, which is the electrode formation technology of semiconductor devices, but the invention is not limited to this, for example. , it can be applied to electrode formation technology on wiring boards, etc.

[Brief explanation of drawings]

1 to 4 are cross-sectional views showing a manufacturing process applied to a first wiring layer of a semiconductor device as an embodiment of the low-level wiring layer and the manufacturing method thereof of the present invention. 3...Polysilicon film to dope 1, 4...S
i'3N4 film, 5... silicon oxide film, 6...
pt silicide, 7...highly doped polysilicon layer.

Claims (1)

[Claims] 1. It is characterized by consisting of a polysilicon silicide wiring formed in a wiring pattern and a silicon oxide film having approximately the same thickness as the silicide wiring and formed around the silicide wiring. Low height difference wiring layer. 2. The low-step wiring layer according to claim 1, wherein the silicide wiring is platinum silicide. 3. Form polysilicon on the entire surface on which the wiring pattern is to be formed, selectively form an oxidation-resistant film with the required wiring pattern on this polysilicon, and remove the polysilicon except directly under the oxidation-resistant film. A method for manufacturing a low-level wiring layer, comprising selectively oxidizing and removing the oxidation-resistant film, and then siliciding the required wiring pattern. 4. The method of manufacturing a low-level wiring layer according to claim 3, wherein the selective oxidation of the polysilicon comprises oxygen ion implantation and subsequent heat treatment.