JPS60132425A - Detecting circuit of disturbing wave of receiver - Google Patents

Abstract

PURPOSE:To eliminate a disturbing wave produced by adjacent waves with high reliability by detecting the difference between the multiplication product value between a reception signal and a reference signal having phase locking to a reception carrier and the multiplication product value between a reception signal and the signal obtained by limiting the amplitude component of the reception signal. CONSTITUTION:An IF signal obtained by transmitting a reception signal through a front end 1, an IF filter 2 and an IF amplifier 3 is supplied to synchronizing wave detectors 7 and 10 as well as to a limiter 8. The limiter 8 supplies the signal obtained by limiting the amplitude component of the IF signal to a PLL9 and the detector 10. The PLL9 delivers the signal having phase locking to the carrier wave of the reception signal to the detector 7. The detector 7 performs the multiplication between the IF signal and the carrier phase locking signal given from the PLL9 and delivers a sound signal AF of a low band component. The detector 10 performs multiplication between the IF signal and the signal given from the limiter 8 and supplies the low band component to a difference detector 11. The detector 11 detects and delivers a disturbing wave caused by adjacent carrier waves of the difference between detection outputs of both detectors 7 and 10.

Description

TECHNICAL FIELD The present invention relates to an interference wave detection circuit for a receiver, and more particularly to a detection circuit for detecting interference waves coming from an adjacent station in an AM receiver.

There is a conventional weighing device as shown in Fig. 1, in which the received signal is passed from the front 1 to the end 1, converted to an IF (intermediate frequency) signal, and passed through an IF filter 2 to the 1F.
Supplied to amplifier 3. Amplified 1: IF signal is A
The signal is detected by the M detector 4 and becomes an A-dio signal, which is applied to a speaker (not shown). The front end output passes through a filter 5 for detecting adjacent stations and becomes an input to a level detector 6, and the output of this detector 6 becomes an interference wave detection output.

In such a configuration, if the passband characteristic of the interference wave detection filter 5 is as shown in FIG. 2, the adjacent station signal included in the received signal will be extracted. In FIG. 2, it is assumed that the IF frequency is 450 K H7 and the device spacing is 9 K +-12.

Therefore, the level of the extracted output of this filter 5 is detected by the detector 6.
If detected by this method, it becomes possible to detect interference waves.

However, in this configuration, the characteristics of the filter 5 are
It is necessary to set the filter as shown in the figure, and variations in the characteristics of the fill 9 and temperature characteristics become important problems, and there is a drawback of lack of reliability.

An object of the present invention is to provide an interference wave detection circuit for a receiver that can detect interference waves from adjacent stations with high reliability.

The interference wave detection circuit according to the present invention has the following characteristics:
means for generating a reference signal phase-synchronized with the reference signal; means for multiplying the reference signal by the received signal to extract a low frequency component of the multiplication output; limiter means for removing the amplitude fluctuation component of the received signal; A means for multiplying the output horn of the limiter means by the received signal to extract a low-frequency component of the n-th power output, and a difference means for generating a signal corresponding to the difference in the low-frequency component of the output of the square product. and the output of the difference means is used as an interference wave detection output.

Embodiment An embodiment of the present invention will be described below using FIG. 3.

In FIG. 3, parts equivalent to those in FIG. 1 are indicated by the same reference numerals, and 1 to 3 are equivalent to those in FIG. 1. I
This is one input of the IF multiplied signal synchronous detector 7 of the F amplifier 3, and the detected output becomes the A-dio signal. The IF multiplied signal also becomes one input of a PLL (phase locked loop circuit) 9 and a synchronous detector 10 via a limiter 8 .

An IF multiplied signal is applied to each input of the synchronous detector 1O, and an output of a PLL circuit is applied to each input of the synchronous detector 7. The outputs of both synchronous detectors 7 and 10 are supplied to a difference detector 11, and the difference component of the detected signals is derived as an interference wave detection output.

The operating principle of the circuit shown in FIG. 3 will be explained below.

For simplicity, it is assumed that the received signal is a non-modulated wave. If the desired wave is Aalsωct and the interference wave is BωSω (then
The received signal of the receiver is expressed by the following formula (ω−ωC+Δω).

f(t)−Aa+sωOt+Bosωt= A cos
ωct+Bcos(ω+Δω)t=A (1+ ([3
/A>2+2 (B/A)ωSΔω)″ ωS(ωat
+ψ(t))...(1) Here, ψN) =
tan −+ ((B/A) s+n8c+t/ (
1+([3/A)cDsΔωt), where Δω is the broadcast station interval frequency. The amplitude fluctuation component of the signal [(1) of equation (1) is removed by the limiter 8. In reality, this limiter action generates a high frequency, but since the frequency is high, it is easily removed after synchronous detection in the subsequent stage, so this high frequency is not considered.

From equation (1), the output of this limiter 8 is cos(ccrct+ψ(t)) ・−・−・(2
). On the other hand, since the signal generated by the PLL circuit 9 is locked to the desired wave, ωSωct
・・・・・・(3) It becomes.

Therefore, each detection port of the synchronous detectors 7 and 1o,
The exclamation ωat of equation (3) for [([) of equation (1) and (2
) of the equation cos(ωct+ψ(t)) 'i, and the low frequency component of the output of these multiplications is △/2+(B/2)
Range Δωt...(4)(A/2)'(1+(B/
AM +2 (B/A)ωSΔωt)k ・・・・・・
(5) It becomes. The DC component of equation (7I) is A/2, and (5)
The approximation of the DC component in the equation is (Δ2+32)''/2, and the difference between these two DC components corresponds to the interference wave level, which is expressed by the following equation.

(1/2>(A・10B・)ori −A)・・・・・・(6
) The output of the difference detector 11 expressed by equation (6) becomes the interference wave detection signal.

FIG. 4 is a specific circuit diagram of the synchronous detectors 7, 1O and the difference detector 11 of the apparatus shown in FIG. , the difference detector 11 has a differential amplifier configuration that receives DC components obtained by smoothing these multiplication outputs by capacitors C+ and C2, respectively. Differential transistor QI
3. A detection output is generated from the collector resistance RL of the transistor Q+< on the other side of QI4.

In the figure, 01 to Q6 are transistors of a double-balanced differential circuit that constitutes the synchronous detector 10, and 0
7 to QI2 are transistors of a double-balanced differential circuit constituting the synchronous detector 7.

APPLICATION EXAMPLE FIG. 5 is a diagram showing an application example of the present invention, in which the detection output of the difference detector 11 of FIG. Q1
The impedance of the detector 6 is controlled depending on the interference wave, so as to control the passage characteristics of the detection output (A-D output) from the synchronous detector 7. That is, the output of this synchronous detector 7 is input to the filter circuit consisting of a resistor R2, a capacitor IC3, and the transistor QI6 via an emitter 7709 circuit consisting of a transistor QCs and a resistor R1. This filter output is supplied to the A-D Δ amplifier 12.

In other words, if the output of the detector 11 increases as the interference level increases, the impedance of the transistor QI6 decreases and the A-D1 passband changes. It is possible to reduce the influence of interference waves.

As described above, according to the present invention, since there is no need to use a special filter for detecting interference waves, it is possible to detect tiJ harmful waves with high reliability. Further, by adopting the configuration shown in FIG. 4, it becomes suitable for IC (integrated circuit) and can be miniaturized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional receiver with an interference wave detection function, and Fig. 2 is a characteristic diagram of the interference wave detection filter shown in Fig. 1.
FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 shows a specific example of a part of the blocks in FIG. 3, and FIG. 5 is a circuit diagram of an applied example of the present invention. Explanation of symbols of main parts 7.10... Synchronous detector 8... Limiter 9... P L 1 circuit 11... Difference detector Applicant: Pioneer Agent Co., Ltd. Patent attorney Motohiko Fujimura (1 other person)

Claims (1)

[Claims] Is the received signal strong? means for generating a reference signal that is phase-synchronized with the received signal; means for multiplying the reference signal and the received signal to extract and cover the low-frequency component of the multiplication error; and amplitude fluctuation of the received signal. limiter means for removing the component; means for multiplying the output of the limiter means by the received signal to extract a low frequency component of the multiplication output; and differential means for generating a signal,
An interference wave detection circuit for a receiver characterized in that the output of the difference means is used as an interference wave detection output.