JPS6016131B2 - Acyclic digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an acyclic digital filter having linear phase characteristics.

As is well known, an acyclic digital filter is used at time nT(
n is a positive integer, T is the sampling time interval), the output at y(n
T), time nT, nT-T, nT-2r,...
, nT-rT as x(nT) and x(
nT-T), x (nT-T), ..., x (nT-rT)
Then, the input/output relationship is expressed by an r-order difference equation.

Here, Li (i=o, . . . r) is a real constant that determines the transmission characteristics of the acyclic digital filter. This formula {1'
can be realized as shown in FIG. That is, input terminal 1
The input signal from is supplied to one end of a circuit in which delay circuits D and ~Dr with a delay time T are sequentially connected in series, and the signal from input terminal 1 and the output signal of each delay circuit D and ~Dr are as follows. are supplied to multipliers Mo to Mr, respectively, and L
Multiplied by o~Lr. These equal multiplication outputs are added in an adder S, and the filter output y(nT) is output from the output terminal 2.
is obtained. This conventional acyclic digital filter requires (r+1) multipliers, which increases the number of multipliers, making it expensive and large.

It is possible to use one multiplier in a time-sharing manner, but this would require (r11) multiplications within one sample interval T, requiring a high-speed multiplier and an expensive one. become.

The object of the present invention is to provide an acyclic digital filter which has a relatively simple configuration, has a small number of multipliers, or a small number of multiplications, and therefore, when multiplication is performed in a time-division manner, it operates at low speed and can be constructed at low cost. Our goal is to provide the following. Formula '1}
is the equation shown in the time domain, but the transfer characteristic of this digital filter in the frequency domain is given by.

is the angular frequency and i is the imaginary unit. By the way, if r is an even number, equation {2} can be rewritten as follows.

The term before L in [ ] of this formula is , and the latter term is Therefore, equation (2} becomes as follows.

Putting this formula [3}' If holds true, then the formula {3- So, the phase angle 0 (of) of the sun (of) is a(no)=Kyo's T(radian) '6'.

Equation (6'') shows that the phase angle of `` is a straight line with respect to '', that is, the phase characteristic of this digital filter is a straight line with respect to . If the phase characteristic of the filter is linear with respect to
The relationship of formula [41 holds, therefore, L=Lr, L,=Lr
-. . . - Therefore, in Fig. 1, the output of the multiplier pigeon and the output of the multiplier Mr are the same except that the latter is delayed by rT, and similarly the output of the multiplier M, The outputs of the multiplier Mr- and the multiplier Mr-, are also the same, and the following is the same machine. Therefore, instead of the outputs of the multipliers Mr, Mr-, the outputs of the multipliers Mo, M can be used as outputs delayed by rT and (r-1)T, respectively. Other multipliers M...
...The same can be said about Mr2. Therefore, the present invention delays the multiplication of each output of the first half of the delay circuit in an acyclic digital filter by a filter constant, and simultaneously supplies the delayed and non-delayed outputs to an adder. The latter half of the acyclic digital filter is omitted.

For example, as shown in FIG. 2, delay circuits D, . . . , D, whose delay time is equal to the sampling interval T, are connected in series. The number r/2 of delay circuits is half that of the conventional case shown in FIG. The input of the input terminal 1 and the output of each delay circuit D, .about.D are respectively multipliers M. supplied to the body. This multiplier Mo
Each output of ~M on-, has a delay time rT, (r-
2) T... is supplied to the system registers Ro to R as delay circuits of 4T and 2T. The shift stages of these shift registers are r, r-2, respectively...
4,2, and the multipliers Mo to M are activated in synchronization with the delay circuits D and D at the time interval of the sampling time T of the input x(nT).
, and performs a shift operation on the outputs supplied respectively. The outputs of these shift registers Ro to R and the outputs of the multipliers Mo to M are sent to an adder S. In this configuration, since the relationship of the above formula {4) holds,
The same output as the multiplier Mr in FIG. 1 is obtained from the shift register Ro, and the same output as the multiplier MH in FIG. 1 is obtained from the shift register R. The inputs supplied to the device S will be the same as in FIG.

However, in the configuration shown in Figure 2, the number of multiplications required to calculate the output y (nT) is (r/21), which is half the number of multiplications compared to the configuration shown in Figure 1. . This means that
When one multiplier is used in a time-sharing manner to perform (r/21) times of multiplication, the time allowed for one multiplication almost doubles, resulting in a slower processing speed of the arithmetic circuit. It has the advantage that it can be used. Furthermore, when (r/21) multipliers are used and each multiplier performs one multiplication, there is an advantage that the number of multipliers can be reduced to approximately half. Furthermore, the delay circuit D is also half of that in the case of FIG. However, shift registers Ro to R, are added to the case in Figure 1, but shift registers are simpler and cheaper in structure and cost than multipliers, and overall, The configuration is simple and inexpensive. Note that this filter is limited to the condition of equation (2), that is, the phase characteristic is linear with respect to , but it is practical because the filters currently used often require the above condition. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional non-recurring digital filter, and FIG. 2 is a block diagram showing an example of a non-recurring digital filter according to the present invention. 1...Input terminal, 2...Output terminal, D. ~Dte...
・Delay circuit, Mo to M... Multiplier, Ro to R.
...Shift register as delay means, S...addition circuit. Group l diagram Figure 2

Claims (1)

[Claims] 1 When an input signal is supplied, the maximum delay amount at which outputs that are sequentially delayed for each sampling time interval T is r/2T.
(r is a positive even number), means for multiplying the input signal and each sequentially delayed output of the delay circuit by a constant coefficient defining filter characteristics, and rT, respectively, for each of the multiplication results. (r-2)T...Equipped with means for delaying by 4T, 2T, and an addition circuit for adding all of the delayed multiplication results and the undelayed multiplication results, so that the phase characteristic is different from the angular frequency. An acyclic digital filter that is linear.