JPS6016745A - Priority recognizing system in loop form network - Google Patents
Priority recognizing system in loop form networkInfo
- Publication number
- JPS6016745A JPS6016745A JP12448183A JP12448183A JPS6016745A JP S6016745 A JPS6016745 A JP S6016745A JP 12448183 A JP12448183 A JP 12448183A JP 12448183 A JP12448183 A JP 12448183A JP S6016745 A JPS6016745 A JP S6016745A
- Authority
- JP
- Japan
- Prior art keywords
- priority
- station
- signal
- counter
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 22
- 230000000737 periodic effect Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 description 3
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/427—Loop networks with decentralised control
- H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0614—Systems characterised by the synchronising information used the synchronising signal being characterised by the amplitude, duration or polarity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は優先度付き通信を提供するループ式ネットワー
クにおいて、各ノードステーションが優先度を認識する
方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scheme in which each node station is aware of its priority in a looped network providing prioritized communications.
優先度伺き通信を提供するループ式ネットワークとして
は、特許用93番号昭58−54117記載のネットワ
ークがある。かかるネットワークは第1図に示すように
複数のノードステージせン1,2゜3、 4. 5.
6及びクロックステーシコン8とから構成されとれらス
テーションはループ状伝送路7により接続されている。As a loop type network that provides priority-based communication, there is a network described in Patent No. 93-58-54117. Such a network consists of multiple node stages 1, 2, 3, 4, as shown in FIG. 5.
6 and a clock station controller 8, these stations are connected by a loop-shaped transmission path 7.
この従来例においては、優先度を示す情報を、信号プロ
、りに付加することにより各ノードステーションに通知
している。In this conventional example, each node station is notified by adding information indicating the priority to the signal processor.
第2図にこの従来例が用いている信号ブロックの構成を
示す。第2図(a)はノードステーション間通信に用い
る信号ブロックを示し、プリアンプル信号PR1開始フ
ラグSF1同期ピッ)FIY、優先情報prtr、あて
先アドレスDA、発信者アドレスS人、情報INFO及
び終了フラグEFとから構成されている。第2図(b>
はクロックステーション8が送信する同期信号及びトリ
ガ信号の構成を示している。クロックステーション8は
一定の周期Toでビット5Y=1、P′fLI = 0
00の周期信号SYNを第3図に示すようにループに供
給する。このPRI=000は最高位の優先レベル0を
与える。各ノードステーションはこの同期信号SYNの
通過を検出すると、周期Toに同期するために内蔵のタ
イマをリセットすると共に、PRIを読みPRIの与え
る優先レベルこの場合レベルOとレベルの送信衆求があ
れば第3図に示すように、第2図(a)の構成を有する
信号ブロックPKTを同期信号syNの後、あるいは上
流のノードステーションから既に信号ブロックPKTが
送出されている場合はその後に送出する。クロックステ
ーション8は伝送路7を一巡してきた同期信号SYNを
除去すると共に、除去した後送信権を獲得するとPRl
、=001とするトリガ信号TR’GIを伝送路7に送
出する。これは優先レベルOよシ1つレベルの低い優先
レベル1を与える。以下同様にしてPRI=010のト
リガ信号’I’ RG 2によシ更に低位の優先レベル
2を与える。以上のようにして伝送路7で行なわれる通
信の優先度を与えているが、この従来例では次の問題点
がある。即ち、優先レベルの数が増大すると優先情報P
RIのビット長が長くなる、つまシ、信号ブロックの固
定部分が長くなるので伝送効率が低下する。FIG. 2 shows the configuration of a signal block used in this conventional example. FIG. 2(a) shows signal blocks used for node-station communication, including preamble signal PR1 start flag SF1 synchronization signal FIY, priority information prtr, destination address DA, sender address S person, information INFO, and end flag EF. It is composed of. Figure 2 (b>
shows the structure of the synchronization signal and trigger signal transmitted by the clock station 8. Clock station 8 has a constant period To, bit 5Y = 1, P'fLI = 0
A periodic signal SYN of 00 is supplied to the loop as shown in FIG. This PRI=000 gives the highest priority level 0. When each node station detects the passage of this synchronization signal SYN, it resets its built-in timer to synchronize with the period To, reads the PRI, and indicates the priority level given by the PRI. As shown in FIG. 3, the signal block PKT having the configuration shown in FIG. 2(a) is sent out after the synchronization signal syN, or after the signal block PKT has already been sent out from the upstream node station. The clock station 8 removes the synchronization signal SYN that has made a round on the transmission line 7, and after obtaining the transmission right, the clock station 8 issues PRl.
, =001 is sent to the transmission line 7. This gives priority level 1, which is one level lower than priority level O. Thereafter, a lower priority level 2 is given to the trigger signal 'I' RG 2 of PRI=010 in the same manner. Although priority is given to the communication carried out on the transmission line 7 as described above, this conventional example has the following problems. That is, as the number of priority levels increases, the priority information P
Since the bit length of the RI becomes longer, the fixed portion of the signal block becomes longer, and the transmission efficiency decreases.
本発明の目的は信号ブロックの固定部分を短かくし伝送
効率の良い優先度付き通信を提供することにある。An object of the present invention is to provide prioritized communication with high transmission efficiency by shortening the fixed portion of a signal block.
本発明によれば、各ノードステーションは前記ループ状
伝送路を通過する前記トリガ信号の数を計数するカウン
タ回路を有するとともに、前記同期信号を受信したとき
前記カウンタ回路をリセリトン、前記カウンタ回路の出
力よシ送信可能な通信の優先度を認識する。本発明によ
る優先度8識方式に用いる信号ブロックの構成を第4図
に示す。According to the present invention, each node station has a counter circuit that counts the number of the trigger signals passing through the loop-shaped transmission path, and when receiving the synchronization signal, the counter circuit is reset and the output of the counter circuit is Recognize the priority of communications that can be sent. FIG. 4 shows the configuration of a signal block used in the eight-priority system according to the present invention.
第4図(、)はノードステーション間通信に用いる信号
ブロックを示し、同図(b)は同期信号及びトリガ信号
を示す。第4図の構成社第2図の構成の優先情報P R
,Iがピッ)TGに置きかわったものである。第4図に
おいて、同期信号であることはビット8Y=1、)リガ
信号があることはビットTG−1により示す。ノードス
テーションが送出する信号ブロックにおいては、5Y=
−TO=0となっている。クロックステーション8は、
5Y=1、TG=0の同期信号8YNを第5図(a)に
示すように周期Toで送出し、次に送信権を獲得した時
SY−〇、TO=1のトリガ信号TR,Gを送出する。FIG. 4(,) shows a signal block used for node-station communication, and FIG. 4(b) shows a synchronization signal and a trigger signal. Priority information for the constituent companies in Figure 4 and the composition in Figure 2 P R
, I is replaced by TG. In FIG. 4, bit 8Y=1 indicates that the signal is a synchronization signal, and bit TG-1 indicates that there is a trigger signal. In the signal block sent by the node station, 5Y=
-TO=0. Clock station 8 is
5A synchronization signal 8YN with Y=1 and TG=0 is sent out at a period To as shown in FIG. Send.
以降、周期To内で、送信権を獲得する度にトリガ信号
TRGを〈シ返し送出する。各ノードステーションは、
ピッ)SY=1を受信すると内蔵のカウンタをクリアす
ると共にビットTG=1を検出するとカウンタを1つず
つインクリメントする。Thereafter, within the period To, the trigger signal TRG is repeatedly sent out every time the transmission right is acquired. Each node station is
B) When SY=1 is received, the built-in counter is cleared, and when bit TG=1 is detected, the counter is incremented by one.
この時のカウンタの出力を第5図(b)に示す。この出
力は優先レベルに対応しておシ、各ノードステーション
はカウンタの出力にもとづいて送信を行なう。The output of the counter at this time is shown in FIG. 5(b). This output corresponds to the priority level, and each node station performs transmission based on the output of the counter.
本発明におけるノードステーションの構成を第6図に示
す。第6図のノードステーションは伝送路7につながれ
た入力端子10.出力端子11を有すると共に、信号検
出回路12、制御回路13、バッファ18、カウンタ1
4、タイマ15、送信バッファ16.スイッチ17とか
ら′4i1成されている。信号検出回路12は、バッフ
ァ18を介し受信される信号ブロックからビット5y=
iを検出したときタイマ15及びカウンタ14をリセッ
トする。まだ、ビットTG=1を検出したときカウンタ
14を1つインクリメントする。制御回路13はカウン
タ14の出力よシ優先レベルを認識し、この優先レベル
と同じあるいは高い優先レベルの送信が生起した場合、
送信権を獲得した後、スイッチ17を送信バッファ16
側に接続し送信を行なう。送信される信号ブロックは、
ビット5Y=TO=Oとする。なお以上の説明では同期
信号は5Y=1、TO=0としたが、8Y=T(j=1
としてもよい。この場合、各7−ドステーシヨンの制御
回路12は5Y=1を検出した場合カウンタ14のクリ
アを行ない、インクリメントは行なわhい。FIG. 6 shows the configuration of the node station in the present invention. The node station in FIG. 6 has an input terminal 10 connected to a transmission line 7. It has an output terminal 11, a signal detection circuit 12, a control circuit 13, a buffer 18, and a counter 1.
4, timer 15, transmission buffer 16. '4i1' is formed from the switch 17. The signal detection circuit 12 detects bit 5y=from the signal block received via the buffer 18.
When i is detected, the timer 15 and counter 14 are reset. Still, when bit TG=1 is detected, the counter 14 is incremented by one. The control circuit 13 recognizes the priority level from the output of the counter 14, and when a transmission with a priority level equal to or higher than this priority level occurs,
After acquiring the transmission right, the switch 17 is transferred to the transmission buffer 16.
Connect to the side and perform transmission. The signal block to be transmitted is
Bit 5Y=TO=O. Note that in the above explanation, the synchronization signal is 5Y=1, TO=0, but 8Y=T (j=1
You can also use it as In this case, when the control circuit 12 of each 7-station station detects 5Y=1, it clears the counter 14 and does not increment it.
このように本発明によれば、送出する信号ブロックに優
先情報を付加しなくてもトリガピットを設けることによ
シ多数のレベルの優先通信を捉供することができ、その
結果通信の伝送効率を向上させることができる。As described above, according to the present invention, by providing trigger pits without adding priority information to the signal blocks to be transmitted, it is possible to capture and provide priority communications at many levels, and as a result, the transmission efficiency of communications can be improved. can be improved.
第1図は本発明におけるループ式ネ、トワークの構成を
示す図、第2図は従来例におりる信月ブロックの構成、
第3図は従来例における8IΦ作タイ示す[ネ]、第6
図は本発明の実施例を示す図である。
第1図及び第6図において、1. 2. 3. 4.
5゜6?」、ノードステーション、7は伝送路、8はク
ロックステーション、12は信号検出回路、13は制御
’++11回路、14はカウンタ、15はタイマ、16
け送イ[jバッファ、17はスイッチを示す。
71 図
第2図
第3図
0 1 2FIG. 1 is a diagram showing the configuration of the loop type network in the present invention, and FIG. 2 is the configuration of the Shinzuki block in the conventional example.
Figure 3 shows the 8IΦ production tie in the conventional example [ne], the 6th
The figure shows an embodiment of the present invention. In FIGS. 1 and 6, 1. 2. 3. 4.
5°6? '', node station, 7 is a transmission line, 8 is a clock station, 12 is a signal detection circuit, 13 is a control '++11 circuit, 14 is a counter, 15 is a timer, 16
17 indicates a switch. 71 Figure 2 Figure 3 0 1 2
Claims (1)
ループ状伝送路により接続され、前記クロックステーシ
ョンが一定の周期で同期信号を供給し更に前記周期内で
トリガ信号を供給するループ式ネットワークにおいて、
前記ノードステーションは前記ループ状伝送路を通過す
る前記トリガ信号の数を計数するカウンタ回路を有する
とともに、前記周期信号を受信したとき前記カウンタ回
路をリセットし、前記カウンタ回路の出力より送信iT
J能な通信の優先度を認識することを特徴とするループ
式ネットワークにおける優先度認識方式。In a loop type network in which a plurality of node stations and a clock station are connected by a loop-shaped transmission line, and the clock station supplies a synchronization signal at a constant cycle and further supplies a trigger signal within the cycle,
The node station has a counter circuit that counts the number of trigger signals passing through the loop-shaped transmission path, resets the counter circuit when receiving the periodic signal, and calculates the transmission iT from the output of the counter circuit.
A priority recognition method in a loop type network, which is characterized by recognizing the priority of communication.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12448183A JPS6016745A (en) | 1983-07-08 | 1983-07-08 | Priority recognizing system in loop form network |
| CA000442460A CA1201784A (en) | 1982-12-03 | 1983-12-02 | Loop network system controlled by a simple clock station |
| DE8383112151T DE3382313D1 (en) | 1982-12-03 | 1983-12-02 | RING NETWORK CONTROLLED BY A SIMPLE CLOCK STATION. |
| EP83112151A EP0111277B1 (en) | 1982-12-03 | 1983-12-02 | Loop network system controlled by a simple clock station |
| US06/824,035 US4627051A (en) | 1982-12-03 | 1986-01-30 | Loop network system controlled by a simple clock station |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12448183A JPS6016745A (en) | 1983-07-08 | 1983-07-08 | Priority recognizing system in loop form network |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6016745A true JPS6016745A (en) | 1985-01-28 |
Family
ID=14886583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12448183A Pending JPS6016745A (en) | 1982-12-03 | 1983-07-08 | Priority recognizing system in loop form network |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6016745A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175429A (en) * | 1987-12-29 | 1989-07-11 | Hitachi Chem Co Ltd | Communication system and equipment |
-
1983
- 1983-07-08 JP JP12448183A patent/JPS6016745A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175429A (en) * | 1987-12-29 | 1989-07-11 | Hitachi Chem Co Ltd | Communication system and equipment |
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