JPS60170184A - Induction heater - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A) Field of Industrial Application The present invention relates to an induction heating device using a digital control circuit.

The conventional induction heating device consists of a heating filter connected to a DC power supply, a capacitor and a switching element that do not form a resonant circuit with this heating coil, and the switching element is set to 0NSOF.
F control generates a resonant current in the heating coil, generates an alternating magnetic field in the heating coil, and inductively heats an object to be heated made of ferrous metal placed close to the heating filter. . In such an induction heating device, the switching elements are ONL,
The timing from turning on to turning off was determined using an RC time constant circuit.

However, in the RC time constant circuit, the time constant changes greatly over time and temperature, making it impossible to accurately maintain the ON period of the switch notching element, resulting in an inconvenience in that the output deviates from the set value. Additionally, when using cooking utensils made of low-resistance non-magnetic materials such as aluminum, the equivalent resistance and equivalent inductance of the heating coil become small, and as the ON time of the switching element increases, the amount of current flowing through the switching element increases. There was a risk of thermal destruction. For this reason, a conventional method has been adopted in which the AC input tfi to the inverter circuit is detected by a current transformer or the like, and the switching element is stopped when the current value exceeds a predetermined value. However, when using this method to prevent overcurrents in switching elements, input detection must be performed by detecting low-frequency AC input current, which increases the time required for detection and makes it difficult to provide overcurrent protection. There was an inconvenience that it took time.

c) Purpose of the invention The present invention has been made in view of the above points, and
The purpose is to quickly provide overcurrent protection for switching elements.

2) Structure of the Invention The present invention detects the resonance period of the inverter for each oscillation when cooking utensils are installed, sets limit data Icp according to the length of this period, and uses this limit data Icp to control the switching elements. A configuration is adopted that limits the ON period length.

(E) Embodiment FIG. 1 is a circuit diagram of an inverter circuit used in the induction heating device of the present invention, in which (1) is an aftereffect rectifier circuit for full-wave rectification of AC power supply voltage, and (2) is a circuit diagram for this full-wave rectification. A choke coil connected to the output terminal of the circuit (1), (3) a filter capacitor that forms a filter circuit together with this choke coil (2), and (4) a filter capacitor (3) that is connected to the output terminal of the circuit (1).
) is connected to one end of the induction heating coil, (5) is a resonant capacitor that forms a resonant circuit together with this induction heating filter (4), and (6> is a transistor etc. connected in parallel to this resonant capacitor (5). Switching element, (?')
is a damper diode connected in antiparallel to this switching element. (8) is turned ON by the control circuit described later.
, shows a drive circuit that turns on and off the switching element (6) in response to an OFF signal, and this drive circuit (
8) is provided with a differentiating circuit consisting of a resistor (9) and a capacitor (10), so that switching rises and falls rapidly. (11) is a current transformer provided in the Act source line, which detects the alternating current input to this inverter circuit.

In such an inverter, the switching element (6) is turned on and off as shown in FIG. 2A via the drive circuit (8).
When an OFF signal is applied, this switching element (6
) flows through the current Ic shown in B of the same figure, and the voltage VCE between the terminals of this switching element (6) fluctuates as shown in C of the same figure. At this time, a resonant current flows through the heating coil (4), generating a high-frequency alternating magnetic field, and cooking utensils (1) such as pots made of iron or 18-8 stainless metal near the heating coil (4).
2>, and this cooking utensil (12) is heated by induction. Incidentally, here, V con is the aftereffect rectification voltage transmitted from the aftereffect rectification circuit (1>) via the choke coil (2).

FIG. 3 is a block diagram showing the control circuit of such an induction heating device, where (13> is the current transformer <1
2) The input current value detected in step 2) is converted into digital input data p.
An A/D conversion circuit that converts to AD, (14) is this A/D
The conversion circuit (13) uses the sample signal that provides the timing for A/D conversion and the AC power supply voltage at full wave! ! This shows a timing generation circuit that generates a MINT signal synchronized with the low potential part of the flowing pulsating current, and generates the Sample signal and MI
Outputs NT signal.

(15) receives the input data (PAD) from the A/D conversion circuit (13), and determines whether small items such as ifs, forks, etc. are placed near the heating filter (4), or if there is no This is an inappropriate load detection circuit that detects a no-load state where no load is placed, and issues a prohibition signal when the input data PAD is less than a predetermined value. (16) is a desotal value and is power setting data P according to the power that should be output from this cooker.
A power setting circuit in which ref is set, <17> is a SUB circuit which receives setting data P ref from this power setting circuit (16) and receives input data PAD from the A/D conversion circuit (13). P r
The value p ref obtained by subtracting the input data PAD from ef
-PAD can output completely. (18) is ON period data P corresponding to the time to turn on the switching element 6).
ON period setting means for setting the above-mentioned S.
Difference data P ref −PAD obtained by subtracting the input data PAD from the setting data P ref from the UB circuit (17)
In response to this, the ON period data P con can be adjusted.

(19) is the DC voltage V from the above full-wave rectifier circuit (1)
By comparing the terminal voltage VcE of the switching element (6) and the terminal voltage VcE of the switching element (6), it is determined that VCF is "L" during the resonance period when Vcon is > Vcon.
It is a resonance period detection circuit that outputs a level detection signal, and also serves as an on-timing detection means to notify the timing to turn on the switching element 6) by the extinction of the detection signal when V CE < V COn. (20) measures the resonance period length using the detection signal from this resonance period detection circuit (19), and generates limit data Icp for limiting the ON time of the switching element (6) according to this resonance period length. The overcurrent protection setting circuit prevents large current from flowing to the switching element (6). (21) receives the detection signal from the resonance period detection circuit (19) and detects the detection signal. The counting operation is started from the time of completion, and when the counted value becomes the same as the ON period data Pcan of the ON period setting means (18) or the limit data Icp of the overcurrent protection setting circuit 20), a match signal is generated. The CIN period counting circuit (22) outputs the signal at the end of the detection signal from the resonance period detection circuit (19), that is, when the VC
This circuit shows a flip-flop circuit that is set when E < V can and is reset by a match signal from the ON period counting circuit (20). A control signal for controlling 0N3OFF of the changing switching element (6) is sent to the drive circuit (8). In addition, this flip-flop circuit (22> is 1−subordinate appropriate load detection circuit<1
The structure is such that this operation can be prohibited by the improper load detection circuit from 5).

In such a control circuit, during operation of the cooker, the detection signal of "L" level from the resonance period detection circuit (19) disappears, and when the output reaches "H" level, the solid flop circuit (22) is set, and the drive circuit (6) of the switching element (6>) is transmitted from this flip-flop circuit (22).
Send ON signal to 8). At the same time, due to the disappearance of the detection signal, the ON period counting circuit (21) performs a counting operation, and normally, when this count value matches the data P con in the ON period setting means (18>), the flip-flop circuit < 22) A reset/to signal is sent. by this,
The flip-flop circuit (22) is reset and an OFF signal of the switching element (6) is sent to the drive circuit (8). That is, during normal operation, the ON period setting means (L) is
The ON period of the switching element is determined by the ON period data P con outputted from 18).

On the other hand, the power setting data P ref set by the power setting circuit (16) and the input data PAD obtained by A/D converting the input current value proportional to the AC input power by the A/D converter circuit (13). The signal is transmitted to the SUB circuit (17) in response to the Sample signal, and this SUBm circuit (17) sets the data value Pref-PAD, which is obtained by subtracting the input data PAD from the power setting data Pref, to the ON period setting means (18).
). Turns on after receiving this data P ref PAD
The period setting means (18) adds P ref PAD to the initially set ON period data P can to set a new ON period.
Use period data. This means that when the input data pAD is smaller than the power setting data P ref, the ON period data is increased to lengthen the ON period of the switching element (6) and the input power is increased; When the data P ref is smaller than the data P ref, the ON period data P con is reduced to shorten the ON period of the switching element (6), thereby reducing the input power. Such operations are repeated until the input data PAp matches the power setting data P ref. For this reason,
The input power, which fluctuates depending on the material, shape, and conductivity of the pot used, is automatically adjusted to remain constant.

In addition, when the inverter is heated with a small load or no load, the input current value detected by the input current transformer (11) becomes low, and the data PAD output from the A/D conversion circuit (13) also becomes small. I hear it. The inappropriate load detection circuit (15) detects that the value of such input data PAD is lower than a predetermined value and activates the free knob flop circuit (22).
to be prohibited. Therefore, the flip-flop circuit (22
) to the drive circuit (8) of the switching element (6>)
N, OFF signals are prohibited. At this time, the above predetermined value is the power setting data Pre of the power setting circuit 16).
It is preferable to change it in conjunction with a power setting knob (not shown) so that when the value of f is set to a large value, the value becomes thick (and when the value of Pref is set to a small value, it becomes small).

Furthermore, when a cooking utensil made of a non-magnetic material such as aluminum is placed close to the heating coil (4) and heated, the equivalent inductance of the heating coil (4) is lower than when a magnetic cooking utensil is used. Therefore, after the switching element (6) is turned off, the switching element (6) terminal voltage VC
The length of the resonance period in which E is higher than the DC voltage V con from the full-wave rectifier circuit (1) becomes shorter. The resonance period detection circuit (19) detects this period, and the overcurrent protection setting circuit (20) reduces the value of limit data fcp that limits the ON period according to the detected resonance period length. As a result, even if the ON period data P con of the numerical value setting means (18) is set to a large value so as to lengthen the ON period of the switching element (6), the count of the ON period counter circuit (21>) will not exceed the above-mentioned overcurrent protection setting. Limit data Icp of circuit (20)
6) O) There is no danger that the ON period of the switching element will be shortened and a large current will flow through the switching element.

Next, a detailed explanation of each block will be given.

FIG. 4 is an embodiment circuit diagram of the A/D conversion circuit (13), in which (23) is a full-wave rectifier circuit that rectifies the alternating current voltage from the current transformer (11), and (24) is a full-wave rectifier circuit that rectifies the alternating current voltage from the current transformer (11). A first operational amplifier amplifies the signal from this rectifier circuit (23), (25) is a peak hold capacitor that is charged by the output of this first operational amplifier, and <26) is a peak hold capacitor (25) that is charged by the output of this first operational amplifier. It shows FETs connected in parallel, with a diode (27) and a capacitor (28).
) to its gate electrode through a parallel circuit consisting of
Receive le signal. As this Sample signal, as will be described later, a signal given at the peak timing of the pulsating current obtained by full-wave rectification of the AC voltage is used. <29>
(30) is a second operational amplifier that amplifies the terminal voltage of the peak hold capacitor (25), and (30) is a first operational amplifier that receives the output VCT of this second operational amplifier (29) at its input terminal.
comparator, (31) is this first comparator (
30) to the drive terminal (D), and a terminal (SC) for starting the operation.
), a signal is input to the clock input terminal (CLOCK) to change and output the 4-bit output QO-Q5. (32) is a D/A converter that performs D/A conversion on the output of this register (31), and its output is input to the e input terminal of the first comparator (30).

(33) shows a latch circuit that latches the output of the successive approximation register (31), and this A/D conversion circuit (1
When the A/D conversion is completed in step 3), a check operation is performed and the output Qo -Q3 of the successive approximation register (31) is outputted as the input data PAD.

FIG. 5 shows a specific circuit diagram of the timing signal generation circuit, where (34) is a full-wave rectifier circuit that full-wave rectifies the AC power supply voltage, and (35) is a full-wave rectifier circuit that performs full-wave rectification from this full-wave rectifier circuit (34). Input the voltage to the input terminal, and connect the voltage regulator Vc to the resistor (35
) (36) is a third humpator that inputs the voltage V divided by
37) and becomes a Sample signal. (38) inputs the full-wave rectified voltage from the full-wave rectifier circuit 34〉 to the input power, and inputs the voltage VB obtained by dividing the constant voltage +Vc by the resistor (39) < 40) to the e input terminal. A third humperator is shown, the output of which is the MINT signal. Note that the above VA is set to be slightly lower than the peak voltage of the source voltage AC', and the above VB is set to be slightly higher than zero voltage. By doing this, the Sample signal as shown in Fig. 6 is emitted near the peak of the ACC electric voltage, and the
A T signal is generated near zero AC power supply voltage.

In such an A/D conversion circuit (13) and a timing signal generation circuit (14), a current transformer (11)
The signal detected according to the input current is passed through the first operational amplifier (24) to the peak hold capacitor (25).
is transmitted to the terminal. When the Act source voltage voltage wave rectification pressure value is low, there is no sample signal, so the FET (26) is turned off.
Is it in N state and is it condensed? (25) is not charged. When the full-wave rectified voltage of the AC power source approaches the peak, S is sent from the timing generation circuit (14) to the gate of the FET (26).
Ample signal is sent and FET (26) is turned off.
do. At this time, the input current transmitted through the current transformer (11) and the full-wave rectifier circuit (23) also reaches the peak of each ripple current, and the peak hold capacitor (25)
A charge corresponding to the peak of the input current is accumulated in the input current. Thus, the voltage appearing at the capacitor (25) terminal passes through the second operational amplifier (29) to V. T is added to the Φ terminal of the first comparator (30). This signal V. Due to T, the first comparator (30) outputs a "H" level signal.

A start signal generated by the Sample signal and the 0N10FF signal of the switching element (6) is supplied to the terminal SC of the register (31), and the operation is started. When the first ON signal is completely supplied to the clock terminal, the D terminal is at "H" level, so the register (31) outputs Q. Q
1Q2Q6 becomes "i o o o".

This "1000"' is D/A converted by the D/A converter 32) and applied to the e input terminal of the humpator (30). In this state, for example, this comparator (30)
■When the input terminal voltage is higher than the e input terminal voltage, the D of the above register (31) is
The signal supplied to the terminal maintains the "H" level state. Therefore, this register (31>) outputs "1100", which is the previous output "1°00" plus "otoo", in synchronization with the rise of the next ON signal.
e of the comparator (30) via the converter (32)
given to the input terminal. At this time, for example, if the e input terminal voltage of this humparator (30) is higher than the input terminal voltage, its output becomes "L II level" and is applied to the D terminal of the register (31).・Since the L t+ level signal is given, the next ON
In synchronization with the rise of the signal, this register (31) receives the value obtained by subtracting "0010" from the previous output "1100".
1010"" is output. This successive approximation operation is further repeated and ends when the register (31) receives the ON signal five times. After this comparison operation is completed, the register (31)
31> is the output Q set by the above operation. -Q4 For example “
While holding 100 bits, connect the latch circuit (
33)-\Give signal. The latch circuit (33) uses this signal to output Q from the register (31). - Latch Q4.

In this embodiment, the A/D conversion circuit 13) is configured using one successive approximation register (31), but the
/D conversion circuit <13) is not limited to this method. Improper load detection circuit (15) and SUB circuit (1
7). The timing chart of this A/D conversion and the timing of the launch operation of the latch circuit <33) are shown in the seventh figure.
As shown in the figure. Here, DUTY is the timing at which the inverter is commanded to oscillate or stop under control from, for example, a duty control circuit (not shown), and duty is the timing at which the oscillation operation of the inverter is actually performed.

FIG. 8 is a block diagram for explaining the ON period setting means in more detail, in which (41) indicates the SUB circuit (
17) shows a prohibition circuit that receives the value Pref-PAD obtained by subtracting the human power data PAD from the power setting data Pref, and this data PrefP is set at the initial stage of inverter oscillation.
An adder circuit receives data from the AD inhibition circuit (41), and <43) represents a latch circuit that latches the output of this adder circuit (42), and its latch timing is determined by the above-mentioned MIN.
This is done in synchronization with the rising edge of the T signal, and its output is given to the ON period counting circuit (21). ) is the above latch circuit (
43) Output P con and soft start setting circuit 4
4) A selection circuit that receives the output 5of and selects which data to output.
of can be selected.

(46) represents a latch circuit that latches the output of the data selector (45), and the latched signal is input to the other input terminal of the adder circuit (42).

In such an ON period setting means, at the initial stage of inverter oscillation, the prohibition circuit (41) is in a prohibition state;
The data transmitted from this inhibition circuit (41) to the addition circuit (42) appears to be "o o o o". Further, the selection circuit (45) is in a state of outputting data 5oft of the soft start setting means (44). In such a state, the data 5oft is sent to the latch circuit (45) via the selection circuit (45), the latch circuit (46), and the adder circuit (42).
3) Given to. The latch circuit (43> is this 5of
t is output approximately at the timing of the MINT signal. After the inverter oscillation starts, the inhibit circuit (
41) releases the inhibited state, and the selection circuit (45) also selects the output of the latch circuit (43).

Therefore, the output P con from the latch circuit (43) is given to the adder circuit (42) via the selection circuit (45) and the latch circuit (46). In this addition circuit (42), data P ref -PAD transmitted from the subtraction circuit (17) via the inhibition circuit (41) is added to P con,
The signal is sent to the latch circuit (43). This Pconi(Pr
ef -PAD) is MIN in the latch circuit (43)
It can be latched as new ON period data at the timing of the T signal. In other words, it turns ON depending on the difference between P ref and PAD.
Period data P con is corrected sequentially. This kind of change in data can be expressed as a recurrence formula as follows.

Pconi; z Pcor+x-++(Pref-
PAD K) (k=1.2.3-= , Pcono-8
FIG. 9 shows a timing chart showing the timing at this time and a table showing the data transition. still,
Here, τ2+11-1 (m=1.2.3 ・) is the timing at which the latch circuit (46) input appears at its output.
12m (m=12.3...) is the timing at which the input to the latch circuit (43) appears at its output.

FIG. 10 is a block diagram showing a specific configuration of the ON period counting circuit. In the same figure, (47) indicates a clock oscillator that starts oscillation operation when the resonance period detection signal disappears from the resonance period detection circuit (19), that is, in response to the ON timing of the switching element (7). This operation is stopped depending on the off timing of element 7). (48) is an ON period counter that counts up by the clock signal from the clock oscillator (47), and is cleared when the detection signal from the resonance period detection circuit (19) disappears. (49)
indicates a first comparator that compares the count output of this ON period counter (48) with the ON period data Pcqn which is the output of the latch circuit (43) of the ON period setting means (18), and if both outputs match, When a match is found, a match signal is emitted.

(50) is a second comparator that compares the count output of the ON period counter (48) and the limit data Icp which is the output of the overcurrent protection setting circuit (20), and when both outputs match, a match signal is sent. is output.〈51) is the above first
, shows an OR gate receiving a match signal from the second comparison circuits (49) and (50), and at least one of the comparison circuits (49
) or <50>, a reset signal is given to the flip-flop circuit 22) in FIG. 3, and a stop signal is sent to the ON clock oscillator (47).

Therefore, in this ON period counting circuit (21), when the detection signal from the resonance period detection circuit (19) disappears, O
The N clock oscillator (47) starts oscillating and generates a clock signal. In addition, at this time, the above switching element (6
) can also be turned ON. At the same time, the ON period counter (48
) is cleared to the initial state and can be counted up by the clock signal from the ON clock oscillator (47). The output of this counter (48) is sequentially sent to the first and second comparison circuits (49) and (50) in accordance with the count up. The first comparison circuit (49) is connected to the counter (48)
This counter (48) output and O
The output Pcon from the N period setting means <18) is compared. The second comparator (5o) compares the output of the counter (48) with the overcurrent protection setting times & the output 1 cp from the counter (20) every time the output of the counter (48) is sent.

In the normal state, the ON period data P can is smaller than the limit data Icp, so when the contents of the ON period counter (48) match P con, the first comparator (49) passes the OR gate (51). A coincidence signal is sent to the reset terminal (R) of the flip-flop circuit (22) and the ON clock oscillator (47) in FIG. As a result, the above flip-flop circuit (22) is reset, the switching element (6) is turned off, and the heating coil (4) and resonance capacitor (5) in the inverter circuit are reset.
) starts a resonance period. The coincidence signal causes the ON clock oscillator (47> to stop oscillating. When the resonance period ends and the detection signal from the resonance period detection circuit (19) disappears, the ON period counting operation described above is repeated again.

Also, if a pot made of non-magnetic high conductivity material such as aluminum is used up as a cooking utensil, the limit data Icp will be ON.
It becomes smaller than the period data P can.

In such a case, when the output of the ON period counter (48) matches the value of the limit data Icp during the count-up process of the ON period counter (48), a match signal is falsely output from the second comparator (50). This coincidence signal is transmitted to the reset terminal (R) of the flip-flop circuit (22) via the OR gate (51) and resets the flip-flop circuit (22). That is, the limit data Icp
The ON period is limited.

FIG. 11 is a block circuit diagram of the resonance period detection circuit and overcurrent protection setting circuit, and the same parts as in FIG. 3 are given the same figure numbers. In the figure, (52) indicates the fourth humpator which is the main component of the resonant voltage detection circuit (19), and the input terminal is connected to the full-wave rectifier circuit (19).
), the power supply voltage Vcon transmitted through the choke coil (2) is divided by the dividing resistors (53) and (54) and inputted, and the switching element (6) terminal voltage V is input to the e input terminal. . is divided by a dividing resistor (55)<56) and input. (57) is a resonance clock oscillator that starts oscillation upon receiving a resonance period detection signal from the fourth converter tough 52), and <58) is a resonance period that is counted up by the clock signal from this resonance clock oscillator (57). A counter, (59) is a latch circuit that latches the count counted up by this counter (58), and (60) is the fourth comparator (60).
52) Indicates a controller that receives the output, and sends a clear signal to the resonance period counter (58) and the latch circuit (52).
9) Generates a latch timing signal to be sent to.

In such a resonance period detection circuit (19) and an overflow protection setting circuit (20), the switching element (6) is turned on.
During this period, the terminal voltage V of the switching element (6) becomes approximately zero, so the voltage at the ■ input terminal of the fourth comparator (52) is higher than the voltage at the e input terminal, and from this fourth comparator (52) The H11 level signal can be output.

While receiving this "H" level signal, the resonant clock oscillator (57) and controller (60) do not operate.

As described above, when the flip-flop circuit (22) is reset and the switching element (6> is turned off), the heating coil (4) and the resonant capacitor (5) start to resonate, and the voltage at the terminal of the switching element (6) decreases. Vc
F2 increases and a resonant waveform as shown in FIG. 2C described above is drawn.

The length of this resonance period varies depending on the material of the cooking utensil.
For example, when using a cooking utensil made of a non-magnetic and highly conductive material such as aluminum, the length is short, and when using a ferromagnetic and relatively high-resistance metal such as iron, the length is long. When the switching element (6) terminal voltage vcg becomes higher than the full-wave II current current voltage con due to the start of this resonance period, the fifth comparator (52) outputs a resonance period detection signal of "L1 level". Upon receiving this detection signal, the controller (60) clears the contents of the resonance period counter (58), and
The resonance clock oscillator (57) receives this detection signal and provides a clock signal to the cleared resonance period counter (58). The resonance period counter (58) is clocked 1/1 in response to this clock signal. When the switching element (6) terminal voltage Vcl becomes lower than the power supply voltage V con at the end of the resonance period, the II HII level signal is again generated from the fifth comparator (52).

In response, the flip-flop circuit (22) is set and the switching element (6) is turned on. At the same time, the resonant clock oscillator (57) stops oscillating and the resonance period (22) is set. The count-up is stopped and held in the γ-output counter (58) according to the resonance period.Furthermore, at the same time, the controller (60) sends a signal to the latch circuit (59). The data held in the resonance period counter (58) is ON
A latch circuit (
59) to the ON period 5] circuit (21). Incidentally, FIG. 12 shows the relationship between the resonant voltage 5', Vcz, the full-wave power supply voltage, and the detection signal.

FIG. 13 is a block diagram showing a different embodiment of the control circuit of the induction heating apparatus of the present invention, and the same parts as those in the above-mentioned drawings are given the same figure numbers. In this example, A
The peak hold circuit (61) holds the C input current, and the input data P passes through the A/D converter (62).
After being converted to AD, it is transmitted to the latch circuit (63). On the other hand, the power setting circuit (16) is composed of an analog circuit, and the output from this circuit (16) is outputted to the A/D converter (62) at a timing different from the A/D conversion timing of the peak hold voltage. ) is converted into power setting data Pref and transmitted to the latch circuit (64). That is, here, the A/D converter (62) is used in a time-division manner. In this time-division operation, the peak hold circuit (61) is connected to the A/D converter (62) at the timing of the Sample signal, and the power setting circuit (16) is connected to the A/D converter (62) at the timing of the MINT signal. 62).

Further, in this embodiment, ON period setting means (18)
receives input data P and power setting data Pref from the latch circuits (63) and (64), respectively, and generates ON period data con in the first arithmetic circuit (65), and generates the above-mentioned data in the second arithmetic circuit (66). Soft data 5oft is generated by reducing P ref by a certain constant ratio. The output selection of these data P can and 5oft is performed by the data selector (67). That is, when the in-hark oscillation starts, the data selector (67) outputs the So-th output, and after a certain period of time has elapsed from the oscillation, the data selector (67) outputs the So. Output.

FIG. 14 shows a block diagram showing still another embodiment of the control circuit of the induction heating apparatus of the present invention, and the same parts as in the above-mentioned drawings are given the same figure numbers. In this embodiment, the first input data PADI and 2 are used to start the inverter oscillation.
Difference of the second input data "AD2" PAD2 - PAD
A rising north detection circuit (68) is provided which detects PAD2 PADI and prohibits the clip float circuit (22) when this PAD2 PADI is smaller than a predetermined value. In addition, the overcurrent protection N determination circuit (20) includes a resonance period counting circuit (69) that counts the resonance period, and when the count of the resonance period counting circuit (69) becomes lower than the set value, a signal is output. In response to the contents of the resonance period counting circuit (69), the S1 number circuit contents of the counter clock 9) are normally turned on by the switching element 6).
An arithmetic circuit (71) is provided which outputs limit data Icp that limits the period and corrects the count contents of the counting circuit (69) in a direction that decreases only when a signal is given from the magnitude comparator (<70). ing. That is, when the resonance period is short, this arithmetic circuit (71) is operated by the counting circuit (6).
9) Further reduce the output content and output it as restriction data Icp. Note that a shift register is used as the arithmetic circuit (71), and when a signal is given from the magnitude comparator (70), the contents are changed from "0101°" to "0010°", for example.
If the configuration is such that the shift is performed once, such a correction can be easily made.

Effects of the Invention As described above, in the present invention, since the control circuit is composed of a digital circuit, the set ON period does not change due to temperature changes or changes in time measurement, and the switching element can be adjusted to 0.
N10FF control can be performed accurately and the I of the control circuit can be
C and miniaturization can be achieved. In addition, the resonance period of the inverter is detected for each oscillation, and the limit data ICp is set according to this period length, and the ON period length of the switching element is limited by this limit data Icp. The material of the cooking utensil used in each inverter oscillation is detected, and the length of the ON period of the switching element is limited, so that overcurrent protection can be speeded up and the switching element can be protected more reliably.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the Hertha circuit used in the present invention;
Figure 2A is a waveform diagram showing the ON and OFF signals, Figure B is a waveform diagram showing the current flowing through the switching element, Figure C is a waveform diagram showing the switching element terminal voltage, and Figure 3 is the induction heating cooking method according to the present invention. The block diagram of the control circuit of the device, Figure 4 is A/
A circuit diagram of the D conversion circuit, Fig. 5 is a circuit diagram of the timing generation circuit, Fig. 6 is a waveform diagram at each point of the timing circuit, Fig. 7 is a timing chart showing the timing of A/D conversion, and No. 8rXJ. is a block diagram of the ON period setting circuit,
FIG. 9A is a timing chart showing the operation timing of the prohibition circuit, FIG. 9B is a flowchart showing the generation state of ON period data, and FIG.
Figure 1 is a block circuit diagram of the resonance period detection circuit and overflow protection setting circuit, Figure 12 is the switching element terminal voltage,
A diagram showing the relationship between the DC power supply voltage and the detection signal of the resonant voltage detection circuit, FIG. 13 is a block diagram showing another embodiment of the control circuit of the present invention, and FIG. 14 is a still another embodiment of the control circuit of the present invention. FIG. (1)...Aftermath rectifier circuit, (2>...Choke coil, (3>...Filter capacitor, (4)...Induction heating coil, (5)...Resonance capacitor, (6)...・
Switching element, (7) Damper diode, (
8)...Drive circuit, '(11)...Current transformer, (12)...Cooking utensil, (13)...A/D conversion circuit, (14)...Timing generation circuit, ( 15)・
...Improper load detection circuit, (16>...Power setting circuit, (17)...SUB circuit, (18)...ON period setting means, (19)...Resonance period detection circuit, (20> −
Overcurrent protection setting circuit, (21)...ON period counting circuit,
(22)...Flip-flop circuit, (25)...Peak hold capacitor, <26>...FET, (3
0) (35) < 38) < 52)...Hunparator, (
31)...Successive approximation register, (32)...D/
A conversion section, (33) (43) (46) (59)...Latch circuit, (41)...Prohibition circuit, (42)...Addition circuit, (44)...Soft start setting circuit, (45
)...Selection circuit, (47)...ON clock oscillator, (48)...ON period counter, (49) (50
)... Comparator, (57)... Resonant clock oscillator, (58)... Resonance period counter, (60)...
Controller, (62)...A/D converter, (65)
<66) (71) Arithmetic circuit, (68) Rise detection circuit, (69) Resonance period counting circuit, (70>
...Big J\Comparator. Applicant: Sanyo Electric Co., Ltd. Agent Patent attorney: Shizuo Sano Practitioner Amendment (Method) June 3, 1980 Mr. Commissioner of the Japan Patent Office 2 Name of the invention Induction heating device 6. Related Patent applicant name (188) Sanyo Electric Co., Ltd. 4, Agent Address 2-18 Keihan Hondori, Moriguchi City Contact information: Telephone (Tokyo) 835-1111 Patent Center Representative Nakagawa 5, Date of amendment order (shipment date) ) May 29, 1980 6. 0 drawings to be amended. 7. Details of the amendment. Of the 0 drawings, Figure 9 will be corrected as shown in the attached sheet.

Claims (1)

[Claims] 1) A DC power source, an induction heating filter coupled to the DC power source, a resonant capacitor forming a resonant circuit together with the induction heating coil, and a switching device connected to the resonant circuit to generate a resonant current in the resonant circuit. element, a diode connected in antiparallel to this switching element,
In an induction heating device that generates an oscillating current in the resonant circuit by controlling ON and OFF of the switching element, an ON period setting for setting ON period data P can corresponding to a time when the switching element should be turned ON. means, a resonance period detection circuit that detects the resonance period of the switching element terminal voltage that resonates after the switching element is turned off, and a resonance period detection circuit that counts the resonance period length that can be detected by the resonance period detection circuit, and limits a value according to the counted value. an overcurrent protection setting circuit configured as data Icp;
An induction heating device comprising: an ON period counting circuit that starts counting at the same time as the switching element is turned ON, and provides an OFF signal to the switching element when the count reaches the ON period data P can or the limit data tcp.