JPS60173643A - Address generating device - Google Patents

Abstract

PURPOSE:To attain the generation of an address with general-purpose and high speed by providing an address operating device with high general-purpose operated by a microprogram control and an address modification function specific to signal processing. CONSTITUTION:An address operating section 100 outputs a modulo address, a row address and the 1st column address based on the input data. The column address is the address as the result of an arithmetic unit inputted with the content of a conventional register 112 and the row address or the 1st column address in addition to the 1st column address and they are controlled by a micro control circuit 1. The modle address, the row address and the 2nd column address obtained in this way are connected by an address modification section 200 and the result is extracted as an address output 270.

Description

TECHNICAL FIELD The present invention relates to an address generation device for a data memory that stores processing data of a digital signal processor (DSP).

(Technical background) In the field of digital signal processing such as sonar, the data subject to signal processing is multi-channel real-time data.
In a DSP, the structure of processing data on a data memory is generally a two-dimensional array in which each channel corresponds to a row vector. For example, there are cases where transversal filter calculations are time-divisionally processed for multiple channels as shown in FIG. 1, or beamformer calculations are performed as shown in FIG.

In signal processing operations in the digital signal processing processor DSP, such as transversal filters, beam formers, FFT (fast Fourier transform), vector inner products, etc., addresses specific to the signal processing operation are used for vectors in a two-dimensional array on the data memory. Need to read and write. That is, a modulo address for realizing a shift register function on random access memory (RAM), a butterfly operation address and a hit reverse order address for FFT operation, an indirect address with modulo that refers to a table for beamformer operation, Complex addresses, such as double precision or double addresses for complex numbers, need to be generated in a complex manner.

Conventionally, the following methods have been used to generate such addresses.

b) A method in which the arithmetic processing unit of the digital signal processing processor DSP generates addresses using a program.

(1) Each process a) A method of having a dedicated address generator in accordance with the revolution rhythm using hardware.

In case (a) above, it takes time to generate an address and is not suitable for real-time processing. Although high-speed calculation is possible in the case of
It had the drawback of lacking versatility.

(Object of the Invention) The present invention solves the above-mentioned drawbacks in generating complex addresses specific to signal processing for processing data on a data memory that is processed in the arithmetic processing unit of a digital processing processor DSP, and handles a wide range of signals. The purpose of the present invention is to provide a highly versatile address generation device that can withstand processing applications.

(Configuration of the Invention) The configuration of the present invention provides an address generation device for a data memory for storing processed data of a digital signal processing system.
means for inputting data; first shifting means for right-shifting data from said means for inputting data by O or 1 bit; and rows on at least two sides connecting the output of said first shifting means. an address register, at least two column address calculation mechanisms, a plurality of general-purpose registers, a first selection circuit that selects either the row address register or the column address calculation mechanism, and an output of the first selection circuit. and an arithmetic operation circuit that calculates outputs of the column address calculation mechanism and the arithmetic operation circuit, and a second selection circuit that selects either the column address calculation mechanism or the arithmetic operation circuit; An address characterized in that an address modification section is provided, which has means for inputting and converting the outputs of the first shift means, the row address register, and the second selection circuit, and for outputting the converted address. It is a generator.

In this way, it has a highly versatile address arithmetic unit 411 that operates under microprogram control, and an address modification mechanism that converts the address generated by the address arithmetic unit into a modulo address, a bit reverse order address, and a double word address specific to signal processing. By providing , address generation can be performed.

(Embodiment) Before explaining the embodiment, digital signal processing that requires address generation specific to signal processing operations will be explained.

b) Transversal filter The operation of the transversal filter is expressed by the following equation.

y=Σhi ” xn−i −(1) ni=O Figure 1 shows the principle of a transversal filter.
The transversal filter of formula i) has a shift register R1 attenuator as shown in FIG. p h, *fi2+...
hN+1 and an adder Σ.

In FIG. 1, when input data xn is input to the shift register R, the contents of the first location L1K, it's location L2, and the second location L2 are as follows. It is shifted to the right by 10 digits. The contents of the Nth location N are then discarded.

The tap output at each location is an attenuator hOe
)11 t h2”' hN-1 to h., hl,・
. . , weighted by a coefficient of hN-4, and added by an adder Σ, resulting in an output yn. Thereafter, a new input xn is input to the shift register R and the above operation is repeated.

The functions of the shift register R described above can be realized by using a random access memory RAM and controlling addresses.

Assuming that the number of stages of the shift register R is N, mono-row N addresses circulating from address 0 to N-1 are used. That is, input data Xn is stored at address (n)modN. Each tag output Xn-1 of the shift register R becomes the contents of the (ni) mod N address. The shift operation can still be realized by updating n by +1. However, (n)mo
dN= n+r −N −” (2) 0≦n+r−N<
N r: Integer (n) In the moaN operation, when the value of N is a power of 2 where N = 2M (M is a positive integer), the lower M bits of n are only valid, and the upper bits of the remaining bits are This can be achieved by setting the bit to 0.

Mouth) Beamformer A beamformer is a beamformer that processes signals from multiple sensors.
- Form the beam output by giving each sensor channel a unique delay and summing. Figure 2 shows a diagram of the principle of the beamformer.

Figure 2 shows the beamformer for the K channel sensor, XO,n'xl,n'...Xk-1,n
are the sensor outputs, and y is the beam output, respectively. The beam output y is obtained as the sum of the outputs of transversal filters corresponding to each sensor channel. At this time, the tap location of each transversal filter is determined by the delay amount specific to the sensor channel.

Address control for realizing the beamformer uses modulo addressing, similar to transversal filters. However, in the beamformer, shift registers Ro, R1...RK-4 corresponding to each sensor channel
Since the tap location is a value unique to the sensor channel and generally difficult to calculate by calculation, it is prepared as a table outside the address generator. Now let the sensor channel be k and the tap location Dk
Considering a shift register with input data X
krn is stored in -N+(n) mod N address, tap output xk, n-Dk is -N ten (n-Dk) mo
d The contents of address N.

c) FFT Figure 3 shows 8-point complex FFT with input bits in reverse order (N=8)
Here is an example.

In FIG. 3, input data f. -f7 is % fQ l f41f2 by a 3-bit bit-reverse order address.
* f6 t fl + f5 + f3' + f7
The bits are sorted in reverse order, and then the complex FFT is performed.
is executed and outputs F in bit-directed order. -F7 is obtained.

fo to f7 and F. −F, is complex data.

In general, in an N-point complex FFT where N=2M, an M-bit bit reverse order address, expressed as , is required for address n, expressed as .

FIG. 4 is a block diagram of an embodiment of the present invention.

Reference numeral 1 denotes a micro control circuit, which decodes and decodes a microcontroller (not shown) and controls various parts via a control line 2. 100 is an address calculation section, and 200 is an address modification section. The data human power 101 is the first shift circuit 1
Connected to 02. The output of the first shift circuit 102 is connected to a row address register 1101, a column address register 111, and a general-purpose register 112 via a data line 103, and is also supplied to an address modification section 200.

120 is the row address of the output of the row address register 110, connected to the first selection circuit 130,
It is supplied to the address modification section 200.

121 is the first column address output from the column address register 111 and is connected to the first selection circuit 130 and the second selection circuit 150. The outputs of the first selection circuit 130 and the general-purpose register 112 become the output of the arithmetic operation unit 1400. The output of the arithmetic operator 140 is connected to the second selection circuit 150 via an arithmetic unit output line 143, and is also connected to the data input 101 by a tri-state gate (not shown).
connected to. The second selection circuit i s'o output
The column address 160 of is supplied to the address modifier 200.

210 is a modulo register, address calculation unit 10
0 data line 103 is input. Modulo register 21
The output of 0 is connected to the bit reversal circuit 2, 20 and the coupling circuit 230 via the output line 21. Address arithmetic unit 1000 row address 120 becomes power of coupling circuit 2300 Å. Second column address 16 of address calculation unit ioo
0 is bi.

The third selection circuit 240 is connected to the second selection circuit 220 and the third selection circuit 240 . Third column address 2 of output of bit reversal circuit 220
The fourth column address 241 of the output of the third selection circuit 240 becomes the coupling circuit 2300A.

231 is the first address of the output of the coupling circuit 230, which becomes the input of the second shift circuit 250.

251 is the second address of the output of the second shift circuit 250, and is supplied to the address register 260. 27
0 is the address output of this device, address register 2
60.

FIG. 5 shows the details of the bit inversion circuit 220, and shows an example in which the address width is 7 bits.

In FIG. 5, M2. M4. Mo is modulo line 2
11, I6-Io are the second column addresses 160.06-O
o is the third column address 22 (l), and 2:zz is a 7-bit wide selector.

FIG. 6 is a circuit showing details of the coupling circuit 230 and the second shift circuit 250, and is an example in which the address width is 7 bits. In FIG. 6, M2 e Mt vM, ) u
-r knee) Yuo line 211, R6 to Ro is row address 12
0.06~co is the fourth column address 241, A'6~A
'o is the first address 231, A6 to Ao are the second addresses 251, CT, , CTo, D/S,
Elo is part of control line 2. 232 is a decoder,
233 is a selector.

In Figure 5, 7 bitO is entered. ~Eng. (Second column address 160) is bit-inverted and input to the selector 222. The selectors 222 are provided in three stages, and the selectors 222 in the three stages are shifted to the right by 7-M bits, resulting in outputs 06 to oo.

However, M-22, M2+21, M1+2°, and Mo.

The input/output relationship of the bit reversing circuit 220 in FIG. 5 is shown in FIG. For input, ~Io, the bits of the lower M pits are reversed for M=Q~7, resulting in outputs 06~Oo. In FIG. 7, the cross mark is prohibited in connection with the coupling circuit described later, so either 0 or 1 may be used.

- In FIG. 6, the decoder 232 detects control line 2 CT1.
CTo, M2 of modulo line 211. M4. M.

Depending on the value of , masks as shown in Figure 8! Turn P6~
Generate Po. In FIG. 8, the mark X means that it does not matter whether it is O or 1.

If CT = 1, then depending on the value of M! In 1lP6 to Po, the lower M bits are 1, and the other bits are 0. However, M=
2-M2+2-M1+2°・Mo. Also, CT1=
0, regardless of the value of M, P6 to Po are CTo
= 0, all 0. , CTo=1, all have a value of 1.

In the coupling circuit 230 of FIG. 6, the outputs P6 to Po of the decoder 232 are connected to the selector 233, and P is 0.
If P is 11 l l , then Ci is selected and becomes Ai' (i=6 to 0).

Next, in the second shift circuit 250, by the control line circuit, when cho = 00, A, =A,' (i = 6 to 0), fi, and when D/S = 1, shift to the left by 1 bit. Then, Al = Ai-1 (t 76-1) and Ao = E10.

VO is a control line and takes a value of 0 or 1.

Next, FIG. 9 shows an example of address modification in the address modification section. Figure 9 shows an example of the address width in bits, RK-1 to Ro are row addresses 12θ, CK-4 to C
o is the second column address 160, subscript M is the content of the modulo reno star 210, Elo is one of the control lines 2,
Takes a value of 0 or 1. (1) is an example in which all RK-1 to Ro are selected, (2) is an example in which all CK-4 to C8 are selected, (3) is an example of a modillo address, and (4) is an example in which bits are selected. Examples of modillo addresses with reversals, (5) to (8)
(1) to (4) are converted to 1 by the second shift circuit 250.
This is an example when bits are shifted to the left.

Next, examples of address generation according to the present invention will be shown in the principle diagrams of address generation shown in FIGS. 10 to 14, and the operation of FIG. 4 will be explained.
= FA+Δ・t (t=o, i, =) −(
5) Equation (5) is an example in which the initial address is FA, the address update width is Δ, and addresses are generated at intervals of Δ from FA. It is assumed that the address update width Δ in FIG. 10 is stored in advance in the general purpose register (GR) JJJ. The initial address FA is provided via the data manual 101.
The column address register (CAR) 111 is stored. At this time, the first shift circuit 102 is in an O-bit shift state. Thereafter, when the first selection circuit 130 selects the first column address 121, the contents of the column address register (CAR) JZI and the Δ are added to the arithmetic operator 140, and the result is The operation of storing the column address register (CAR) 777 is repeated. This results in column address register (CAR) J J J (5
) expression address is generated.

The address generated by the column address register (CAR) 111 is selected by the second selection circuit 150 as the first column address 1.
21 side is selected, the third selection circuit 240 selects the second column address 160 side, the combination circuit 230 selects all the fourth column addresses 241, and the second shift circuit 250 is set to 0.
The data is bit shifted, stored in address register 260, and output to address output 270.

mouth) Double word increment address (Figure 11) Adr=
FA-)2-Δ・i+1y'o(i=0, 1,...
- (Vo=o, 1))... (6) Equation (6) is an example of a case where two consecutive words such as double precision or complex number data are treated as a double of one word. Assuming that the initial address is FA and the double word address update width is Δ, double word addresses (two consecutive words) at 2Δ intervals are generated from FA. In FIG. 11, it is assumed that Δ is stored in advance in a general-purpose register (GR) J J ,2. The initial address FA is entered via data input 101,
It is shifted to the right by 1 bit in the first shift circuit 102, and F'
Column address register (CAR) 111 as A, /2
is stored in Thereafter, in the same manner as in item (a) above, the contents of the column address register (CAR) 11J and the above Δ are added, and the result is added to the column address register (CAR) I I
Repeat the operation of storing data in z once every two steps.

The address FA/2+Δ·i generated in the column address register (CAR) IJJ is shifted to the left by 1 bit in the second shift circuit 250, and during the two steps, it is set to 0 in the first step and 0 in the second step. The address output 27 is routed in the same manner as in item a) above, except that 1 is added to the LSB.
Output to 0.

c) Transversal filter address (Figure 12) Adr=-N-1-(n-i) modN(i=0.
1, -N'-1) - (7) k: Channel number N': Filter order N: N=2M>N' n: Reference address Equation (7) is from k-N to (k+1)・N-1 This is an example of generation of arithmetic addresses of a transpersal filter using a shift register function configured by a random access memory RAM of N words up to address.

In FIG. 12, the reference address n is stored in the general purpose register (GR) 112 in advance. The row address -N is input from the data input 101, and is stored in the row address register (RAR) 110 in a θ bit shifted state in the first shift circuit 102.

Next, the n is stored in the column address register (CAR) I11 via the arithmetic operator 140. Thereafter, the contents of the column address register (CAR) 211 are input to the arithmetic operation unit 140, and the contents of the column address register (CAR) 211 are subtracted by 1.
AR) J J Repeat the operation of storing in J.

The contents of the row address register (RAR) 110 are supplied to a combination circuit 230, the contents of the column address register (CAR) 7J1 are supplied to a second selection circuit 15.
0 selects the first column address 121 side, and the third selection circuit 240 selects the second column address 160 side, which is then supplied to the coupling circuit 230. In the coupling circuit 230, the modillo register 210 According to the modillo value M stored in advance in the mask pattern P such that only the lower M bits are 1, an AND-OR gate is used to combine the contents of the row address register (RAR) J1o and the column address register. The contents of (CAR) 711 are combined, shifted by 0 bits by the second shift circuit 250, stored in the address register 260, and outputted by the address output 270.

2) Beamformer address (Figure 13) Adr = -
N+(n Dk) mod N (k=o, 1..= -1)
・=(8) k: Channel number: Total number of channels Dk= Number of delay taps for channel N: N=2 〉Dk n: Reference address Equation (8) is expressed in the principle diagram of the beamformer shown in Figure 2. , is a generation sequence of beamformer calculation addresses when the order of the transversal filter of each channel is 1.

In FIG. 13, kN-1-N-Dk is an address table prepared externally, and is inputted from the data input 101, and the first shift circuit 102 is shifted by θ bits to the row address register (RAR). JJ.

and column address register (CAR) J J 1 at the same time.

The address table is composed of words, k=O~ to -
1-i every step the row address register (RAR)
110 and the column address register (CAR) 11.

The contents of the row address register (RAR) 11θ are as follows:
A coupling circuit 230 is provided.

The contents of the column address register (CAR)'zZZ are added to the reference address n previously stored in the general purpose register (GR) II2 by the arithmetic operator 140, and the addition result is sent to the second selection circuit. The arithmetic unit output line 143 side is selected at 150, the second column address 160 side is selected at the third selection circuit 240, and the signal is supplied to the coupling circuit 230. ° From the coupling circuit 230 to the address output 220, the same operation as in the previous section (c) is performed, and the address output 27
Output to 0.

e) Bit reverse order address (Figure 14) Adr=2kN+2[(n')modN)+E10,
・r9)n=0.1, -N-1(I10=0.
1) n': Value N shown by formulas (3) and (4)
:Number of FET points 2kN:Start address Equation (9) is an example of generating an M-bit bit reverse order address for N double words from 2.k-N to 2(k+1).N-1 address. . In FIG. 14, the row address 2·k-N is passed through the data input 101 and shifted to the right by 1 bit in the first shift circuit 102, resulting in k-N, !
: Row address register (RAR)
K is stored. Next, the initial value O generated by the arithmetic operator 140 is stored in the column address register (CAR) JJ1.

Thereafter, the contents of the column address register (CAR) 211 are added by 1 to the arithmetic operation unit 140, and the operation of storing the contents in the column address register (CAR) III once every two steps is repeated. The row address register (RA
The contents of R) 110 are provided to a combining circuit 230. The contents of the column address register (CAR) JJJ are stored in advance in the modulo register 210 by the bit reversing circuit (BRV) 220 after the second selection circuit 150 selects the first column address 12. The bits are reversed according to the modulo value M, and the third selection circuit 240 selects the third column address 221 side, and the coupling circuit 23
0. In the coupling circuit 230, the row address register (RAR) J
The contents of o and the column address register (CAR) 11
Combine the contents of 1 with the M pit reversal result. Coupling circuit 2
The value of kN+(n')modN generated at 30 is shifted to the left by 1 bit by the second shift circuit 250,
During the two steps, 075E is added to the LSB in the first step and 1 is added to the LSB in the second step, which are stored in the address register 260 and output to the address output 270.

In addition to the above examples of address generation, various types of address generation are possible. On the other hand, digital signal processing processor (DSP)
), in order to achieve parallel or online processing of data, it is necessary to generate two or more addresses that operate independently.
Column address register 111 and Himojiro register 210
This is realized by having a plurality of general-purpose registers 112, each having two sides.

(Effects of the Invention) As explained above, the present invention allows the address calculation unit to generate general-purpose addresses such as increment and decrement, and to generate complex addresses for butterfly calculations in fast Fourier transform (FFT). Yes, again, 7 pages
Since the address modification section is provided with a modulo register, a bit reversal circuit, a combination circuit, and a second shift circuit, the address generated by the address calculation section is converted into a modulo address, a bit reverse order address, and a double word address. It is possible to efficiently generate complex addresses specific to signal processing operations.

In addition, by providing two row address registers, two column address registers, and two modulo registers, and providing multiple general-purpose registers, it is possible to generate two independent addresses, and parallel processing of vector data is possible. It enables evelining. It also enables indirect addresses that refer to external tables.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of a transversal filter, the second side is a diagram of the principle of a beamformer, Figure 3 is an example of a complex FFT, Figure 4 is a block diagram showing an embodiment of the present invention □, Figure 5 shows the details of the bit reversal circuit, and Figure 6 shows the coupling circuit and the second
Details of the shift circuit, Figure 7 shows the input/output relationship of the bit inversion circuit, Figure 8 shows an example of the mask pattern of the coupling circuit, and Figure 9 shows the details of the shift circuit.
The figure shows an example of address modification by the address modification section, and FIGS. 10 to 14 are diagrams showing the principle of address generation in this device. 1... Micro control circuit, 2... Control line, 100.
...Address calculation section, 101...Data input, 102
...First shift circuit, 10°3...Data line, 1
10... Row address register, 111... Column address register, 112... General purpose register, 120...
Row address, 121...first column address, 130...
...First selection circuit, 140...Arithmetic operator, 143
...Arithmetic unit output line, 150...Second selection circuit, 1
60... Second column address, 200... Address modifier, 210... Modulo register, 211... Modulo m, 220... Bit inversion circuit, 221...
Third column address, 230...coupling circuit, 231...
・First address, 240...Third selection circuit, 24
1... Fourth column address, 250... Second shift circuit, 251... Second address, 260... Address register, 27°... Address output, 222...
- Selector, 232... Decoder, 233... Selector. Figure 1 Figure 2 Figure 3 Figure 4 Figure 7 Figure 9 (81K-2RK-3---RM co -M-2CN
) IF7 ('Fig. 10 p8 Fig. 11 A FA, 2・Δke E10 Fig. 12 kN+(n-i) mod N Fig. 13 shows N+(n-ok) mod N Fig. 14 kN 2kN+2[(n '1modNl10E10 Procedural Amendment (
(Spontaneous) ■, Indication of the case 1982 Patent Application No. 028564 2, Invention name address generator 3 Relationship with the person making the amendment Patent applicant's office (105) 1-7 Toranomon, Minato-ku, Tokyo Number 12
No. 4 Agent address (105) 1-7-12 Toranomon, Minato-ku, Tokyo
No. 6, Contents of amendment (1) The phrase "digital processing" in the fifth line of page 5 of the specification is amended to read "digital signal processing." (2) In the 16th line of the same page, the phrase "first shifting means" is corrected to "first shifting means." (3) In the 5th line of page 23 of the same book, "rN: FET score" is corrected to "rN: FFT score." (4) On page 26, line 8 of the same book, the phrase "second page" is amended to read "Figure 2." (5) The drawings “Figure 1,” “Figure 10,” and “Figure 11” will be corrected as shown in the attached sheet. Figure 1

Claims (2)

[Claims] (1) In an address generation device for a data memory for storing processed data of a digital signal processor, means for inputting data, and first shifting means for right shifting the data input from the means for inputting data by 0 or 1 bit. and at least two row address registers, at least two column address registers, and a plurality of general-purpose registers, to which the output of the first shifting means is connected, and one of the row address register and the column address register. a first selection circuit for selecting, an arithmetic operation circuit for calculating an output of the first selection circuit and an output of the general-purpose register, and a second selection circuit for selecting either one of the column address register and the arithmetic operation circuit. an address calculation unit having a selection circuit; an address calculation unit that converts an address by inputting the respective outputs of the first shift means, the row address register, and the second selection circuit of the address calculation unit, and outputs the converted address; 1. An address generation device comprising an address modification section having means for modifying an address. (2) As the address modification part, the first part of the address calculation part
If the contents of the modulo register are an integer M, the lower M bits of the second selection circuit of the address calculation section are a bit reversing circuit for reversing bit positions; and a third selecting circuit for selecting either one of the output of the bit reversing circuit and the output of the second selection circuit.
and the third selection circuit with the lower M bits of the output of the row address register of the address calculation section being valid and the lower M bits of the output of the row address register of the address calculation section being invalid;
a coupling circuit that selects either the output of the second selection circuit via the third selection circuit or the output of the row address register regardless of the value of t-;
a second shift means that shifts left by o or 1 bit and adds a signal of O or 1 to the least significant bit when shifted left by 1 bit; and an address renostar that temporarily stores and holds the result of the second shift means. 2. The address generating device according to claim 1, further comprising means for outputting the output of said address renostar.