JPS60186035A - Forming method of impurity region - Google Patents

Abstract

PURPOSE:To reliably separate and partition an impurity region by separating grooves without complicating manufacturing steps with respect to a forming method for the impurity region provided on the surface of a semiconductor substrate. CONSTITUTION:The first resist pattern 5 of a desired impurity region shape is formed on a substrate 1 which includes an insulating film, with the resist as a mask the film 4 is sidewisely etched and removed by isotropically etching, with the resist as a mask an impurity is implanted to provide an impurity region 6, the first resist is then removed, the inverting pattern of the first resist is then formed of the second resist 7, with the remaining insulating film and the second resist 7 as masks the surface of the substrate is etched, a groove 8 surrounding the region 6 is formed, polycrystalline silicon 11 is filled in the groove 8, and the fourth SiO2 film 12 is formed on the polycrystalline silicon 11 by thermal oxidation to coat the upper surface of the groove 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for forming an impurity region on the surface of a semiconductor substrate.

(2) Prior art In recent years, in semiconductor devices, semiconductor integrated circuits have been fabricated by providing a large number of impurity regions on a semiconductor substrate in which semiconductor elements are to be formed, and forming semiconductor elements such as transistors and diodes in each of these impurity regions. It consists of In order to improve the degree of integration of semiconductor devices, a method has been adopted in which separation trenches of a desired shape are provided on the surface of the substrate, as shown in FIG. There is.

However, in the structure in which grooves are provided in this manner, mask alignment for forming the impurity region and mask alignment for forming the groove must be performed, which has the disadvantage of complicating the manufacturing process.

c) Purpose of the invention The present invention has been made in view of the above points, and
1. 2) Structure of the Invention The present invention aims to reliably isolate impurity regions using isolation trenches without complicating the manufacturing process. A resist pattern No. 1 is formed, and the insulating film is removed by isotropic etching using this resist as a mask so as to cause side etching. Then, using the resist as a mask, impurities are implanted to form an impurity region.
After removing the resist, an inverted pattern of the first resist is formed with a second resist, and the substrate surface is etched using the remaining insulating film and the second resist as a mask to form a groove surrounding the impurity region. After the formation, annealing is performed.

E) Embodiment FIGS. 1 to 8 are cross-sectional views showing the method of forming an impurity region according to the present invention in the order of steps, and the invention of the cap will be explained in detail using these drawings.

First, a first SIO film (2) of several 100X thickness is formed on a -conductivity type, for example, N type silicon semiconductor substrate (1), and a film (2) of several 1[]0
^thick 5iIN4 film (3), 5000^ thick second s
io.

After sequentially laminating the films (4), a first resist (5) having a desired shape is formed on the second slo, the substrate (1) containing the films (4) (FIG. 1). Subsequently, using the first resist (5) as a mask, the second resist film (4) is isotropically etched with a hydrofluoric acid etchant. At this time, the etching time is set to twice the normal time, and side etching of one voice is performed as shown in FIG. Furthermore, using the remaining second Si film (4) as a mask, Si
, after etching the N4 film (3) by plasma etching using, for example, CF or gas, the first resist (5) is etched.
) as a mask, add a P-type impurity such as boron to 100K.
The impurity region (6) is implanted into the substrate surface (1) with an acceleration voltage of ey and a dose of 5×10−2 to form an impurity region (6) with a peak depth of implantation concentration of 3000λ (FIG. 5). Then the first
This first resist (5) is removed.
A second resist (7) is provided according to the inversion pattern of (FIG. 4). At this time, the 26th resist (7) can be formed with a positioning margin of about 1/11 by making it about 2 tones smaller than the inverted pattern of the first resist (5). After that, the first 5tQ is etched using, for example, CH8 gas or active ion etching.
The t-film 12) is etched (FIG. 5). At this time, the second SIO film (4) is also etched, but the second SIO film (4) is also etched.
Since the iOt film (4) is sufficiently thicker than the first film (2), the second 8i0. Not all of the film (4) is etched away. Furthermore, using the second resist (7) and the second 8 IO film (4) as a mask, vertical etching is performed using CCI, gas, or active ion etching to a depth of 2 to surround the impurity region (6). Form a separation groove (8) for voice ~ 3fi, and
) At the bottom, acceleration voltage 1' 00 Kev, dose amount lX1
Phosphorus is implanted under the condition of 0" to form an N-type region for junction isolation (
9) (Figure 6). Next, the second resist (7), the first and second sto, the film +21+41 and the Si
,N.

The film (3) is removed and a new substrate (1) containing the groove (8) is formed.
) After forming a fifth StO film with a thickness of about 50A on the surface, annealing is performed at 1100° C. for 10 hours to stabilize the crystal in the impurity region (6) (FIG. 7). At this time, diffusion of impurities in the lateral direction is prevented by the grooves (8). Thereafter, this groove (8) is filled with polycrystalline silicon aυ, and a fourth
A Stow film az is generated to cover the upper surface of the groove (8) (8th
figure).

f) Effects of the Invention As described above, the method for forming an impurity region of the present invention involves over-etching this insulating film when opening an insulating film on a substrate for impurity implantation. Since the structure is used as a mask on the outer periphery for etching grooves that separate and partition the grooves, it is only necessary to form a mask that covers the impurity region as a mask for etching the grooves. A positioning margin can be taken, and the mask positioning work becomes easy.

Furthermore, since annealing is performed to stabilize the crystal of the impurity region after the groove is formed, there is no habit of impurities diffusing in the lateral direction, and the impurity region can be separated more reliably.

[Brief explanation of drawings]

1 to 8 are cross-sectional views showing the method of forming an impurity region according to the present invention in the order of steps. (1)...Semiconductor substrate, j2) (4) QlllltJ
21...5io2 membrane, (3)...S+3N4 membrane, +
51 (71...resist, (6)...impurity region, (8)...groove. Applicant Yoyo Denki Co., Ltd. Patent Attorney Shizuo Tosano

Claims (1)

[Claims] 1) When forming an impurity region on the surface of a semiconductor substrate, an insulating film is provided on the semiconductor substrate, a pattern with a desired impurity region shape is formed on the substrate including this insulating film using a first resist, and After removing the insulating film by isotropic etching using the resist as a mask so as to cause side etching, impurities are implanted using the first resist as a mask to form an impurity region. By forming an inverted pattern with a second resist, only the substrate surface under the side-etched insulating film is exposed, and vertical etching is performed using the remaining insulating film and the second resist as a mask. A method of forming an impurity region by etching the exposed surface of the substrate to form a groove surrounding the impurity region, performing annealing, and then burying the groove to serve as an isolation region.