JPS60186723U - Frequency divider circuit - Google Patents
Frequency divider circuitInfo
- Publication number
- JPS60186723U JPS60186723U JP7300984U JP7300984U JPS60186723U JP S60186723 U JPS60186723 U JP S60186723U JP 7300984 U JP7300984 U JP 7300984U JP 7300984 U JP7300984 U JP 7300984U JP S60186723 U JPS60186723 U JP S60186723U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- pulse
- divider circuit
- frequency divider
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の分周回路の回路図、第２図ａ〜ｆはその
動作を説明するタイミングチャート、第３図はこの考案
による分周回路の回路図、第４図ａ〜ｇはその動作を説
明するタイミングチャート、第５図はこの考案による分
周回路をクロ゛ング回路に適用したコンピュータのブロ
ック図である。
１１．１２・・・フリップ・フロップ、１３，１．４・
・・オアゲート、２１・・・ＣＰＵ、２２・・・コプロ
セッサ、２３・・・バス、２４・・・インターフェース
、２５・・・水晶発振器、２６・・・切替スイッチ。
６Figure 1 is a circuit diagram of a conventional frequency divider circuit, Figures 2 a to f are timing charts explaining its operation, Figure 3 is a circuit diagram of a frequency divider circuit according to this invention, and Figures 4 a to g are its timing charts. A timing chart for explaining the operation, and FIG. 5 is a block diagram of a computer in which the frequency dividing circuit according to this invention is applied to a clocking circuit. 11.12...Flip-flop, 13,1.4.
...OR gate, 21...CPU, 22...coprocessor, 23...bus, 24...interface, 25...crystal oscillator, 26...changeover switch. 6
Claims (2)
同期した、周波数１７２ｆの出力パルスを発生するフリ
ップ・フロップを備えた分周回路において、前記入力パ
ルスの前縁または後縁の他方に同期したトリガパルスを
発生する手段を備え、このトリガパルスを前記フリップ
・フロップのクリア端子またはプリセット端子に与える
ことにより、前記フリップ・フロップから、前記入力パ
ルスの周波数、ｆと同一の周波数を有する出力パルスを
得ることを可能にした分周回路。(1) In a frequency divider circuit equipped with a flip-flop that generates an output pulse with a frequency of 172f that is synchronized with one of the leading edge or the trailing edge of an input pulse with a frequency f, the other of the leading edge or the trailing edge of the input pulse means for generating a trigger pulse synchronized with f, and by applying this trigger pulse to a clear terminal or a preset terminal of the flip-flop, the flip-flop has a frequency equal to the frequency of the input pulse, f. A frequency divider circuit that makes it possible to obtain output pulses.
ップの補出力端子からの出力パルスと周波数ｆの入力パ
ルスとが入力されるオアゲートを―えていることを特徴
とする実用新案登録請求の範囲第”１項記載の分周回路
。(2) The means for generating the trigger pulse comprises an OR gate into which the output pulse from the auxiliary output terminal of the flip-flop and the input pulse of frequency f are input. “The frequency divider circuit described in item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7300984U JPS60186723U (en) | 1984-05-18 | 1984-05-18 | Frequency divider circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7300984U JPS60186723U (en) | 1984-05-18 | 1984-05-18 | Frequency divider circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60186723U true JPS60186723U (en) | 1985-12-11 |
Family
ID=30611962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7300984U Pending JPS60186723U (en) | 1984-05-18 | 1984-05-18 | Frequency divider circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60186723U (en) |
-
1984
- 1984-05-18 JP JP7300984U patent/JPS60186723U/en active Pending
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