JPS601967B2 - capacitance circuit - Google Patents
capacitance circuitInfo
- Publication number
- JPS601967B2 JPS601967B2 JP52009229A JP922977A JPS601967B2 JP S601967 B2 JPS601967 B2 JP S601967B2 JP 52009229 A JP52009229 A JP 52009229A JP 922977 A JP922977 A JP 922977A JP S601967 B2 JPS601967 B2 JP S601967B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitance
- circuit
- input terminal
- resistor
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/46—One-port networks
- H03H11/48—One-port networks simulating reactances
- H03H11/481—Simulating capacitances
Landscapes
- Networks Using Active Elements (AREA)
Description
【発明の詳細な説明】
本発明は簡単な回路により実現されるキャパシタンス回
路に関し、特に接地型キヤパシタンス回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitance circuit realized by a simple circuit, and in particular to a grounded capacitance circuit.
近年集積回路による演算増幅器(オベアンプ)を用いた
回路が種々提案され実用に供されている。In recent years, various circuits using integrated circuit operational amplifiers (obeamps) have been proposed and put into practical use.
この種の回路のひとつにオベアンプを利用して実現され
るィンダクタンス及びキャパシタンスがある。このうち
インダクタンス回路については本出願人により既に特関
昭53−63947が提案されており、従って本発明は
キヤパシタンス回路に関する。第1図Aは従来の技術に
よるキャパシタンス回路、第1図Bはその等価回路をし
めし、OPはオベアンプ、R,,R2,R3は抵抗、C
,はキヤパシタンスであり、この回路の合成容量Co及
び直列抵抗分RSの値は次のごとく与えられる。One such type of circuit is the inductance and capacitance implemented using an OBE amplifier. Among these, an inductance circuit has already been proposed by the present applicant in Japanese Patent Application No. 53-63947, and therefore the present invention relates to a capacitance circuit. Figure 1A shows a conventional capacitance circuit, and Figure 1B shows its equivalent circuit, where OP is an obeamp, R, , R2, and R3 are resistors, and C
, is the capacitance, and the values of the combined capacitance Co and the series resistance RS of this circuit are given as follows.
C。C.
=登害‐CI, RS;R3従って第1図のキャパシタ
ンス回路では本質的に直列抵抗分RSがふくまれ、RS
の値を0にすることは原理的に不可能である。= Climb - CI, RS; R3 Therefore, the capacitance circuit in Figure 1 essentially includes a series resistance RS, and RS
It is impossible in principle to set the value to 0.
一方通常の回路設計においては、キャパシタンスは一般
に無損失として扱われているので、直列抵抗分が存在す
るということは実用上大きな欠点である。従って本発明
は従釆の技術の上記欠点を改善するもので、無損失の直
列抵抗分をふくまないキヤパシタンス回路を提供するこ
とを目的とする。On the other hand, in normal circuit design, capacitance is generally treated as lossless, so the presence of a series resistance component is a major drawback in practice. SUMMARY OF THE INVENTION The present invention therefore aims to improve the above-mentioned drawbacks of the prior art and provides a capacitance circuit that does not include a lossless series resistance component.
この目的は、1個のオベアンプと3個の抵抗及び2個の
キャパシタンスから成る騒く簡単な回路により実現され
る。第2図Aは本発明によるキヤパシタンス回路の回路
図、第2図Bはその等価回路をしめす。This purpose is achieved by a simple circuit consisting of one amplifier, three resistors and two capacitors. FIG. 2A shows a circuit diagram of a capacitance circuit according to the present invention, and FIG. 2B shows its equivalent circuit.
第2図Aにおいて参照番号1はオベアンブで、負入力端
子la、正入力端子lb及び出力端子lcを有する。負
入力端子laと出力端子lcの間には第1抵抗2(アド
ミッタンスy2)、が接続され、正入力端子lbと出力
端子lcの間には第1キャパシタンス5(アドミッタン
スY5)が接続される。又正入力端子lbと接地点の間
には第2キャパシタンス6(アドミッタンスY6)が接
続され、負入力端子laと正入力端子lbの間には第2
抵抗3(アドミッタンスY3)と第3抵抗4(アドミッ
タンスY4)による直列回路が続たれる。該直列回路の
結合点7と接地点8との間に合成キャパシタンスCoが
得られる。第2図Aの回路の入力アドミッタンスYin
‘ま次式により与えられる。Yin= Y2Y6(Y
4十Y3)
−Y3Y5十Y4Y2十Y2Y6
ここでY3Y5=Y2Y6とすると、上記式は次のよう
になる。In FIG. 2A, reference number 1 is an obeamp, which has a negative input terminal la, a positive input terminal lb, and an output terminal lc. A first resistor 2 (admittance y2) is connected between the negative input terminal la and the output terminal lc, and a first capacitance 5 (admittance Y5) is connected between the positive input terminal lb and the output terminal lc. Further, a second capacitance 6 (admittance Y6) is connected between the positive input terminal lb and the ground point, and a second capacitance 6 (admittance Y6) is connected between the negative input terminal la and the positive input terminal lb.
A series circuit including a resistor 3 (admittance Y3) and a third resistor 4 (admittance Y4) is continued. A composite capacitance Co is obtained between the connection point 7 and the ground point 8 of the series circuit. Input admittance Yin of the circuit of Fig. 2A
'Given by the following equation. Yin=Y2Y6(Y
40Y3) -Y3Y50Y4Y20Y2Y6 Here, if Y3Y5=Y2Y6, the above equation becomes as follows.
Yin=Y6(1十字)
更にY2=Y3,Y5=Y6=sCとおくと(但しsは
iの)Yin!SC(1十申)
となり、第2図B‘こしめす等価回路となる。Yin=Y6 (1 cross) Furthermore, if we set Y2=Y3, Y5=Y6=sC (where s is i), then Yin! SC (10 min), which is the equivalent circuit shown in Figure 2 B'.
ここでキャパシタンスの値を可変とするには抵抗3又は
4のいずれか一方を可変抵抗とすればよい。以上の解析
から明らかなごと〈、本発明によるキャパシタンス回路
は直列抵抗分を全く含まず、無限大のQが得られる。以
上実施例により説明したごとく、本発明によれば、簡単
な回路により、直列抵抗分のないキャパシタンス回路が
得られる。Here, in order to make the capacitance value variable, either one of the resistors 3 and 4 may be made a variable resistor. As is clear from the above analysis, the capacitance circuit according to the present invention does not include any series resistance and can obtain an infinite Q. As explained above using the embodiments, according to the present invention, a capacitance circuit without series resistance can be obtained with a simple circuit.
第1図Aは従来の技術によるキャパシタンス回路、第1
図Bは第1図Aの等価回路、第2図Aは本発明によるキ
ャパシタンス回路、第2図Bは第2図Aの等価回路であ
る。
1;オベアンプ、2,3,4;抵抗、5,6;キヤパシ
タンス。
叢ノ図
第2図Figure 1A shows a capacitance circuit according to the prior art;
FIG. 2B is an equivalent circuit of FIG. 1A, FIG. 2A is a capacitance circuit according to the present invention, and FIG. 2B is an equivalent circuit of FIG. 2A. 1; obeamp; 2, 3, 4; resistance; 5, 6; capacitance. Fig. 2
Claims (1)
ンプの出力の間に接続される第1抵抗と、該オペアンプ
の正入力端子とオペアンプの出力の間に接続される第1
キヤパシタンスと、該正入力端子と接地点の間に接続さ
れる第2キヤパシタンスと、前記負入力端子と正入力端
子の間に接続される第2抵抗と第3抵抗による直列回路
とを有し、前記第1抵抗と第2キヤパシタンスとの積が
第2抵抗と第1キヤパシタンスとの積にほゞ等しく、該
直列回路の結合点と接地点との間にキヤパシタンスを提
供することを特徴とするキヤパシタンス回路。 2 前記第1キヤパシタンスと第2キヤパシタンスが等
しいことを特徴とする特許請求の範囲第1項のキヤパシ
タンス回路。[Claims] 1. An operational amplifier, a first resistor connected between the negative input terminal of the operational amplifier and the output of the operational amplifier, and a first resistor connected between the positive input terminal of the operational amplifier and the output of the operational amplifier.
a series circuit including a capacitance, a second capacitance connected between the positive input terminal and a ground point, and a second resistor and a third resistor connected between the negative input terminal and the positive input terminal, A capacitance characterized in that the product of the first resistor and the second capacitance is approximately equal to the product of the second resistor and the first capacitance, providing a capacitance between a connection point of the series circuit and a ground point. circuit. 2. The capacitance circuit according to claim 1, wherein the first capacitance and the second capacitance are equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52009229A JPS601967B2 (en) | 1977-02-01 | 1977-02-01 | capacitance circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52009229A JPS601967B2 (en) | 1977-02-01 | 1977-02-01 | capacitance circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5395553A JPS5395553A (en) | 1978-08-21 |
| JPS601967B2 true JPS601967B2 (en) | 1985-01-18 |
Family
ID=11714567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52009229A Expired JPS601967B2 (en) | 1977-02-01 | 1977-02-01 | capacitance circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601967B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5883813U (en) * | 1981-11-30 | 1983-06-07 | 日本電気ホームエレクトロニクス株式会社 | Variable capacitance modulation circuit |
| FR2595527B1 (en) * | 1986-03-04 | 1988-05-13 | Cit Alcatel | CAPACITY MULTIPLIER CIRCUIT, ESPECIALLY FOR ELECTRONIC TRUNK |
| JP2653474B2 (en) * | 1988-06-15 | 1997-09-17 | 株式会社東芝 | Active filter circuit |
-
1977
- 1977-02-01 JP JP52009229A patent/JPS601967B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5395553A (en) | 1978-08-21 |
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