JPS60200773A - Controller for inverter - Google Patents

Abstract

PURPOSE:To obtain a controlled suppressed in the capacity of a memory cell to the minimum limit by separately storing the combination state of ON and OFF of switching elements and the maintaining time of the combination state, and obtaining a PWM output in combination with both. CONSTITUTION:The first memory 10 in which the combination states of the ON and OFF of switching elements are stored and the second memory 11 in which the maintaining time of the combination states is stored are provided in a controller of a 3-phase bridge circuit using a plurality of swtiching elements. The sequence of the combination obtained continuously for a sinusoidal wave and the maintaining time are read out from the both memories 10, 11 in response to the frequency set by a frequency setter 8, and continued PWM outputs X, Y,... are output to the swtiching elements by a timer 13 and a controller 14.

Description

Detailed Description of the Invention (a) Field of Application The present invention relates to ON-OFF control of a plurality of switching elements constituting a three-phase bridge. This is done once based on the combination state of and this maintenance time.

(b) Prior art In general, conventional inverter devices configure multiple switching elements (for example, transistors, SIRIS, etc.) in a bridge shape, and control the ON/OFF states of these switching elements to convert DC into single-phase or three-phase. It was converted to output.

The 0N-OFF signal for one cycle of this switching element was stored in a storage element, and the 0N-OFF signal of the switching element was read out sequentially to control the 0N-OFF of the switching element. To explain, Figure 1 shows six switching transistors (2) connected to a DC power supply (1).
) to (7) are connected in a bridge shape and the terminal (LJ), ■,
FIG. 2 is a diagram of an inverter circuit that allows three-phase output to be obtained from W. Transistors (2) to (powers are respectively base terminals (X), (Y), (Z), (2), (Y), (Z)
ON (energized state) when H level voltage is applied.
This is the result. Figure 2 shows the distance between the terminals, (Y), (Z),
■, ω, (This is an address map showing the state of H level voltage applied to terminal (3). For example, H level voltage applied to terminal (3)
Although only the state of the level signal is described based on the PWM method, the H level signals applied to other terminals are omitted because they are similar. 1-10Hz between addresses 0-5110
Signals used for each frequency band are stored, and signals used for 11 to 20t (zK) are stored at addresses 512 to 1023. Similarly, signals used for each frequency band are stored.

This is tailored to the drive characteristics of the load connected to terminal (2), W, and if the drive characteristics of the load are constant, only the signal for one frequency band can be stored. It's a good thing. For example, if an output of 1 to 10 Hz is required from terminals (Y, (T), W), specify addresses from 0 to 511 in sequence and connect transistors (2) to (
Force terminal prisoner, (Y), (Zl, (2), (to), (obtained a control signal to the force. In this case, addresses 0 to 511 constitute one cycle, so the clock specifying the address It is necessary to set the cycle appropriately.

In this way, the switching signal for the transistor (2) or (force) was stored in the storage element for one period. Therefore, in order to store one period of the signal for each frequency, a large amount of storage element capacity is required. Furthermore, in order to increase the resolution of the output signal, it was necessary to further increase the capacity of the storage element.

In order to solve the above problems, Japanese Unexamined Patent Publication No. 57-46
Four methods have been considered as described in Publication No. 677.

According to this method, if the negative part of the three-phase alternating current as shown in Fig. 3 (al) is inverted using a phase inverter etc.
There will be only positive waveforms like b). If the waveform of FIG. 3(b) is divided by 60 electrical angles into 1st, 2nd, 2nd, etc., the waveforms will be exactly the same, although there are differences in the U, 2, and W phases. These waveforms are symmetrical even in the middle of each section, that is, at the position shown by the dashed line.

When these waveforms are shifted by 30 and superimposed, six characteristics Do, D+, D2, Ds, D as shown in Fig. 3(C) are obtained.
4.

D. becomes. Conversely, this can be seen in Figure 3 (by appropriately combining the characteristics of cl, an ideal AC waveform can be obtained. In other words, to obtain the U phase, if the Ds characteristics are selected in sequence from 0 to 30, the A half-wave sine wave can be extracted continuously.Next, to obtain a negative waveform from 180° to 360°, the phase of the waveform selected using the above method can be shifted to make a complete sine wave. This sine wave can be returned to an ideal three-phase alternating current by shifting the phase by 1200, that is, by arbitrarily selecting the above characteristics.

Therefore, a three-phase sine wave can be represented by six characteristics selected within an angle of 0 to 30' as described above. This means that if these characteristics were memorized, they could be used as one signal on the three-phase side, but when such a method is used, the utilization rate of the memory element may be reduced to a certain extent. It could be improved, but it was still not enough. That is, since 1) is stored at the - of a three-phase sine wave, there is a limit to the reduction in the capacity of the storage element due to the conflict with the resolution.

(c) Object of the Invention In view of the above problems, the present invention provides an inverter control device in which the capacity of a memory element is minimized.

B) Structure of the Invention The inverter control device of the present invention includes a three-phase bridge section configured using a plurality of switching elements, a first storage section that stores the ON-OFF combination state of the switching elements, and a first storage section that stores the ON-OFF combination state of the switching elements. ' A second storage unit that stores the maintenance time for maintaining the combination state of F, and the 011-OFF
Continuous PW by combining the combination state and this maintenance time
Since it includes a control section that outputs the M output to the switching element, it is possible to suppress the amount of storage elements used.

(E) Embodiment Below, embodiments of the present invention will be explained based on FIGS. 4 to 12. First, FIG. 4 shows a PWM control signal applied to the same inverter circuit as shown in FIG. 1. This is an explanatory diagram of the failure, and (c) in the diagram shows carrier waves, (Ml), (M2),
(M3) is a variable wave whose phase is shifted by 12o, and (
There is a relationship of carrier wave frequency)/(modulated wave frequency)=(odd multiple of 3).

(XO) is the switching signal of the transistor (2) obtained by comparing the carrier wave (cl) and the modulated wave (Ml), and (yo) is the switching signal of the transistor (2) obtained by comparing the carrier wave (c) and the modulated wave (M2). The switching signal of transistor (3) obtained by (2o) is the carrier wave (c) and modulation v(
The switching signal of transistor (4) obtained by comparing M3) with transistor (5)
, (6), (force switching signal (also), (YO)
, (ZO) are switching signals (XO), (yo), (
20) are respectively inverted, so the explanation will be omitted.

As can be seen from this figure, the three-phase alternating current shown in Fig. 4 has components (modulated waves (M, ), (M,
2), a part of (M3)) is appropriately synthesized to give 0 to 360
It forms a three-phase alternating current.

Therefore, carrier wave (cl) and modulating wave (Ml), (M2), (M
3), the switching signal (XO
), (YO), and (ZO).

Switching signals in the 0 to 30 section (XO), (yo),
The signal waveforms of (20) are (X, ), (y+), (z
+), the signal waveform in the 30-60 interval (X2), (
Y2) and (Z2) correspond to the waveform obtained by reading the signal waveform (Z+) backwards, the waveform reading the signal waveform (Y, ) w backwards, and the waveform reading the signal waveform (Xl) backwards, respectively. Hereinafter, by converting the signal waveforms (Xl), (Y, ), (Z,) by reading them backwards, inverting them, etc., one cycle of switching signals (0 to 36o) ( Xo), (yo), (, Z.) can be obtained.

Next, Figure 5 shows (frequency of carrier wave)/(frequency of modulated wave)
It is an enlarged view of the 00-30 section when =27. Components in the figure that are the same as those in FIG. 4 are designated by the same reference numerals, and explanations thereof will be omitted. As shown in figure wJ5, the signal waveforms (Xl), (Y, ),
If the periods in which the states of (Z, ) change are respectively (T1) to (TI2), then the transistors (2) to (7)
The ON-OFF state of is as shown in FIG. Incidentally, the interval (TI2) in FIG. 5 always takes a small amount of time even when the voltage ratio between the carrier wave and the modulated wave is changed. 9-C Yu, X). Since the time period in the range from 0.degree. This section (To), (T2), (T6), (T,
) in transistor (2) to (power 0N-OFF
The combination states of are the same, and the intervals ('r+), (T
7), (Tit) is also connected to transistor (2) or (force 0N).
The combination of -OFF is also the same, and similarly the interval (T, ),
(T, ), (T9), ('rn), interval (T4), (T
+o) is also the same. Therefore, it is configured in four types of combinations as described above.

In this way, from transistor (2) to (power 0N-OFF)
The number of combinations of states is limited to a predetermined number.

Therefore, the possible 0N of transistors (2) to (7) is
The combination state of -OFF (ON is 1 and OFF is φ) is shown in FIG. In this figure, state (φ
) to (power are the basic combination states of transistors (2) to (7). Furthermore, transistors (5), (6),
The 0N-OFF state of (7) is the transistor (2), (3
), (4) are assumed to be in the inverted state of the ON-OFF state. Furthermore, states (8) to (c) indicate dead time states. For example, the section ('ro) in Figure 6 → (
When switching to T1), the combination state of the transistors is switched from state (φ) in FIG. 7 to state (6). Specifically, the transistor (4) changes from ON to OFF, and the transistor (power changes from OFF to ON.) At this time, if there is no dead time condition, the transistor (4), ( 7) may be in a simultaneous KON state, causing a short circuit in the inverter circuit and damaging the transistor (4). This is based on the switching characteristics of transistors (4) and →OF
This is due to the time delay when transitioning to the F state. Therefore, when switching from state (01) to state (6), put-time state (8) is used to switch from state (0+→put-time state (8).
)→state (6), transistor (4), (there will be no short-circuit of power and this problem will be solved. (section 0 in Figure 8)
60) If the switching characteristics of the transistors (2) to (7) are improved by adding a discharge circuit or the like, such a dead time state will become unnecessary.

Such a condition (of force and put-time status)
If you combine 8) to (25), you will get 0N-OF for one period.
F combination states can be obtained. ON-0 of transistors (2) to (7) for one period obtained in this way
FIG. 8 shows the combination of FFs. This figure shows 60 sections divided into 12 sections of 30 sections each as shown in FIG. 6, that is, the 60 sections are divided into 24 sections. Note that the section (end) is a get time state.

Figure 9 shows each section (・,・) to (24) shown in Figure 8.
maintenance time (put-time state (approximately several tens of microseconds)
). In addition, the fourth
As can be seen from Fig. 5, the output waveform for one period is 0.
It can be represented by a waveform of 30 intervals, and the 0 to 60 interval, which is doubled, has a symmetrical maintenance time for each interval with 30 as the boundary. In other words, if the interval (...) to 02) is reversely arranged with the interval α2 to (11), the interval (I3) to (
7! City can be obtained. Therefore, if the maintenance time of each interval of θ to 30 is determined, the maintenance time of each interval for one cycle is also determined. In addition, in Figure 9, the output frequency is 20 to 12.
It is separately described in 41iz@ up to 0Hz. this is,
Since the time of one cycle, that is, the frequency, is determined by the sum of the sustaining times, it is necessary to set the sustaining time for each frequency.

Therefore, transistors (2) to (2) as shown in FIG.
If the 0N-OFF combination state of 7) is stored in the first storage section and the maintenance time as shown in FIG. 9 is stored in the second storage section, this ON-OFF combination state and this maintenance time can be stored. By reading out the transistors (2) to (7)
) can control the ON-OFF state.

For example, to obtain an output with a frequency of 20) Jz, the 10th
To explain based on the figure, first, in the interval (To), the transistor (2
) to (7) on the basis of the ON-OFF combination states and FIG. 9, the maintenance time of section (0) is read out and set in a separately provided timer. Therefore, this state is maintained until this timer times out. Furthermore, this section (
The predetermined time at the end of 0) becomes a put-time state, and the transistor (2) to (0N-OF of power
This prevents damage to the transistors (2) to (7) when the F state is switched. Next, when the timer time-amps,
Section (transistor (2) in IIK to (force 0N)
- Read out the OFF state and maintenance time from the first and second storage units, and read the OFF state and maintenance time from the first and second storage units, and
This controls the F state. A continuous switching signal can be obtained by sequentially reading out the ON-OFF state and sustaining time of the transistor (2) to (ON-OFF) each time the following sections are switched.

The operation of the control section when the control section that executes the above operations and the first and second storage sections are housed inside a microprocessor will be explained based on the flowchart shown in FIG. is the set frequency given externally, (1) is the remaining time of the built-in timer, (
C1 is the setting value of the interval, (θ) is °“θ≦θ〈θ+60″
It is an electrical angle section showing θ=0 is O≦θ<60, θ=
60 is 601θ<120,...θ=300 is 3
00≦θ≦360. Also, the initial setting of the remaining time (1) is ' = f + (F'' from Figure 9).
, C), and the transistor (2) to (force 0N)
-OFF state box From Figures 7 and 8, p”A (θ, C)
It is determined by

When operation is started by turning on the power, etc., after initializing and initializing variables, read the setting frequency (month) set in the external setting section, then set the maintenance time, that is, the timer setting time (1), and start the timer. Next, set the transistors (2) to (7) to the ON-0FF state (e) and output to the transistor (2) to (power) to determine the ON-OFF state of the transistor (2) to (power). Time,
When changing to the next interval, that is, the interval (q is the interval (C+1)
Note the required put-time state output (P) when . After that, the timer starts decrementing. After this, the remaining time of the timer is "t <to" (the put time is tDμ [sec). ), the output becomes a put-time state of P. After changing the descendant variables (C) and (, the set frequency (F) is read again and the same operation is repeated. Therefore, if the set frequency (F) is switched, this set frequency (F) The output frequency changes from the time of reading.

FIG. 12 shows a block configuration diagram of the device according to the present invention, in which (8) is a frequency setting section, (9) is a microprocessor, and FIG. 7 is shown inside. 1st storage unit 00)
, a second storage unit (11) that stores the data shown in FIG. 9, a third storage unit α2 that stores the data shown in FIG. It consists of In addition, terminal (3), ■), (Z
+, ■, (to), (2 are connected to the base terminals of the respective transistors (2) to (power) of the three-phase inverter circuit shown in FIG.

The operation of the inverter control device configured as described above will be explained in detail again using FIG. The unit 04) reads the maintenance time "t=132" from the second storage unit Uυ based on 'F=20' and the value of 'CCo1' and sets it to the timer 0.

Next, based on the value of "θ=0 pad c=o", the transformer is converted in the third storage unit (12), stored in the first storage unit (10), and output as Δ. This output turns OFF, OFF, ON, ON, ON in sequence as shown in the state of 0 air angle in Figure 10.
, is in the OFF state. After this, timer 03) starts decrementing, and the remaining time of timer u31 is t (to
This state is maintained until ``.

That is, section T in FIG. 1O. It is. Furthermore, this section T
. During the latter half of the period (to Cm5cc), there is a dead time state and the transistors (2) to (7) are 0N-OF.
F state is OFF, OFF, OFF, ON, ON, OFF
becomes. Next, this timer α times up (1 (0)
Then, after changing the variable C1θ, the first
The operation based on the flowchart shown in FIG. 1 is repeated to obtain the section 'r1 of FIG. 10. Thereafter, in the same way, one cycle of transistors (2) to (
7) ON-OFF signal can be obtained.

When the value of the set frequency is changed while obtaining an AC output of 20 Hz in this way, the value of the set frequency (0) stored in the control unit α4) changes from the turn after 360 in FIG. The sustain time based on the new value of (F) is read from the circuit, and the ON-OFF state of transistors (2) to (7) and this sustain time are determined based on the flowchart of FIG. 11 in the same way as above. It is something to control.

In the case of such an inverter device, the output resolution is determined by the time accuracy of the maintenance time. In other words, the unit of maintenance time is, for example, "several tens of μ (sec)" → "μ [sec]"
”, the accuracy can be further increased.

(F) Effects of the Invention The inverter control device of the present invention includes a three-phase bridge section configured using a plurality of switching elements, a first storage section that stores the ON-OFF combination state of the switching elements, and a first storage section that stores the ON-OFF combination state of the switching elements. - a second storage section that stores a maintenance time for maintaining the OFF combination state; and a control section that outputs a continuous PWM output to the switching element by combining the ON-OFF combination state and this maintenance time. Therefore, the ON-OFF combination state of the switching element and its maintenance time can be stored separately, and the output of the switching element can be obtained by combining these. Therefore, PWM output for one cycle can be obtained with a small storage capacity. Go for efficient use of low-volume elements ν 1-. 1. ! -f
'- to T 2 towns, ri and 1 D'uυλl...width σ)
Since the A resolution can be determined by the value of the sustain time stored in the second storage section, there is no need to increase the capacity of the storage element in order to increase the resolution, unlike in the past. In other words, a high-resolution computer can be easily constructed with a small storage capacity.

[Brief explanation of drawings]

Figure 1 is an electric circuit diagram of a three-phase inverter, Figure 2 is an address map diagram of the contents of a memory element showing a conventional embodiment, and Figure 3 is an electric circuit diagram of a three-phase inverter.
Figure (a) is a waveform diagram showing three-phase AC, and Figure 3 (b) is a waveform diagram showing three-phase AC.
A waveform diagram in which the negative part of the waveform in Figure (a) is inverted, Figure 3 (
c) is 00 of any single molding shown in Figure 3(b).
A waveform diagram obtained by dividing ~180° into 6 parts and combining J1 East, Figure 4 is an explanatory diagram showing the waveform obtained by the present invention, Figure 5 is a partially enlarged view of Figure 4, and Figure 6 is In order to obtain the waveform shown in Figure 5, the transistors constituting the
An explanatory diagram showing the F state; FIG. 7 is an explanatory diagram showing the ON-OFF combination state of transistors constituting the inverter;
FIG. 8 is an explanatory diagram showing the ON-OFF combination state of the transistors constituting the inverter for one cycle; FIG. 9 is an explanatory diagram showing the maintenance time of the ON-OFF combination state of the transistors constituting the inverter; Figure 10 is an explanatory diagram showing an actual 1m ON-OFF state of transistors forming an inverter when the embodiment of the present invention is used.
The figure is a flowchart showing the operation of the embodiment of the present invention, and FIG. 12 is a block configuration diagram of the apparatus showing the embodiment of the present invention. 00)...first storage section, 01no...second storage section,
(14+...control unit. Applicant: Sanyo Electric Co., Ltd. and one other representative, patent attorney: Shizuo Sano @V, Figure 2, Figure 3 (1))

Claims (1)

[Claims] (1) A three-phase bridge section configured using a plurality of switching elements, a first storage section that stores the ON-OFF combination state of this switching element, and a first storage section that stores the ON-OFF combination state of this switching element;
a second storage unit that stores a maintenance time for maintaining the combination state; and a control unit that outputs a continuous PWM output to the switching element by combining the ON-OFF combination state and the maintenance time. An inverter control device featuring: