JPS60201310A - Distance detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a distance detection device, in particular, a distance detection device that projects light from a light source onto a distance measurement object, and generates two current outputs that are determined corresponding to the incident spot position on a light receiving means of reflected light from the distance measurement object. The present invention relates to a distance detection device used in a camera or the like that detects the distance to a distance measurement target based on a relationship.

Conventionally, this type of distance detection device uses, for example, an infrared light emitting diode (hereinafter referred to as IRED) as a light source.

As a light receiving device, for example, a semiconductor device detection element (hereinafter referred to as PSD) is used.
) is used to detect the distance to the measurement target based on the following principle.

That is, the IRED projects pulsed light onto the object to be measured, and the PSD receives the reflected light.

If the distance to the distance measurement target differs, the parallax of the reflected light will also differ.
Therefore, the spot position of the reflected light on the PSD is also different. This change in spot position changes the resistance ratio on the current path, so the output current ratio also changes.

Therefore, by comparing these output currents, the distance to the object to be measured can be calculated.

Incidentally, the output current value is influenced by the intensity of the reflected spot light incident on the PSD, and becomes large when it is strong and small when it is weak. For this reason, it is necessary to provide a signal compression means or the like in front of the comparator circuit to ensure the dynamic range of the signal, but this has the drawback of complicating the circuit and degrading the S/N ratio.

In addition, when used in automatic focus adjustment devices such as cameras, it is necessary to standardize the output current value of the comparison circuit in order to correspond to the drive of the photographic lens, but the output current value may change due to fluctuations in temperature or power supply voltage. was there. For this reason, the correspondence between the output current value and the digital zone signal for controlling the photographic lens is broken, resulting in a drawback that accurate focus adjustment cannot be performed.

The present invention has been proposed in view of the above-mentioned drawbacks, and is based on PSD
The purpose of the present invention is to provide a distance detection device with a simple configuration and high accuracy by outputting one or both current outputs through an amplifier with a variable amplification factor and comparing these outputs. be.

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are principle diagrams showing the principle of the present invention.

In FIG. 1, 2 is a light source, I RED,
4 is a PSD which is a light receiving element, 6 is a light emitting optical system,
8 is a light receiving optical system.

When the distance measurement target is at the position Dl, the pulsed light reflected from the distance measurement target from the IRED 2 through the light emitting optical system 6 is focused on 4a on the PSDd through the light receiving optical system 8, and is outputted to the terminal 4.
Currents IA and In are output from A and 4B, respectively. The distance measurement target is D2°D3. When located at each position of psD4, images are formed on 4b, 4a, and 4d on psD4, and currents corresponding to the imaged positions are output.

Figure 2 is a schematic sectional view showing the structure of PSD4, and
is an N-type semiconductor layer, 4P is a P-type semiconductor layer, and the P-type soil conductor layer 4P has resistance values R1, R2, R3,
It has R4 and R5. Here, R1 is 4 from terminal 4A.
The resistance value from 4a to 4b, R2 is the resistance value from 4a to 4b, R
3 is the resistance value from 4b to 4C, 4 is the resistance value from 4c to 4d, and R5 is the resistance value from 4d to terminal 4B.

When the reflected spot light is not incident on the P-N junction, it remains reverse biased and no current flows; when the reflected spot light is incident, electron-hole pairs are generated and a current flows in the junction, causing the current lm and IB
flows.

Table 1 shows that the reflected pulsed light is 4 a + 4 b on PSDJ.
Output current I when imaged on +4e and 4d, respectively
It shows the relationship between A and IB. Here ■ is Ih and l
It is the sum of II.

Table 1 FIG. 6 is a diagram showing the principle of signal processing in the present invention. Reference numeral 10 denotes an amplifier that amplifies one of the output currents (for example, IA) of the PSD 4, and its amplification factor is denoted by G. As is clear from the relationship in Figure 2, when the pulsed light reflected from the distance measurement target is imaged on 4a on the PSD 4, G = R+
/ 1*- when (R2+ Rs+ R4+ Ra)
When G=In and similarly imaged on 4b, G= (
When R++ Rz ) /(R3+ R4+ R5), IA-G=In, and when imaged on 4c, G= (
When R++Rt+Rs)/(Ri + Rs), IA・G=
When it becomes Is+ and is imaged on 4d, G = (RI+
R2+ R3+ R4) /'When R5, Ia-G=
Becomes In.

Therefore, amplification factor G and Ia-G: >In and ■A-G
The relationship between the imaging positions resulting in IB is shown in Table 2.

In other words, G = R+/(R2+ Rs+ R4+ R5
), if G>Is, the image is formed between 4A and 4&, and if it is ll-G (In, it can be detected that the image is formed between 4a and 4B.Similarly, if G −
When (R1+R2)/(R3+R40R), IA-
G) II is between 4A and 4b.G(III
Then, it is between 4b and 4B, and G=(R++ R2+
When Rs)/(R4+Ra), Ia-G)I
If s, it is between 4A and 4c, and if G<III, it is between 4c and 4B, and G = (R++ R** R3+
When R4/R5, if IA-G>IB, 4A to 4
If IA-G <Ia between 4d and 4B, it can be detected that each image is formed between 4d and 4B. Therefore, the amplification factor G is R1/(R2+R3+R4+R5) +(RI+
R2)/(R3+R4+R6), (RI+R2+R
8)/(R4+R5).

(R+ + R2+ Rs+ R4) /R5 and 111
Next, change 4A to 4a by comparing E^・G and In at that time.

It is possible to detect where the image is formed between 4a and ab, 4b and 4c, 4c and 4d, and 4d and 4B.

Table 2 FIG. 4 is a circuit diagram of an embodiment of a distance detection device for a camera according to the present invention. Reference numeral 12 denotes a power supply circuit block, which outputs VCC, which is the circuit power supply, and VC2, which is the bias voltage to the PSD 4, and KVC, which is the reference voltage, in response to pressing the release button of the camera. Reference numeral 14 denotes a PUC signal generation block, which outputs a PUC signal for power-up clear to a control block 20, which will be described later, when the power supply VCC is turned on. Reference numeral 16 denotes a light projection block, which drives the IRED 2 in response to a control signal 200 from the control block 20. A light receiving block 18 calculates the output signal from the PSD 4 according to control signals 201 to 206 from the control block 20, and outputs the calculation result to the control block 20 as an output signal 207. 20
is a control block which outputs control signals 200 to 2'06 to the light emitting block 16 and the light receiving block 18, detects the distance of the distance measurement target from the output signal 207 of the light receiving block 18, and sends the distance measurement end signal END and Distance zone trust Zl, Z2. Z3. Z4. Output Z5.

In the power supply circuit block 12, 61 is a power supply battery, SW
is a switch that is linked to pressing the camera's release button, and turns on and off when the photographer presses the release button.
It turns off when released. 62 and 66 are capacitors, and 64 is a choke coil, which constitute a π-type power filter. Reference numeral 65 denotes a known constant voltage circuit, which inputs the power supply VCC and outputs a bias power supply VC of the PSD 4 and a reference voltage KVC of each amplifier to be described later.

In the PUC signal generation block 14, 41 is a resistor;
2 are capacitors connected in series with each other, and the capacitor 42 is charged via a resistor 41 from the power supply CC. 46 is an inverter.

The input is connected to a connection point between a resistor 41 and a capacitor 42. When the power supply VCC is turned on, the voltage at the connection point between the resistor 41 and the capacitor 42 is QV, so the PUC signal, which is the output of the inverter 46, becomes a "H" level, but the capacitor 42 is charged and the inverter 46 continues. When the voltage exceeds the threshold voltage of , the PUC signal becomes L'' level.

In the light projection block 16, 51 is an OP amplifier with a strobe terminal, which operates when the strobe terminal is open, but does not operate when a transistor 55, which will be described later, is conductive. 52 is a transistor whose base is controlled by the output of an operational amplifier (hereinafter referred to as OP amplifier) 51 and drives RED2. 53 and 54 are resistors, which divide the voltage across IRBD2 and connect it to the op amp 51.
Feedback to the inverted input. 55 is a transistor whose base is controlled by the control signal 200 from the control block 20 and controls the strobe terminal of the OP amplifier 51. That is, when the control signal 200 is at the "H" level, the transistor 55 becomes conductive and the OP amplifier does not operate, so that the IRED 2 is turned off. - force control signal 20
0 is at the “L” level, the transistor 55 is not conductive (the nistrope terminal is in an open state, and the OP amplifier 5
IRED 1 is activated, and IRED 2 is driven by transistor 52 and lights up. A resistor 56 limits the base current of the transistor 55.

In the light receiving block 18, (Sl, 62 is an OP amplifier and 63.64 is a resistor. The output current A of the PSD 4 is converted into voltage by the OP amplifier 61.Resistor 63, and the output current IB is the OP amplifier 62.Resistor 64. 65 and 66 are capacitors that cut the DC component of the output voltage of the OP amplifier 61 and 62. 67
is an op amp.

68 is a resistance. Since the resistor 68 has one end connected to the reference voltage KvC, the signal whose DC component is cut off by the capacitor 65 becomes an AC signal with the voltage KVC as a reference. The op amp 67 has its inverting input and output connected, and operates as a buffer. 69,70,71.72
．． 73 is a resistor, 74°, 75, 76, and 77 are analog switches, and 78 is an operational amplifier, and these elements operate as an inverting amplifier. Analog switch 74, 75
, 76° and 77 are turned on and off by control signals 201 and 201, respectively.
202゜205.204, when each control signal is at "H" level, the corresponding analog switch is turned on, and when it is at "IIL" level, it is turned off.Respective resistors of 69゜70.71.72.73 The value R1'.

If R7, R11', R4', and Rs' are set, the gain of the inverting amplifier when only the analog switch 74 is turned on is -R1'/(R1+R3'+R4'+Ra'), and similarly, the analog switch 75.76 When .77 is turned on individually, each gain is -(R+'+R2'
)/(Rs+R4'+R11') + (R+'+ R
2'+ R3')/ (R4'+ R5'), (R
4'+ R2'+ R3'+R41') /R5'
become. 79, 80, and 81 are resistors, and 82 is an operational amplifier, and these elements operate as an adder. OP
Since the non-inverting input of the amplifier 82 is connected to the reference voltage KVC, the inverting input also has the same potential as KVC, and therefore the signal whose DC component has been cut by the capacitor 66 has the voltage KVC.
It becomes an AC signal based on VC. 83.84 is an analog switch, and 85.86 is a capacitor. The analog switches 83 and 84 are turned on and off by control signals 205 and 206, respectively. When each control signal is at the "°H" level, the corresponding analog switch is turned on, and when it is at the "L" level, it is turned off. The analog switch 86 and the capacitor 85 operate as a sample and hold circuit, and the capacitor 85 samples the output of the OP amplifier 82 when the analog switch 86 is turned on, and holds it while the analog switch 86 is turned off. Similarly, analog switch 84 and capacitor 86 also operate as a sample and hold circuit. 87 is a comparator, the inverting input is connected to the capacitor f85, and the non-inverting input is connected to the capacitor 86.
, and when the voltage of capacitor 85 is higher than the voltage of capacitor 86, output signal 207 is “L I
+ level, when it is low, it becomes “H level”.

In the control block 20, 91, 92, and 96 are inverters, 94 is a resistor, and 95 is a capacitor. Inverters 91 and 92 and resistor 94. Capacitor 95 operates as a CR type oscillation circuit. The inverter 96 shapes the sinusoidal oscillation output into a rectangular wave. 96, 97, and 98 are D-type flip-flops (hereinafter referred to as FF), and the Q output of FF96 is connected to the D input of FF97, and the Q output of FF97 is connected to the FF.
The Q output of FF 98 is connected to the D input of FF 98, and the Q output of FF 98 is connected to the D input of FF 96, and all the CLOCK inputs are connected to the output of inverter 96, forming a so-called Johnson counter. 99 and 100 are AND gates, and AND gate 99 connects the Q output of FF96 and the FF
It inputs the Q output of 98 and outputs a control signal 205 to the analog switch 86. anime game) 100 is FF96
The control signal 206 to the analog switch 84 is output by inputting the Q output of the FF 98 and the mutual output of the FF 98.

101 is an or gate, and the or gate 114 will be described later.
The Q output of FF98 is passed only when the END signal, which is the output of FF98, is at the "L11 level".

102 is a 7-bit binary counter, and the output of the OR gate 101 is used as the CLOCK input.

106 is an OR gate, which receives the PUC signal and the E described below.
The ND signal is input. 104 is an R8 type FF, which is reset by the output of the OR gate 103 and outputs the counter 10.
It is set by the Q1 output of 2.

105 is an OR gate, which outputs FF98 and F
The calculated power of F104 is input, and its output is the control signal 20
0 and is connected to the light projection block 16. When the output of the OR gate 105, that is, the strobe terminal is at the "H" level, I'RE D 2 is turned off, and when the output is at the "L" level, I'RE I) 2 is turned on.

106 is a D-type FF, and the output signal 207, which is the output of the comparator 87 of the light receiving block 18, is used as the D input;
The calculation output of F98 is used as the clock input. 107 is a three-man power AND gate, FF98 glue output, counter 10
The Q4 output of 2 and the calculation power of FF106 are input. The counter 102 uses the calculation output of the FF98 as a clock input through the OR gate 101, and the Q4 output of the counter 102 is “
The output of the AND gate 107 becomes 'H' level during 8 clocks of the output of the FF 98. Therefore, the output of the AND gate 107 is within the period in which the Q4 output of the counter 102 is at the 'IH' level, and the calculation output of the FF 106 is Depending on whether it is at the "H" level or the "L" level, the pulse output ranges from a maximum of 8 pulses to a minimum O pulse. 108 is a 3-bit binary counter that counts the number of pulses output from the AND gate 107. 109 is an OR gate, which receives the PUC signal and the output of an AND gate 112 (described later), and its output resets the counter 108. 110 is an inverter, which receives the Q3 output of the counter 102 as input.

111 is an inverter, which receives the Q4 output of the counter 102 as an input. 112 is an AND gate, and the Q2 output of the counter 1.02, the output of the inverter 110, and the output of the inverter 111 are inputted manually.

116 is an R8 type FF that is reset by the PUC signal,
It is set by the Q3 output of counter 108. 114
is an OR gate, which inputs the Q7 output of the counter 102 and the calculation output of the FF 113, and outputs the output as an END signal. 115 is an inverter, which receives the Q5 output of the counter 102 as an input. 116 is an inverter, and 211 receives the Q6 output of the counter 102 as an input.
7 is an AND gate which receives the output of the inverter 115 and the output of the inverter 116, and its output is output as the control signal 201. 118 is an AND gate, which connects the Q5 output of the counter 102 and the inverter 1.
16 is input, and the output is output as a control signal 202 and a z2 signal. 119 is an AND gate, which connects the Q6 output of the counter 102 and the inverter 11.
5 is input, and the output is output as a control signal 206 and a z3 signal. Reference numeral 120 denotes an AND gate, which has inputs as the Q5 output and Q6 output of the counter 102, and its output is output as the control signal 204 and the z4 signal. 121 is an inverter, and counter 102
The Q7 output of is input.

122 is an AND gate, which receives the output of the AND gate 117 and the output of the inverter i21, and outputs the output as the z1 signal.

Next, the operation of the signal processing circuit according to the embodiment of the present invention will be explained. When the photographer presses the release button and turns on the switch SW, the power supply VC is supplied from the power supply circuit block 12.
c, VC, and KVC are output. When the power supply VCC is supplied, the PUC signal generation block 14 outputs a PUC signal at the H" level for a time determined by the time constants of the resistor 41 and capacitor 42 and the threshold voltage of the inverter 43. This PUC signal causes the FF 96, 97°9
8.113 and counter 102 are reset. Further, the FF 104 is reset via the OR gate 106, and the counter 108 is also reset via the OR gate 109. FF
104 is reset, the calculation output becomes "Hn level," and the control signal 200 also becomes "Hn level" through the OR gate 105.
The level becomes H''. Therefore, the transistor 55 of the light projection block 16 becomes conductive, and the IRED 2 is turned off.

Since the counter 102 has been reset, the Q7 output is “
Since the calculation power is "L" level and FFI 16 has also been reset, the calculation power is "L" level. Therefore, OR gate 1
The output of counter 102 is also at the "L" level.
Since the 2 output, the Q3 output, and the Q4 output are at the °L" level, the output of the AND gate 112 is also at the °L'" level. Since the Q5 output and Q6 output of the counter 102 are at the L" level, the output of the inverter 115 is at the jlH" level, and the inverter 11
6 output? >"H" level, and as a result, the output of AND gate 117 becomes "H" level, and AND gate 118
The output of the AND gate 119 is also "L" level.

The output of the AND gate 120 also goes to the "L" level.

When the PUC signal returns from the °H' level to the "L" level, each FF and counter are released from reset.

The operation of each part at this time will be explained with reference to the timing chart shown in FIG. In FIG. 5, (a) is the PUC signal,
(b) is the output of inverter 93, (C) is F F 99
(d) is the Q1 output of the counter 102, (e)
is the distorted output of the FF 104, and (f) is the output of the OR gate 105. FF96.97.98 is shown in Figure 5 (a) +:
, when the reset by the PUC signal shown in FIG. 5 is released, the FF 98 operates using the output of the inverter 93 shown in FIG.

Since the Q output of the FF 98 becomes the clock of the counter 102 via the OR gate 101, the Q1 output of the counter 102 becomes as shown in FIG. 5(d).

Since the FF 104 is set by the Q1 output of the counter 102, the output becomes the "L5 level" as shown in FIG. As shown in FIG. (f), the Q output of F''F1a is passed through, and the IRED 2 is blinked by the control signal 200.

The light projected from the I RED 2 is reflected by the object to be measured, and the reflected light is imaged on the PSDJ.

First, a case where the distance measurement target is closer than Dl in FIG. 1 will be explained. At this time, the reflected light spots are 4A and 4 shown in Figure 2.
The image is formed in the middle of a. The signal waveforms of each element in the light receiving block 18 are shown in FIG. 6 below.

In FIG. 6, (a) is the blinking waveform of IRED2,
° “L” level indicates off, uH” level indicates on. (b
) is the waveform at the connection point of capacitor 65 and resistor 68, (C)
is the waveform at the connection point between the capacitor 66 and the resistor 80, (d) is the output waveform of the OP amplifier 78, (e) is the output waveform of the OP amplifier 82, (f) is the waveform of the control signal 205, and (g) is the control signal. 2060 waveform, (h) is the inverted input terminal voltage waveform of the comparator 87, (i) is the non-inverted input terminal voltage waveform of the comparator 87, and (j) is the output waveform of the comparator 87. When I RED2 blinks as shown in FIG. 6(a), PSD4 is connected to the connection point between capacitor 65 and resistor 68, and the connection point between capacitor 66 and resistor 80, respectively.
Figure 6(b) corresponds to the output currents IA and IB from
And an alternating current signal based on KVC as shown in (C) is generated. Since the OP amplifier 67 operates as a buffer amplifier, the output voltage waveform of the OP amplifier 67 is shown in FIG.
) is the same as Control signal 201.202.203.2
04, only 201 is at the "H" level at first, so only 74 of the analog switches f74°75.76.77 are on.

At this time, resistances 69 (R1') and 70 (R2')
, 71 (R3'), 72 (R4'), 73
The gain G of the inverting amplifier consisting of (Rs) and the op-amp 78 is -RI'/(R2' + R8' + R4' +
R5'), and the output voltage of the OP amplifier 78 is the sixth
The result will be as shown in figure (d). Here, the resistances of each part of the light receiving element 4 are R1+R2+R3+R4, R5 and Rr', R2
The relationship between T Rs HR4'HRs' is as follows.

One town - 5 - 4' - Tori' = μ' - □ R + Rt Rs R4R11 At this time, as is clear from the relationship in Table 2, I^・(G)>
IB.

therefore! ＾・G+l5(0. Therefore, the output voltage of the adder consisting of the resistors 79, 80.81 and the op-amp 82 is below KVC when IRED2 lights up as shown in FIG. 6(e).
When the light goes out, it becomes more than KVC. Since the control signal 205 of the analog switch 86 becomes "H" level when the IRED 2 is turned on as shown in FIG. 6(f), the voltage sampled and held in the capacitor 85 becomes KVC as shown in FIG. 6(h).
The voltage will be as follows.

In addition, since the control signal 206 of the analog switch Y-84 becomes "H" level when IRED2 is turned off as shown in Fig. 6 (g), the voltage sampled and held in the capacitor f86 is Therefore, since the voltage at the non-inverting input of the comparator 87 is higher than that at the inverting input, the output of the comparator 87 becomes an "H" level as shown in FIG. 6 (j). It is communicated to control block 20 as signal 207.

On the other hand, the control block 20 issues an END signal;
The operation at this time will be explained using the timing chart shown in FIG. In Fig. 7, (a) is AND gate 1
17 output, (b) is the blinking waveform of IRED2, (C) is the Q2 output of the counter 102, (d) is the Q3 output of the counter 102, (e) is the Q4 output of the counter 102, (f)
is the output of the comparator 87, (g) is the ζ output of the FF 106, (h) the output of the FF 107, (i)
is the Q3 output of the counter 108, ('') is the OR gate 11
This is the output of 4. AND gate 117 by PUC signal
The output becomes “H” level as shown in Figure 7(a), and O
The gain of P amplifier 78 is determined. At this time, the Q7 output of the counter 102 is at the "L" level, so the output of the inverter 121 is at the "H" level, and the z1 signal is also at the "H" level.
level. When the reset by the PUC signal is released, IRED2 starts blinking as shown in Fig. 7(b), and the counter 102 also starts blinking as shown in Fig. 7(C), (d), (e).
Start counting like this.

When I RED2 starts blinking, the light reception block 18 processes the light reception signal at PSD4, and the comparator 87
The output becomes "H" level as shown in FIG. 7(f). FF
Reference numeral 106 receives the output of the comparator 87 as an input, and is also at the "H" level. When the count of the counter 102 progresses and the Q4 output reaches the "l Hl" level as shown in FIG. The counter 108 counts the pulses from the AND gate 107, and when the count reaches 4, the Q3 output goes to the "H" level as shown in FIG. 7(1). The FF 116 is set at the rising edge of the Q6 output of the counter 108, and since the ζ output becomes "HI+ level", the output of the OR gate 114 also becomes "as shown in FIG. 7 (0)".
The output of the OR gate 114 becomes °H" level.
When the level is reached, the output of the OR gate 106 also becomes the “H1” level, the FF 104 is reset, and the ζ output becomes “H1”.
It becomes l level. Therefore, the output of OR gate 105 is also H”
level, and IRED2 turns off. Also, or gate 1
The output of 01 also becomes "H" level, and the counter 102 stops counting. At this time, the control block 20 outputs the END signal, which is the ranging operation end signal, and the z1 signal, which is the zone signal, at H'' level.

Next, a case where the object to be measured is located between D2 and D3 in FIG. 1 will be described. At this time, the reflected light spot is imaged midway between 4b and 40 shown in FIG.

When only the output of AND gate 117 is at "H" level, resistors 69, 70.71, 72.75 and OP amplifier 78
The gain G of an inverting amplifier consisting of -R1'/(R2'
+ R3' + R4' + R6'), so
As is clear from the relationship in Table 2, IA・(G) < III.

Therefore, IA-G+I〉0. Therefore, the output of the adder made up of the resistors 79, 80.81 and the OP amplifier 82 is above KVC when IRED2 is turned on, and below KVC when it is turned off. Therefore, since the output of the comparator 87 is at the "L" level, the ζ output of the FF 106 is also at the "L" level, and no pulse is output from the AND gate 107. counter 10
Since the count number of 8 remains 0, the FFI 16 is not set, so the output of the OR gate 114 remains at the "L" level, the IRED 2 continues to blink, and the counter 102 also continues to count. Counter 102 advances Q4
The output becomes “L 11 level,” and the Q5 output becomes “+H.”
+” level, the output of the inverter 115 becomes “L” level, so the output of AND gate 117 also becomes “L” level, but instead, the output of AND gate 118 becomes “H” level.
become the level. When the output of the AND gate 118 becomes "H" level, the gain G becomes -(R+'+R2')/(Ra
' + R4' + R7), and as is clear from the relationship in Table 2, ■mu・(G)<IB.

Therefore, ■^・G+I++)0 is obtained, and the output of the comparator 87 is still L'°, and the count of the counter 102 continues as it remains as a pel.

When the count of the counter 102 progresses and the Q5 output reaches the "L" level and the Q6 output reaches the 1 "H" level, the inverter 1
The output of inverter 15 is at Hn level, and the output of inverter 116 is “
Since the L I+ level is reached, the output of the AND gate 118 becomes the "L'" level, and instead the output of the AND gate 119 becomes the °H level. When the output of the AND gate 119 becomes the "HI+ level", the gain G becomes -(R+'+R
2'+R3')/(R4''+Rs'), and as is clear from the relationship in Table 2, Ih.(-G)) IB.

Therefore, ＾・G+In<0. Therefore, the output of the comparator 87 becomes the H11 level, and the Q output of the FF 106 also becomes the HII level. On the other hand, when the Q4 output of the counter 102 becomes "H" level, a pulse is output from the AND gate 107, the counter 108 starts counting, and when the count number reaches 4, the Q3 output becomes "i H+" level, and the FF1
13 to bring the output of the OR gate 114 to the "H" level. When the output of the OR gate 114 becomes HI+ level, IRED2 goes out and the counter 102 stops counting. At this time, the END signal and z3 signal are “H”.
It will be level 11.

Next, a case where the distance measurement target is farther than D4 in FIG. 1 will be explained. At this time, the reflected light spots are 4d and 4B shown in Figure 2.
The image is formed in the middle of In this case, the counter 102
As the count progresses, the output of AND gate 119 becomes “H”
level and rege in G is -(R+'+R2'+R3'
)/(RX+Rs), as is clear from the relationship in Table 2, IA・(-G)(Is).

Therefore, IA-G+IB)0. Therefore, the output of the comparator 87 remains at the "L II level", the count of the counter 102 continues, and both the Q5 output and the Q6 output of the counter 102 become "H" level. At this time, the output of the anti-game 119 is " The output of the AND gate 120 becomes the "°H" level instead.

Here, the gain G is -(R1' - R2' + R3'
+R4') /Rs', but as is clear from the relationship in Table 2, IA・(G)<IB.

Therefore, IA-G+In)0. Since the output of the comparator 87 is still a "'L" level, the count of the counter 102 further advances.When the count of the counter 102 advances and both the Q5 output and the Q6 output become the "L II level" and the Q7 output becomes the "H" level, the OR gate 114 Also °H'.

become the level. Here, IRE and D2 go out and counter 1
The count of 02 also stops. At this time, the output of the inverter 121 is at the "L I+ level," so even if the output of the AND gate 117 becomes the "HI+ level," the output of the AND gate 122 remains at the "L I+ level. Therefore, the END
signal and z5 signal become °゛H level.As mentioned above, when the END signal becomes "H1 level", the distance of the object to be measured depends on which signal from z1 signal to z5 signal is "H'level".゛The above-mentioned principles and embodiments apply to PSD as a light receiving element.
Although the description has been made on the assumption that the present invention is not limited to a PSD, the present invention may be applied to a light receiving element shown in FIG. 8, for example. In Figure 8, 3
01 and 302 are silicon photodiodes, and 303 and 304 degrees 605 shown by dotted lines are IRED spot images. Silicon photodiodes 601 and 6
02 have the shape of a right triangle, for example, and the oblique sides thereof face each other. The spot image of the IRED is formed at a position 606 when the object to be measured is at a short distance, at a position 604 when it is at an intermediate distance, and at a position 605 when it is at a long distance. I RED depending on the distance of the distance measurement target
As the position of the spot image changes, the ratio of light amounts incident on the silicon photodiodes 301 and 602 changes.
The ratio of the photocurrents generated in the two amplifiers will also change, and by changing the gain of one amplifier and comparing it with the other, distance information can be obtained.

Furthermore, in the above embodiment, it is possible to digitally change the gain of the amplifier to obtain a distance zone signal, but the resistance that determines the gain of the amplifier is replaced by a variable resistance that changes according to the rotation of the distance ring of the photographing lens. By doing so, it is possible to display the front focus and the rear focus, and it is also possible to servo control the photographic lens using a motor.

As explained above, according to the present invention, in the relationship between two current outputs corresponding to the incident spot position on the light receiving means, the gain of the amplifier that amplifies one current output is changed and compared with the other current output. Since distance information is obtained by doing this, there is no need to provide a signal compression means, etc., the circuit configuration is relatively simple, and the disadvantage of a small dynamic range is eliminated. Also, unlike conventional systems in which the value of the output current of the comparator circuit directly corresponds to the distance detection l, the comparator circuit detects only the magnitude relationship of the input voltage, so the amount of distance detected due to changes in the power supply voltage or temperature There is no change in Therefore, the distance zone signal for setting the position of the photographic lens of the camera always has an accurate value.

[Brief explanation of drawings]

1 to 6 are diagrams for explaining the principle of a distance detection device according to an embodiment of the present invention, FIG. 4 is a signal processing circuit diagram according to an embodiment of the present invention, and FIGS. A timing chart or a waveform diagram of the signal processing circuit diagram shown in the figure, and FIG. 8 is a top view of a light receiving element according to another embodiment of the present invention. 2... Infrared light emitting diode (IRED), 4... Position detection diode (PSD), 14... PUC signal generation block, 16... Light emitting block, 18... Light receiving block, 20...・Control block. Patent applicant Canon Co., Ltd. c Figure 2 lA3

Claims (1)

[Claims] In a distance detection device that projects light from a light source onto a distance measurement target and detects the distance of the distance measurement target based on two current output relationships determined in accordance with the incident spot position on a light receiving means of light reflected by the distance measurement target. , comprising an amplifier that amplifies the one current output, a control means that changes the amplification factor of the amplifier, and a comparator that compares the output current of the amplifier with the other output current that does not go through the amplifier. . A distance detection device, characterized in that the distance of the object to be measured is detected based on the output information of the comparator and the amplification factor setting information.