JPS60205653A - Data transfer system - Google Patents

Abstract

PURPOSE:To reduce the number of transfer control signals and a control procedure, and speed up data transfer and simplify a circuit by using a write signal from a transmission-side microprocessor as an interruption signal to a reception- side microprocessor as it is. CONSTITUTION:The transmission-side microprocessor (MPU) 21 while sending out a data signal to a bus gate circuit 11 from a data bus 2-10 transmits the write signal 2-14 to a READY returning circuit 13 and an interruption control circuit 12. The interruption signal 23 from the interruption control circuit 12 is received by the reception-side MPU31, which then sends a readout signal 2-12 to the bus gate circuit 11 and READY returning circuit 13 to input the data signal from a data bus 2-11. The READY returning circuit 13 which receives both the readout signal 2-12 and write signal 2-14 sends a READY signal 2-15 to the transmission-side MPU21. The transmission-side MPU21 stops sending out the write signal 2-14 and the data transfer operation is ended.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a data transfer system, and particularly to a data transfer system that connects a plurality of micro computers using a data bus.
This relates to a data transfer method for transfer control lines in computer application systems.

BACKGROUND ART Conventionally, data processing systems that perform distributed control using a plurality of microcomputers have been widely used in various fields. In that case, data transfer control between the microphone p and the computer is performed using the circuit configuration shown in FIG.

FIG. 2 is an operation time chart in the circuit of FIG. 1.

In FIG. 1, 1 is a latch circuit, 2 is a buffer gate circuit, 3 is an interrupt control circuit, 4 is a READY return circuit,
δ is an interrupt clear control circuit, 2o is a transmitting side MPU, and 30 is a receiving side MPU.

The data connecting the transmitting MPU 20 and the latch circuit 1 in FIG. 1 is 8.16°3.
It is a 2nd class bit'14 configuration and is used for sending and receiving data signals. The above data signal is temporarily stored in the latch circuit l by the "write" signal (1-14) from the transmitting MPU 20, and then sent to the buffer gate circuit 2 through the data bus (1-11). Ru. Furthermore, in response to the above "write" signal (1-14), the READY return circuit 4 returns a "READY" signal (1-16) to the transmitting MPU 20, reporting that the data signal has been stored in the latch circuit 1. do.

The transmitting MP that received the “READY” signal (1-16)
U20 sends an "interrupt control" signal (1-17) to report to the receiving MPU 30 through the interrupt control circuit 3 that the data signal is being input to the buffer gate circuit 2. The receiving side MPU 30 includes a buffer gate circuit 2
The read signal (1-13) is sent to the data bus (1-12), the data signal is taken in from the data bus (1-12), and the "interrupt clear" signal ( 1-19). Sending side MPU2
0 stops sending the "interrupt control" signal (1-17) and the data transfer operation ends (see FIG. 2).

However, in the data transfer process described above, "writing" is required to store the latch circuit IK data signal.
Since the signal (1-14) and the "interrupt °' signal 1-15) for the receiving MPU 30 are required, the processing time is long, the processing program is complicated, and the number of circuit components increases, etc." There is.

An object of the present invention is to eliminate such conventional drawbacks, increase the speed of data transfer, and simplify the circuit without reducing the reliability of data transfer processing even if the number of transfer control lines is reduced. The object of the present invention is to provide a data transfer method that can perform the following steps.

composition Hereinafter, the configuration of the present invention will be explained using examples.

FIG. 3 is a block diagram of a data transfer circuit showing one embodiment of the present invention, and FIG. 4 is an operation time chart of FIG. 3.

In FIG. 3, 11 is a bus gate circuit, 12 is an interrupt control circuit, 13 is a READY return circuit, and 21 is a transmitting side MP.
U, 31 is a receiving MPU.

The transmitting MPU 21 in FIG.
), the data signal is sent to the bus gate circuit 11, and at the same time, the "write" signal (2-14) is sent to the READY signal (2-14).
It is sent to the return circuit 13 and the interrupt control circuit 12.

1 interrupt" signal (2-13) from the above interrupt control circuit 12
By receiving it at the receiving side MPU 31, the receiving side MP
U31 sends the “read” signal (2-12) to the bus gate circuit 1.
1 and READY to the return circuit 13 to take in the data signal from the data bus (2-11).
-14) The READY return circuit 13 sends the "READY" signal (2-15) to the transmitting MPU 21.
Send out. The transmitting side MPU 21 sends a 6 write” signal (2-
14) is stopped, and the data transfer operation ends.

(See FIG. 4) In other words, in order to directly read the data signal sent by the transmitting MPU 21 into the receiving MPU 31, a "write" signal (2-14) from the transmitting MPU 21 is sent.
) is directly sent to the receiving MPU 31 as an "interrupt °" signal (2
-13), the number of transfer control lines can also be reduced.

In this manner, by providing the data transfer circuit of the present invention in the data bus connecting the microphone and the computer, the data transfer process can be performed at high speed with a simple transfer control signal procedure.

Effects As explained above, two points: according to the present invention, it is possible to reduce the number of transfer controls and their control procedures, thereby increasing the speed of data transfer processing and simplifying processing programs.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a conventional data transfer circuit, Fig. 2 is an operation time chart of the circuit of Fig. 1, and Fig. 3 is a data transfer circuit showing an embodiment of the present invention. The block diagram and FIG. 4 are operation time charts in the circuit of FIG. 3. l: latch circuit, 2: buffer gate circuit, 3.12
: Interrupt control circuit, cow, 13: READY return circuit, 5:
Interrupt clear control circuit, 11: Bus gate circuit, 20.2
1: Sending side MPU, 30°31 = receiving side MPU 0 Figure 1 n Figure 6 1

Claims (1)

[Claims] In a data processing system that transfers data using a data bus line and a transfer control line connected between multiple data processing devices, the data bus line is made conductive by a read signal from the receiving data processing device. gate means for;
A between the above read signal and the write signal of the sending data processing device
The ND has a sending means for sending a transfer end signal to the sending data processing device, and after the receiving data processing device interrupts and receives the write signal, it sends out a read signal for fetching data. Data transfer method.