JPS60208873A - Manufacture of josephson junction element - Google Patents

Abstract

PURPOSE:To disregard over-etching and to manufacture a Josephson junction element having a tunnel barrier part with excellent dimensional accuracy, by applying an ion etching method having excellent anisotoropy and selectivity in forming the tunnel barrier part. CONSTITUTION:On an insulating substrate 11, three-layer films, i.e., a first superconductive electrode 12, a tunnel barrier layer 15 and a second superconductive electrode 21, are formed. A resist mask 22 is formed at the place of the tunnel barrier part on the second superconductive electrode 21. Thereafter perfect etching is performed by an ion etching method. Then, a first insulator layer 23 is formed on the exposed surfaces of the first and second superconductive electrodes 12 and 21. Thereafter, a second insulator layer 24 of SiO and the like is deposited. The resist mask 22 is lifted off and a pattern is formed. A third superconductive electrode 25 is formed by the same way. The first insulator layer 23 prevents the short circuit between the first superconductive electrode 12 and the third superconductive electrode 25 through pinholes in the insulator layer 24.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a Josephson junction device, and particularly to a method for manufacturing a tunnel barrier type Josephson junction device i).

(Prior art and one of its problems) In general, logic circuits and memory circuits made of Josephson junction elements have excellent junction characteristics, small variations in these characteristics between elements, and characteristics that may be affected by thermal cycles. Elements with minimal deterioration are required. As a device that satisfies both of these integration requirements of excellent bonding properties and high reliability, niobium (Nb) or a Nb compound is used for the first superconductor electrode, and lead (Pb) is used for the second superconductor electrode. Alternatively, those using a pb gold alloy are attracting attention. However, this p
Since b-based materials are chemically unstable, conventional patterning methods have been limited to the lift-off method.

As an example of this conventional example, R.F.E.Broom et al. published an article in the American magazine "IEBB Trans" in 1980
actionson Electron, Devic
ES” Volume ED-27 No. 10 1998-2008
There are papers published on the page.

The method described in this paper will be explained step by step using cross-sectional views of FIGS. 1(a) to 1(f).

First, as shown in FIG. 1 (aJ), a first superconductor electrode 12 made of Nb is formed on an insulating substrate or a substrate 11 having an insulating layer on its surface by vapor deposition or sputtering. Patterning of the first superconductor electrode 12 is performed by an etching method or a lift-off method using a normal photoresist process.Next, as shown in FIG. 1(b), a tunnel is formed on the first superconductor electrode 12. A resist mask 13 with an undercut shape is formed in the part that will become the barrier part, and as shown in FIG. 1(C), silicon monoxide (8i0), silicon dioxide, etc. Silicon (S
An insulating layer 14 made of tO, ) or the like is deposited and then lift-on is performed to form a tunnel barrier portion having an opening as shown in FIG. 1(d). The undercut-shaped resist mask 13 can be obtained by applying an organic solvent such as chlorobenzene or bromobenzene before or after exposure in addition to a normal photoresist process. Next, as shown in FIG. 1(e), a tunnel barrier layer 15 having a thickness of several tens of angstroms is formed in the tunnel barrier portion by thermal oxidation or plasma oxidation. Thereafter, as shown in FIG. 1(f), a second superconductor electrode 16 is formed by a vapor deposition method and a lift-off method.

This manufacturing method requires an undercut-shaped resist mask 13 to form the tunnel barrier portion, but the shape of this mask is easily influenced by resist pre-baking conditions, organic solvent liquid temperature, dipping time, etc. In particular, it is very difficult to accurately obtain the dimensions of the lower part of the resist mask 13 that define the effective area of the tunnel barrier section. Another disadvantage is that the tunnel barrier section is contaminated by debris from the insulating layer 14 during sputter cleaning or plasma oxidation of the tunnel barrier section.

(Object of the Invention) An object of the present invention is to provide a method for manufacturing a Josephson junction element that eliminates the above-mentioned conventional drawbacks and can form a tunnel barrier portion with high dimensional accuracy without overetching.

(Structure of the Invention) The structure of the method for manufacturing a Josephson junction element of the present invention is as follows: a first superconducting electrode in a predetermined pattern made of KNb or a Nb compound on a substrate; a tunnel barrier layer on the first superconducting electrode; A first step of successively forming a second superconducting electrode made of PB or a PB gold alloy on the barrier layer, and forming an etching mask at a location on the second superconducting electrode that will become a tunnel barrier portion, and forming an etching mask on the second superconducting electrode. a second step of etching the second superconducting electrode portion at other locations; a third step of forming a first insulator layer on the exposed surfaces of the first and second superconducting electrodes; a fourth step of depositing a second insulating layer so as to fill the insulating layer and the surface of the substrate other than the pattern, and then removing the etching mask; and a portion contacting the second superconducting electrode. a fifth step of depositing a third superconducting electrode on the second insulator layer;
It is characterized by comprising the steps of.

(Example) The present invention will be explained in detail below with reference to the drawings.

FIGS. 2(a) to 2(b) are cross-sectional views of elements showing an embodiment of the present invention in the order of steps. First, as shown in FIG. 2(a), an insulating substrate or a substrate having an insulating layer on the surface
A 3N film of a first superconductor electrode 12 made of Nb or a Nb compound, a tunnel barrier layer 15, and a second superconductor electrode 21 made of PB or a PB gold alloy is formed thereon. These first superconductor electrode 12 and second superconductor electrode 21
The tunnel barrier layer 15 is formed by a vapor deposition method or an evaporation method, and the tunnel barrier layer 15 is formed by oxidizing the surface of the first superconductor electrode by heat or plasma, or by depositing an insulating film or a semiconductor film. Patterning of these three-layer films 12115.21 is performed by an etching method or a lift-off method using a normal resist process. Next, as shown in Figure 21), a resist mask 22 is formed on the second superconductor switch 21 at a location that will become the tunnel barrier, and then ion etching is performed as shown in Figure 2(C). The second superconductor electrode 21 is completely etched using a method. Here, the film thickness of the resist mask 22 is optimized so as not to cause re-deposition on the side walls of the resist mask 22 after etching. Next, as shown in FIG. 2(al), after forming the tenth green body layer 23 on the surface of the second superconductor electrode 12°210 and the second superconductor electrode 12, as shown in FIG.
), SiO, 8i was deposited on the entire surface of the substrate by a film-forming method with good directionality such as vapor deposition or ion beam deposition.
The second insulator Ii consisting of 02? 1i24 is deposited, and the resist mask 22 is lifted on to form a pattern as shown in FIG. 2(f). After this, as shown in FIG.
The third superconductor electrode 25 is formed using the same film forming method and processing method as in case 1. The first insulator layer-23 is the second insulator layer-23.
This is to prevent a short circuit between the first superconductor electrode 22 and the third superconductor electrode 28 that occurs through the pinhole in the insulator layer 24 of the superconductor electrode 28 .

According to this manufacturing method, a rectangular resist mask with good reproducibility can be used when forming the tunnel barrier section,
The second layer is removed from the resist mask 22 by ion etching.
Since the pattern can be transferred to the superconductor electrode 21 with high precision, it is easier to control the dimensions of the tunnel barrier portion compared to a method using the conventional lift-off method. Further, when forming the tunnel barrier layer 15 by sputter cleaning or plasma oxidation, there is no problem that the tunnel barrier portion is contaminated by sputtering of the surrounding insulating layer.

(Concrete example) Next, a specific example of this embodiment will be explained.

First, one surface is thermally oxidized 8 i 0. On a silicon (8,i) substrate (11) coated with 1! Nb film (12) was deposited to a thickness of 2000A at a substrate temperature of 300C using a single beam evaporation method.
to adhere to. Subsequently, in the same apparatus, using an argon (Ar)-0 gas mixture containing 2% oxygen (02), a total pressure of 1X10 Torr and a cathode voltage of -170 V were applied to Nb.
The li surface was plasma plated for 10 minutes, and 20~3υA v
Corner 1j.

A niobium (Nb20g) film (15) is formed. Thereafter, a Pb film (21) is continuously deposited to a thickness of 200 OA at room temperature. A resist mask 22 was formed on this film by a normal photoresist process using a positive type photoresist (AZ135oJ manufactured by Silaplay), and then a parallel plate type sputter etching device was used.

Ar, foyi 3 (CF4) and Pb(2
1).

A first superconductor electrode pattern is formed by sequentially etching Nb/Nb2O5 (15).

Next, a resist mask with a diameter of 1.5 μm and a film thickness of 2000 Å is patterned on the three-layer film 12, 15. (21) is completely removed to form a second superconductor electrode pattern. The etching conditions were an Ar pressure of 2 to 0' Torr, an accelerating voltage of 500 V, and a current density of 0.9 mA/-. The exposed surfaces of the first and stripe 2 superconductor electrodes are then coated with approximately 1.
0. After forming thermally oxidized I'm (23) having a film thickness of Q A, 2000AO8i0 (24) is deposited on this substrate.
is deposited, and the resist mask 22 is lifted on by ultrasonic cleaning in acetone. After the surface of the substrate is tuff-lined with Ar, a third superconductor electrode 25 made of a 30001 Pb film is formed in the same manner as in forming the second superconductor electrode pattern.

In this manufacturing method, when patterning the second superconductor electrode 21, the etching rate ratio of Pb[ to AZ1350J is very large, 13 to 14.

Moreover, since anisotropic etching is possible, almost no change in pattern dimensions of the tunnel barrier portion with respect to the resist mask 22 occurs. In addition, Pb is Nb, which is the first superconductor electrode, and Sin! is the base insulating layer. 13 to 1 respectively for
Because it has a large etching rate ratio of 4,7~8, Pb
Selective etching is possible.

Note that in this specific example, N is used as the first superconductor electrode 12.
Although the case where pb is used as the second and third superconductor electrodes 21.25 has been described, similar results can be obtained with Nb compounds and Pb alloys, respectively. Also, the third
Nb or a Nb compound can also be used for the superconductor electrode 25. In addition to the oxidized layer on the surface of the first superconductor electrode, the tunnel barrier layer 15 includes an insulator layer formed by deposition, a metal layer when the tunnel barrier layer is oxidized,
Semiconductor layers can also be applied. Furthermore, although AZ1350J was used as a mask for forming the tunnel barrier section, other organic resists, inorganic resists, etc. can also be used. Furthermore, in the ion etching method, since Pb has a very high etching rate ratio compared to the electron beam resist, the electron beam resist is effective for processing fine patterns of about 1 μm.

(Effects of the Invention) As explained above, according to the present invention, since the ion etching method with excellent anisotropy and selectivity can be applied to the formation of the tunnel barrier portion, overetching can be ignored.
A Josephson junction element having a tunnel barrier portion with good dimensional accuracy can be manufactured.

[Brief explanation of the drawing]

Fig. 1(a) - (fl is a cross-sectional view explaining the process NLK of the conventional method for manufacturing a dielectric Sefson junction element, Fig. 2(a) -
- Moriki It is a sectional view of an element explaining an example of the present invention in the order of steps. In the figure, 11...Substrate, 12...First superconductor electrode, 13.22...Resist mask, 14
...Insulator layer, 15...Tunnel barrier layer, 16, 21...Second superconductor electrode, 23
...First insulation layer. 24... Second insulator layer, 25... Third superconductor electrode. vJ1 country (rL) Figure Z

Claims (1)

[Claims] A first superconducting electrode of a predetermined pattern made of Nb or a Nb compound is formed on a substrate, a tunnel barrier layer is formed on this first superconducting electrode, and a second superconducting electrode made of Pb or a pb gold alloy is continuously formed on this tunnel barrier layer. a second step of forming an etching mask at a portion of the second superconducting electrode that will become a tunnel barrier portion and etching a portion of the second superconducting electrode other than the mask; ,
a third step of forming a first insulator layer on the exposed surfaces of the first and second superconducting electrodes; and a second step of forming a first insulator layer on the exposed surfaces of the first and second superconducting electrodes, and forming a second insulator layer so as to fill the first insulator layer and the substrate surface other than the pattern. a fourth step of depositing an insulating layer and then removing the etching mask, and depositing a third superconducting electrode on the second insulating layer including a portion that contacts the second superconducting electrode. A method for manufacturing a Josephson junction element, comprising a fifth step.