JPS6022429B2 - How to create integrated devices - Google Patents

How to create integrated devices

Info

Publication number
JPS6022429B2
JPS6022429B2 JP615177A JP615177A JPS6022429B2 JP S6022429 B2 JPS6022429 B2 JP S6022429B2 JP 615177 A JP615177 A JP 615177A JP 615177 A JP615177 A JP 615177A JP S6022429 B2 JPS6022429 B2 JP S6022429B2
Authority
JP
Japan
Prior art keywords
insulating film
integrated device
pattern
etched
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP615177A
Other languages
Japanese (ja)
Other versions
JPS5390831A (en
Inventor
壮太郎 絵所
博史 後閑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP615177A priority Critical patent/JPS6022429B2/en
Publication of JPS5390831A publication Critical patent/JPS5390831A/en
Publication of JPS6022429B2 publication Critical patent/JPS6022429B2/en
Expired legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 本発明は円筒磁区(バブル)素子や半導体集積回路の如
き集積化素子であって段差を解消した集積化素子の作成
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for producing an integrated device such as a cylindrical magnetic domain (bubble) device or a semiconductor integrated circuit, which eliminates the step difference.

区筒滋区素子は通常軟磁性体/・汐ーン(通常パーマロ
ィパターン)をバブル結晶膜(ガーネット等)上に作成
し、磁性体パターンをガイドとしてバブルを移動させる
。バブルを発生,消去させたり、転送径路を変えたり又
は2つ以上の複数の径路にバブルを分割して転送させた
りするためのいわゆる機能部は、磁性体パターンと結晶
の間に配線された導体パターンを含んでいる。導体パタ
ーンに電流を流し、発生する磁界でこれらの機能を行う
。一般に機能部では磁性体パターンの一部は導体パター
ン上にも配督される。このため磁性体パターンは導体パ
ターンの段差の影響を受け、段差が急峻な場合は導体パ
ターンにまたがる磁性体パターンの磁気的な結合が弱く
なり、各機能部の動作特性を低下させる。また半導体等
の集積化素子においても段差が存在し、このような段差
部においては回路の断線が生じうる。このために段差解
消が種々提案されている。円筒磁区素子においては、そ
の導体パターンは導体膜(例えばA↓ AZ−Cu等)
を蒸着後、ポジレジストにより導体パターンを形成する
In the Kuzutsu Shigeru element, a soft magnetic material (usually a permalloy pattern) is usually created on a bubble crystal film (garnet, etc.), and the bubbles are moved using the magnetic material pattern as a guide. The so-called functional part that generates and eliminates bubbles, changes the transfer path, or divides the bubbles into two or more multiple paths and transfers them is a conductor wired between the magnetic material pattern and the crystal. Contains a pattern. These functions are performed by passing current through the conductor pattern and using the generated magnetic field. Generally, in a functional part, a part of the magnetic material pattern is also arranged on the conductive pattern. For this reason, the magnetic material pattern is affected by the step difference in the conductor pattern, and if the step is steep, the magnetic coupling between the magnetic material patterns spanning the conductor pattern becomes weaker, which deteriorates the operating characteristics of each functional section. Furthermore, there are steps in integrated elements such as semiconductors, and circuit breakage may occur at such steps. For this reason, various proposals have been made to eliminate the level difference. In a cylindrical magnetic domain element, the conductor pattern is a conductor film (for example, A↓ AZ-Cu, etc.)
After vapor deposition, a conductor pattern is formed using a positive resist.

即ちパターン部以外の膜をエッチングで除去する。その
後レジステを剥離して絶縁層及び転送用の欧磁性体(例
えばパーマロィ)を蒸着する。したがつて導体の境界で
は、導体の厚さの段差ができ、この段差を軽減するため
に、導体の厚さをできるだけ薄くしたり、その形状をエ
ッチング条件により制御すること等が試みられている。
しかし導体を薄くすることには限界があり、又エッチン
グ条件による形状の制御も本質的な段差の解消とはなっ
ていない。他の方法は、水ガラス等熱硬化性の無機ポリ
マーを、導体パターン形成後スピンコートし段差の7ー
パ一角を小さくする方法である。
That is, the film other than the pattern portion is removed by etching. Thereafter, the resist is peeled off, and an insulating layer and a European magnetic material (for example, Permalloy) for transfer are deposited. Therefore, a step in the thickness of the conductor is created at the boundary between the conductors, and in order to reduce this step, attempts have been made to make the thickness of the conductor as thin as possible or to control its shape by controlling the etching conditions. .
However, there is a limit to making the conductor thinner, and controlling the shape through etching conditions does not essentially eliminate the step difference. Another method is to spin-coat a thermosetting inorganic polymer such as water glass after forming the conductor pattern to reduce the 7-percent corner of the step.

この方法ではテーパ一角は小さくなるが段差の本質的な
解消ではなく、又塗布したポリマーの接着性、基板との
熱膨ヒ張率の差による割れ等の問題がある。さらに他の
方法は導体パターンを絶縁層で埋め込む方法である。例
えば結晶上に絶縁膜を均一に付着させた後、レジストで
マスキングしエッチングにより導体パターン用の溝を堀
り、その後溝の深さに相当する厚さの導体を付着しリフ
トオフによる埋め込まれた導体パターンを作成する方法
が知られている。しかし乍らリフトオフ法の問題点は、
レジストパターンの側壁に膜が付着し、レジスト剥離を
困難にすることがある。そのためレジストを厚く塗布し
たり、ポジ型のレジストを用いてレジストパターン側壁
を急峻にする試みがなされている。本発明の目的は、段
差の無い、円筒磁区素子や半導体集積回路の如き集積化
素子を作成する新規な方法を提供することにある。
Although this method reduces one corner of the taper, it does not essentially eliminate the step difference, and there are also problems such as cracking due to the adhesiveness of the applied polymer and the difference in thermal expansion coefficient with the substrate. Yet another method is to embed the conductive pattern with an insulating layer. For example, after depositing an insulating film uniformly on a crystal, masking it with resist and digging a groove for a conductor pattern by etching, a conductor with a thickness corresponding to the depth of the groove is deposited, and the buried conductor is removed by lift-off. Methods of creating patterns are known. However, the problem with the lift-off method is that
A film may adhere to the sidewalls of the resist pattern, making it difficult to remove the resist. For this reason, attempts have been made to make the side walls of the resist pattern steeper by applying a thicker resist or using a positive resist. SUMMARY OF THE INVENTION An object of the present invention is to provide a new method for producing integrated devices such as cylindrical magnetic domain devices and semiconductor integrated circuits without steps.

すなわち本発明は、集積化素子の作成工程において、レ
ジストパターンをマスクとして被エッチング膜をエッチ
ングし〜前記マスクを剥離することなく続けて絶縁膜を
前記被エッチング膜の厚さ以上に付着し、前記マスクパ
ターンの側壁に付着した絶縁膜をエッチングにより除去
した後、前記マスクパターンを剥離してなる平面化工程
を少くとも1つ含む集積化素子の作成方法である。
That is, in the process of producing an integrated device, the present invention etches a film to be etched using a resist pattern as a mask, then continues to deposit an insulating film to a thickness greater than the thickness of the film to be etched without peeling off the mask, and then etches the film to be etched using a resist pattern as a mask. This method includes at least one planarization step of removing the insulating film attached to the sidewalls of the mask pattern by etching and then peeling off the mask pattern.

本発明を主として円筒滋区素子について図面を参照して
説明する。第1図は通常の方法で作成された導体パター
ンでレジストは剥離されていない。同図亀はバブル結晶
、2はスベーサ一層、3は導体パターン、亀はマスクの
レジストである。導体パターン3の作成には化学エッチ
ング又はイオンミーリング等のドライエッチングが採用
される。マスク4の厚さはlAw以上が望ましい。第2
図は第1図のパターンに蒸着又はスパッタリングにより
絶縁膜5が導体3の厚さ以上に付着された状態を示す。
絶縁膜6はマスク4の側壁にも付着することがある。こ
の側壁の絶縁膜6は次のいずれかの手段により取り除か
れる。1斜め入射ビームによるイオンミーリング法:第
3図に示すように、試料7は入射ビーム方向8から■の
角度で斜いた夕−ンテープル9上に固定,されている。
The present invention will be explained mainly regarding a cylindrical element with reference to the drawings. FIG. 1 shows a conductor pattern created by a conventional method, and the resist has not been peeled off. The tortoise in the figure is a bubble crystal, 2 is a single layer of substrate, 3 is a conductive pattern, and the tortoise is a mask resist. To create the conductor pattern 3, chemical etching or dry etching such as ion milling is used. The thickness of the mask 4 is preferably lAw or more. Second
The figure shows a state in which an insulating film 5 is deposited on the pattern of FIG. 1 by vapor deposition or sputtering to a thickness greater than that of the conductor 3.
The insulating film 6 may also adhere to the sidewalls of the mask 4. The insulating film 6 on this side wall is removed by one of the following methods. 1. Ion milling method using an obliquely incident beam: As shown in FIG. 3, the sample 7 is fixed on an evening table 9 that is inclined at an angle of {circle around (2)} from the incident beam direction 8.

入射角■は45度から80度までの角度に設定されるの
が望ましく、このように斜めからビームを入射するのは
側壁への再付着効果を小さくするためである。なおイオ
ンミーリング法の場合、絶縁膜5の厚さはほぼ導体の厚
さに等しい値が望ましい。2プラズマエッチング法:絶
縁膜として二酸化ケイ素(Si02)を用いた場合、プ
ラズマエッチングが使用できる。
It is desirable that the incident angle (2) be set at an angle between 45 degrees and 80 degrees, and the purpose of making the beam incident obliquely in this way is to reduce the effect of reattachment to the side wall. In the case of the ion milling method, the thickness of the insulating film 5 is preferably approximately equal to the thickness of the conductor. 2 Plasma etching method: When silicon dioxide (Si02) is used as the insulating film, plasma etching can be used.

この時第2図における絶縁膜5の厚さは導体3の厚さに
側壁の絶縁膜6の厚さを足した値に設定することが望ま
しい。即ち側壁の縄孫敦膜6がエッチングされた時絶縁
膜5の厚さは導体3の厚さになるようにする。3化学エ
ッチング:絶縁膜としてアルミナ(A夕203)を用い
た時、熱リン酸液による化学エッチングが可能である。
At this time, it is desirable that the thickness of the insulating film 5 in FIG. 2 be set to the sum of the thickness of the conductor 3 and the thickness of the insulating film 6 on the side wall. That is, the thickness of the insulating film 5 is made to be the same as the thickness of the conductor 3 when the sidewall Atsushi film 6 is etched. 3. Chemical etching: When alumina (A-203) is used as the insulating film, chemical etching with hot phosphoric acid solution is possible.

この場合も側蟹の絶縁膿6が取り除かれた時に、絶縁膜
5の厚さが導体3の厚さになるように絶縁膿5の初期厚
さを設定することが望ましい。以上のいずれかの手段で
側壁の絶縁膜5を取り除いた後リムーバーにより導体上
のレジスト4を剥離し、その後絶縁膜及び転送パターン
用軟磁性体を付着することにより段差を解消した円筒磁
区素子が得られる。また導体パターンが絶縁膜で埋め込
まれているので、レジスト剥離時に導体パターンに傷を
付けることも軽減される。
In this case as well, it is desirable to set the initial thickness of the insulating pus 5 so that the thickness of the insulating film 5 becomes the thickness of the conductor 3 when the lateral crab insulating pus 6 is removed. After removing the insulating film 5 on the side wall by any of the above methods, the resist 4 on the conductor is peeled off with a remover, and then the insulating film and the soft magnetic material for the transfer pattern are attached, thereby producing a cylindrical magnetic domain element that eliminates the step difference. can get. Furthermore, since the conductor pattern is embedded with an insulating film, damage to the conductor pattern when removing the resist is reduced.

以上説明した如く、本発明によれば段差のない集積化素
子が容易に作成され、円筒滋区素子においては動作特性
を向上させ、半導体等の一般集積化素子においては回路
の断線が無くなる効果を有する。
As explained above, according to the present invention, an integrated device without steps can be easily created, the operating characteristics of a cylindrical device can be improved, and the effect of eliminating circuit disconnection can be achieved in general integrated devices such as semiconductors. have

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はしジストマスクにより導体パターンが形成され
た状態を示す断面図、第2図は第1図の構成素子上に絶
縁膜5が付着された状態を示す断面図、第3図は斜め入
射ビームによるイオンミーリソグの方法を示す概略図で
ある。 1・・・バブル結晶、2・・・スベーサー層、3・・・
導体パターン、4・・・レジストマスク、5・・・絶縁
膜、6・・・マスクの側壁に付着した絶縁膜、7・・・
試料、8・・・入射ビーム、9・・・ターンアーフル。 オー図オ2図 才3図
Fig. 1 is a cross-sectional view showing a state in which a conductor pattern is formed using a resist mask, Fig. 2 is a cross-sectional view showing a state in which an insulating film 5 is attached on the component shown in Fig. 1, and Fig. 3 is an oblique view. 1 is a schematic diagram showing a method of ion millilithography using an incident beam; FIG. 1... Bubble crystal, 2... Baser layer, 3...
Conductor pattern, 4... Resist mask, 5... Insulating film, 6... Insulating film attached to side wall of mask, 7...
Sample, 8...Incoming beam, 9...Turn full. O diagram O 2 diagram Sai 3 diagram

Claims (1)

【特許請求の範囲】 1 集積化素子の作成工程において、レジストパターワ
をマスクとして被エツチング膜をエツチングし、前記マ
スクを剥離することなく続けて絶縁膜を前記被エツチン
グ膜の厚さ以上に付着し、前記マスクパターンの側壁に
付着した絶縁膜をエツチングにより除去した後、前記マ
スクパターンを剥離してなる平面化工程を少くとも1つ
含むことを特徴とする集積化素子の作成方法。 2 集積化素子は円筒磁区素子であり、被エツチング膜
は導体膜である特許請求の範囲第1項記載の集積化素子
の作成方法。 3 マスクパターンの側壁に付着した絶縁膜のエツチン
グは斜め入射ビームによるイオンミーリング法で行なう
特許請求の範囲第1項もしくは第2項記載の集積化素子
の作成方法。 4 マスクパターンの側壁に付着した絶縁膜のエツチン
グはプラズマエツチング法で行なう特許請求の範囲第1
項もしくは第2項記載の集積化素子の作成方法。 5 マスクパターンの側壁に付着した絶縁膜のエツチン
グは化学エツチング法で行なう特許請求の範囲第1項も
しくは第2項記載の集積化素子の作成方法。
[Scope of Claims] 1. In the process of producing an integrated device, a film to be etched is etched using a resist patterner as a mask, and an insulating film is continuously deposited to a thickness greater than the thickness of the film to be etched without peeling off the mask. A method for producing an integrated device, comprising at least one planarization step of removing an insulating film attached to a side wall of the mask pattern by etching and then peeling off the mask pattern. 2. The method of manufacturing an integrated device according to claim 1, wherein the integrated device is a cylindrical magnetic domain device, and the film to be etched is a conductive film. 3. The method of manufacturing an integrated device according to claim 1 or 2, wherein etching of the insulating film attached to the side wall of the mask pattern is performed by an ion milling method using an obliquely incident beam. 4. Etching of the insulating film attached to the side wall of the mask pattern is performed by plasma etching method.
A method for producing an integrated device according to item 1 or 2. 5. The method of manufacturing an integrated device according to claim 1 or 2, wherein the insulating film attached to the side wall of the mask pattern is etched by a chemical etching method.
JP615177A 1977-01-21 1977-01-21 How to create integrated devices Expired JPS6022429B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP615177A JPS6022429B2 (en) 1977-01-21 1977-01-21 How to create integrated devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP615177A JPS6022429B2 (en) 1977-01-21 1977-01-21 How to create integrated devices

Publications (2)

Publication Number Publication Date
JPS5390831A JPS5390831A (en) 1978-08-10
JPS6022429B2 true JPS6022429B2 (en) 1985-06-01

Family

ID=11630520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP615177A Expired JPS6022429B2 (en) 1977-01-21 1977-01-21 How to create integrated devices

Country Status (1)

Country Link
JP (1) JPS6022429B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584946A (en) * 1981-06-30 1983-01-12 Nippon Telegr & Teleph Corp <Ntt> Manufacture for buried wiring layer

Also Published As

Publication number Publication date
JPS5390831A (en) 1978-08-10

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