JPS6022820A - Ultrasonic wave delay circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to eliminate the need for adjustment in an ultrasonic delay circuit using an ultrasonic delay line, and to obtain a small, inexpensive delay circuit.

Ultrasonic delay lines are used to delay electrical signals for a certain period of time. Focusing on the fact that the speed of sound waves is approximately 1/100,000 times that of electromagnetic waves, the ultrasonic delay line first converts electrical signals into ultrasonic signals. After obtaining a delay time of several tens of microns to several hundred microns, the signal is converted back into an electrical signal.

FIG. 1 shows the principle of a commonly used ultrasonic delay line. That is, conversion elements 3 and 3' having an electro-mechanical energy conversion function and having electrodes 2a, 2b and 2a', 2b' are attached to the end face of the glass delay medium 1. When an electric signal Ei is applied between the 30 electrodes 2a and 2b, the conversion element 3 mechanically vibrates according to the frequency of the signal, and ultrasonic waves are emitted into the delay medium 1. This ultrasonic wave is reflected many times within the delay medium 1 as shown in the path shown in FIG. , an electrical signal E according to its frequency. is generated between electrodes 2a' and 2b'.

The present invention uses such an ultrasonic delay line to provide a substantially compact ultrasonic delay circuit without adjustment.

Hereinafter, one embodiment of the present invention will be explained with reference to FIGS. 2 and 3.
Explain with mouth and ha. In FIG. 2, reference numeral 4 denotes an ultrasonic delay line, which normally has four terminals, but only the two terminals at the input end are used, and the secondary reflection that returns to this input end is utilized. Of course, the ultrasonic delay line 4 normally provides a predetermined delay time of 1τ from the output end when a signal is applied to the input end. is the reflected wave voltage E(2τ) that appears with a delay time of 2τ. A buffer amplifier 5 such as an emitter follower is connected to the input end of the ultrasonic delay line 4, and the amplification factor of this amplifier 5 is 1.
3, the input of the buffer amplifier 5 (111, l
, line 6.7 is taken out from the output ηIll,
They are designed to have opposite phases.

The output of this circuit is taken out from line 8 where the lines 6 and 7 are joined.The operation of the circuit of the present invention will now be explained.

41. A signal voltage of El is applied to the circuit of the present invention!
+, line 6 shows - as shown in waveform A in Figure 3A.
The voltage of E1 appears. On the other hand, since the amplification factor of the buffer amplifier 5 is 1, the voltage at the input end of the ultrasonic delay line 4, the voltage appearing on the Zunawara line 7, is expressed as jT' in FIG.
< Waveform B of El and waveform C of the secondary unnecessary reflected voltage E (2τ) reflected at the input end of the ultrasonic delay line 4
It is. Then, at output line 8, dl, - of waveform A
E1 and El of waveform B cancel each other out, as shown in FIG.

With the ultrasonic delay circuit of the present invention? In addition, unnecessary second-order reflections of the ultrasonic delay line can be used/stopped, and the ultrasonic delay line itself can be miniaturized. The most significant effect of the present invention is
Since the applied signal pressure E1 is canceled regardless of the human impedance of the ultrasonic delay line, the amount of unnecessary secondary reflection, etc., the delayed signal Nj is canceled without any adjustment. As described above, the present invention allows a small, low-cost delay circuit to be constructed with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a top view for explaining the configuration and operation of an ultrasonic delay line, Fig. 2 is a block diagram showing an embodiment of an ultra-B wave delay 4+j circuit according to the present invention, and Fig. 3 . C is a voltage waveform diagram of the main part of the circuit of FIG. 2. 4...Ultrasonic delay line, 5...] Sofa amplifier. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] An ultrasonic delay circuit characterized in that a Banfa amplifier such as an emitter follower is connected to the input end of an ultrasonic delay line, and the input side and output side of this amplifier are connected with opposite phases and used as an output end.