JPS60231982A - Digital data recording device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital data recording device applied to, for example, a device for storing code data on an optical disc.

[Background technology and its problems]

Storage devices are used that write code data on recording media such as optical disks, magnetic disks, and magnetic tapes.

Code data refers to digital data in which errors are not allowed, and is called code data to distinguish it from digital data that can be modified, such as image data and audio data, and which is allowed to have a certain degree of error. When storing code data on a recording medium, it is necessary to use some method to determine whether or not the code data has been correctly written. If the data has been written correctly, an alternative data area is secured and the data is written there again.

By the way, since optical discs have a high error rate, powerful error correction is performed on read data (read data). Therefore, if you immediately reproduce the written data (write data) and check the write data in the state after error correction, even if the write data is correct, when this write data is read, It is unclear whether it will be read correctly. Tsumashi, not only when writing,
With the addition of errors during reading, there is a possibility that the read data will become unprocessed data.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital data recording device that determines whether write data has been correctly recorded in terms of error correction margin and eliminates the possibility that read data will be erroneous. [Summary of the Invention] This invention, when writing digital data to a recording medium, reads the written data after writing and performs step 2-correction, and the written data is corrected depending on the decoding state at the time of error correction. This digital data recording device detects an error state of data that has been written, and determines whether or not to write data again based on the error state.

[Example 1] In FIG. 1, 1 indicates a disk, and this disk 1 is rotated by a spindle motor 2 at a constant linear velocity. The disk 1 is a substrate made of glass or synthetic resin, the surface of which is coated with a metal layer such as bismuth, and the surface is plated. Disk 1 is
The recording laser beam from the optical head 3 melts and deforms the metal layer to form pits. On the other hand, optical head 3
The pits are read by a reading laser beam from the . The recording laser beam is modulated by write data.

A large number of spiral tracks are formed on the disk 1, and each of the tracks is divided into a plurality of sectors. The address part for each sector is stored in advance on the disk 1.
The presence or absence of pits is recorded in the data field, and depending on the address reproduced from the address section, a digital signal can be recorded in a target sector or a digital signal can be reproduced from a target sector.

The optical head 3 includes an objective lens and a beam splitter.

It has an optical modulator, a light receiving element, etc., and a laser beam is applied to the optical head 3 from a laser generating circuit 4 including a semiconductor laser. Write data is supplied to the laser generating circuit 4 via a drive interface 5, and read data read by the optical head 3 is extracted via the drive interface 5. A power control signal is supplied from the dry fin interface 5 to the laser generating circuit 4 in order to increase the power of the laser beam during writing (recording) compared to when reading (reproducing).

A servo circuit 6 is provided to rotate the disk 1 at a constant linear velocity. Further, the optical head 3 can be threaded in the radial direction of the disk 1 by a thread feeding section T consisting of a linear motor. The optical head 3 is provided with a focus and tracking servo 8 to ensure good focusing and tracking. The reproduction output of the optical head 3 is supplied to the system controller 9 for detection of focusing errors and tracking errors.

This system controller 9 is supplied with commands via the drive interface 5, and the servo circuit 6 is supplied with commands via the drive interface 5.
．． Thread feeding section7. Control signals for the focus and tracking servo 8 are generated from a system controller 9.

The drive interface 5 has the configuration shown in FIG. In FIG. 2, a block coding encoder 21 is shown which converts 8 bits into a 10 bit preferable pattern, that is, a pattern that can reduce DC components.
and write data is formed. Read data from the optical head 3 is supplied to a serial-parallel converter 24 and a PLL 25 via a limiter 23. The output of the serial-parallel converter 24 is supplied to a block coding decoder 26 and a sync/mark detection circuit 27.

PLL 25 Hiro extracts the pit clock from the read data and syncs/syncs this pit clock with the decoder 26.
The signal is supplied to the mark detection circuit 27. The sync/mark detection circuit 2T detects the sync signal and mark (address mark or data mark) in the read data, generates a timing signal synchronized with the read data, and supplies this timing signal to the decoder 26. Furthermore, the drive controller 28 generates a command to the drive system controller 9 and a power control signal to the laser generation circuit 4.

Formation of write data, processing of read data, and formation of data to the drive controller 28 are performed by the error correction code processor 11. This is done by the Batza memory 12 and the system controller 13. Also, interface 1
The host processor 15 and the optical disk recording/reproducing device are coupled via the optical disc storage device 4.

As will be described later, the 11 error correction code processors perform error correction encoding processing during recording, convert this error correction encoded recorded data into write data in a predetermined format, and convert read data into read data during playback. This process performs error correction processing.

The format in one embodiment of the present invention will be described with reference to FIGS. 3 and 4. Figures 3A and 4
As shown in Figure A, one track consists of 20 of (θ~19).
divided into sectors.

Data is written and read in sector units, and data is transferred between the disk drive unit and the host processor 15 in sector units. Each sector includes an address section and a data section, as shown in FIGS. 3B and 4B.

An address section is recorded in advance on the disk by its manufacturer. As shown in FIG. 3C, the address parts have the same address 0. Address 1 and address 2 are recorded and formed in sequence. A 16-byte sync signal is located at the beginning of the address section. This sync signal has a bit pattern of (AA...A) in hexadecimal representation. The third diagram shows the number of bits and bit pattern in the first part of the address field. After this sync signal, there is a 2-byte address mark, Address 0 is located, which consists of a CRC code of 1 and 2 bytes. One byte of this data is encoded by an 8→10 conversion.
It is converted to 10 bits and recorded on the disc.

The sync signal is a pulse signal with a repetition frequency equal to the highest frequency generated by 8→10 conversion, and is used as an ampoule signal for bit synchronization. The address mark has a unique bit pattern (a bit pattern of ccacc in hexadecimal notation) that does not occur in the data recorded in the data portion and is difficult to get out of bit synchronization. This address mark expansion is used for word synchronization. The track number and sector number are the addresses of the track and sector, and a CRC code (a 2-detection code using a cyclic code) is added to detect errors in both. Data IDO for identifying address O is inserted in the sector number.

A 3-byte sync signal is interposed between address 0 and address 1, and between address 1 and address 2, respectively. This sync signal is a pulse signal having the same frequency as the sync signal at the beginning of the address section, and prevents bit synchronization from being lost.

Recording the same address three times in the address field is a measure against errors. That is, among the reproduced addresses, the address that is determined to be error-free as a result of error detection of the CRC code is considered valid. However, when recording addresses in triplicate, a sync signal is inserted at the boundary between two addresses, which not only facilitates bit synchronization but also prevents both addresses from being in error due to burst errors that occur during disk playback. This will prevent it from happening. In this embodiment, the length of the burst error that occurs during disk playback rarely exceeds 3 bytes (30 bits on the disk), so the length of the sync signal inserted between two addresses is set to 3 bytes (30 bits on the disk). I have a part-time job. In this way, even if a burst error occurs at the boundary between two addresses, the error remains in one address and the sync signal, and it is possible to prevent both addresses from becoming errors. Further, by repeatedly inserting the address mark a plurality of times, the reliability of word synchronization can be improved. Once the first address mark is detected, the second and subsequent address marks will generate a correct window.

Further, a gap is provided between the end of the address section, that is, the rear end of the CRC code at address 2, and the next data section. This gap is provided to compensate for the rise and time from when a target address is detected until a laser beam with sufficient power for recording is generated.

For example, the length of the gap between the address field and the data field is 10 bytes.

FIG. 4C shows the format of the data section, and the fourth diagram shows the number of bytes and bit pattern of the leading part of this data section. The data portion includes error correction encoded data, a sync signal, and a data mark. A 16-byte sync signal is inserted at the beginning of the data portion. This sync signal is a pulse signal with a repetition frequency equal to the highest frequency generated by 8→10 conversion, and is used to pull in bit synchronization. A 2-byte prefix data mark is inserted after this sync signal. This prefix data mark has a unique bit pattern (1
It is 330 CF in hexadecimal notation and is used for data synchronization. Thirty-two sets from set 0 to set 31 are inserted after this prefix data mark. Each set consists of a 2-byte data mark with a unique bit pattern (33C33 in hexadecimal notation) and 96 bytes of data.

One sector includes 1.5 bytes of data.

The data of one sector is encoded using the CIRC code, and interleaving is completed within one sector. Similar to the address mark mentioned above, multiple data marks are recorded in the data section within one sector, and even if word synchronization is lost midway through, these data marks will invalidate subsequent data. is prevented. A gap having a length of, for example, 30 bytes is provided at the last position of the data portion of each sector. The purpose of this gap between sectors is to prevent the length of a sector from becoming longer than specified due to uneven rotation of the disk, eccentricity of the disk, etc., and to prevent the sector from overlapping the beginning of the next sector.

In this embodiment described above, the data processing during recording and playback is illustrated by the sequence and corresponding block diagram of FIG. 5.

When recording is controlled by the system controller 13,
A write command is sent from the host processor 15 to the system controller 13 through the interface 14, and data transfer is started.

A scramble/unscramble circuit 31 performs a scrambling operation to spread and record data on a disk during recording.A 02 encoder/decoder 32 performs encoding using a 02 code, for example, a (20°16) Leadon-Romon code during recording. The interleave/dinterleave circuit 33 performs an interleaving operation during recording, and the interleaved data and redundant data spanning C2 are
The signal is supplied to an encoder/decoder 34. The C1 encoder/decoder 34 encodes 01 codes, for example (24,
20)! Performs J-de Solomon code encoding. Furthermore,
The output of the C1 encoder/decoder 34 is supplied to a one symbol delay circuit 35 for distributing the data. The output of this l-symbol delay circuit 35 is passed through a 5-io modulation/demodulation circuit 36 and a formatting/deformatting circuit 37, and is recorded on the optical disc 1 in the signal format shown in FIGS. 3 and 4.

During reproduction, a read command is sent from the host processor 15 to the system controller 13, and the reproduced data is processed in the reverse order as described above. The Cl encoder/decoder 34 decodes the C1 code; detects burst errors and corrects random errors.

The C2 encoder/tecoder 32 performs burst error correction. Interleave/dinterleave circuit 3
No. 3 performs a dinterleave operation to return the data arrangement to that of I during reproduction, thereby dispersing burst errors.

FIG. 6 shows a specific configuration of the error correction code processor 11. In FIG. 6, 40 is a sequencer that controls the entire operation of the error correction code processor 11. Error detection is performed by inputting data (including redundant codes) from the data bus 42 to the syndrome generation circuit 41, generating a syndrome, and transmitting this syndrome to the sequencer 40.
This is done by supplying In this case, in addition to determining the presence or absence of an error, it is also necessary to determine whether there is a 1-symbol error, 2-symbol error, or 3 or more symbols. The claimed error location for which circuit 43 is provided is stored in error location register 44 .

-1-Error correction U, reads the symbol indicated by the error location register 44 from the buffer memory 12;
This is done in the syndrome generation circuit 41. Further, interleaving and dinterleaving are realized by controlling the address of the buffer memory 12 by the address generation circuit 45. During recording, the sequencer 40 and the Galois field arithmetic circuit 43 encode the C1 code and the C2 code.

During reproduction, the error detection information of the C1 code is used as a C1 pointer to perform reliable error correction when decoding the C2 code. Boink number register 4
Reference numeral 6 includes a counter for counting pointers and a register for storing the counted value. C1 code and C2
An example of a decoding method using both codes will be described. First, the C1 code is decoded as follows.

Let the syndrome calculated from the playback data be SI, and C
2. Let PI be the pointer passed for decoding.

(1) Syndrome S! When there is no error, no correction is performed and (pt=o) is set.

(2) When a single error is detected from syndrome S1 1 Correct the single error and set (Pt=0).

(3) When a double error is detected from syndrome S1, the double error is corrected and set (Px=1).

(4) When triple or more errors are detected from syndrome S1, no correction is made (p1=1).

That is, in C1 decoding, it is performed at second gear error stop, and at that time, there is a risk of erroneous correction, so (Px = 1)
Then check again with C2 decoding.

C2 decoding will be explained next. Ss is the syndrome calculated during C2 decoding, Pl is the pointer information formed during C1 decoding, and N(Pt) is the pointer P1 (D number,
t, (pt = Ss) is a pointer P1 of 1 that coincides with the error location calculated from syndrome s2
The final outside flag is the number + P2.

(1) When it is determined from syndrome s2 that there is no error, no correction is made and (P2=O) is set.

(2) When a single error is detected from syndrome S2, perform single error correction and set (p,=o).

(3) When double engineering 2- is detected from syndrome S2 (I) N(Pl)≦4 and L(PI = 82)
= 2, double error correction is performed and (P2 = 0
).

(n) N(Pl)≦3 and L(Pt = St)
= 1 or tN(P+)≦2 and L(Pl=32)
When Pz = 0, no correction is made and (Pz = 1).

01l) In cases other than (1) and (II), no correction is made and Pi is set as P2.

(4) When triple or more errors are detected from syndrome S2 (IN(pt)≦2, no correction is performed and (P
+=i).

■) In cases other than the above, do not make any corrections and use P1 as is! shall be.

In this embodiment, when writing data, on the writing edge,
The written data is read to perform the above-mentioned error prevention and determine the error state.

The state after error correction is the number of code sequences EPTR for which the pointer PR was set during C1 decoding, the number ECWI of code sequences for which 1 symbol error was corrected during C2 decoding, and 2 when C2 was obtained.
Number of code sequences that corrected symbol E2-ECW2, C2
At the time of decoding, the determination is made using four status signals of the number of code sequences ECEH that cannot be error corrected.

These four status signal lines are stored in the decode status register 4T. In this embodiment, the code sequence of the C1 code consists of 24 symbols, and the code sequence of the C2 code consists of 20 symbols. The above-mentioned EPTR indicates the state of error distribution, and ECWI and ECW2°ECER indicate the number of error symbols at the time of C10. As mentioned above, C1
The C2 code is used for burst error detection and random error correction, and the C2 code is used for burst error correction.
The number of error symbols when decoding a C2 code greatly contributes to the possibility of correction, as the number of error symbols is constant depending on the code. therefore,
The number of errors when decoding a C2 code is expressed by the following equation.

ECW1+2ECW2+3ECER・・・・・・・・・
(1) In the above equation, the fact that coefficients are added to each of ECW2 and ECER indicates that ECW2 has a 2-symbol error and ECER has a probability of a 3-symbol error.

On the other hand, the interleaving depth in the C2 code is that 49 symbols or 97 symbols appear alternately, and this sum is the C2 code.
Compatible with 6 code sequences of 1 code.

That is, if the number of errors when decoding the C1 code is 6 or less,
Errors are always corrected using the C2 code.

When decoding the C1 code, the pointer is set to 1 when an error of 2 or more symbols occurs, so the EPTR
If it exceeds 6, there is a high possibility that the error cannot be corrected even with the C2 code. Therefore, the boundary condition of EPTR is set to (EPTR=F).

The boundary conditions regarding the number of errors in the C2 signal expressed by the above equation (1) are determined as follows from the randomness and burst nature of the C2- signal.

The most urgent condition in which random error cannot be corrected is when there are three CI code sequences each containing 3 symbol errors, and three symbols out of these nine error symbols are included in the same 02 code sequence. be.

At this time, it becomes impossible to correct the nine error symbols. As a result, C1 caused a 3-symbol error.
In order to allow up to one code sequence and reduce the risk of errors during C2 decoding, (ECWI≦3.EPTR≦6
) as a boundary or matter. Regarding burst errors, Mori, C2
Since the code sequence has a length of 20 symbols, the value of equation (1) is divided into numerical values of 20, 40° and 60, and it is assumed that burst errors are small when the value is 10 or less.

Taking into account the above points, FIG. 7 shows how to determine the error type and margin from the error status stored in the decoding status register 47.

A determination based on this error state is made in the system controller 13, and the determination result is transmitted to the host processor 15 via the interface 14. The host processor 15 determines whether or not to write again, and if necessary, issues a write command to a replacement sector.

The system controller 13 may decide whether to perform this rewriting. Further, FIG. 7 shows a judgment that takes into consideration when recording data that can be interpolated, such as video data or audio data that is not code data.

〔Effect of the invention〕

According to the present invention, when write data is recorded, it is checked whether the recording was performed correctly with respect to the error correction margin, so that the possibility that read data becomes error data is reliably eliminated when read data. I can do it.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an embodiment of this invention, Figure 2 is a block diagram of a part of the configuration of an embodiment of this invention, and Figure 3 is a block diagram of the data format of an embodiment of this invention. FIG. 4 is a route map showing the structure of the address section; FIG. 4 is a route map showing the format of an embodiment of the present invention, particularly the structure of the data section; FIG. 5 is an error correction encoding and decoding diagram of an embodiment of the present invention. FIG. 6 is a block diagram showing the configuration of an example of an encoder/decoder for a correction code, and FIG. 7 is a route diagram used to explain the operation of an embodiment of the present invention. 1... Disc, 3... Optical head, 4
... Laser generation circuit, 5 ... Drive interface, 11 ... Error correction code processor, 12 ... Buffer memory, 13.
...System controller, 15 ... Host processor, 47 ... Decode status register. Agent Masatomo Sugiura

Claims (1)

[Claims] When writing digital data to a recording medium, the written data is read after writing and error correction is performed, and the error state of the written data is detected based on the code state at the time of error correction. A digital data recording device that determines whether or not to write again from this error state.