JPS60233833A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60233833A JPS60233833A JP59087909A JP8790984A JPS60233833A JP S60233833 A JPS60233833 A JP S60233833A JP 59087909 A JP59087909 A JP 59087909A JP 8790984 A JP8790984 A JP 8790984A JP S60233833 A JPS60233833 A JP S60233833A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- solder
- solder material
- semiconductor pellet
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
- H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07336—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
- H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/331—Shapes of die-attach connectors
- H10W72/334—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
- H10W72/387—Flow barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置、竹に半導体ペレットと電極の鑞付
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device and a structure in which semiconductor pellets and electrodes are brazed to bamboo.
第1図は従来の半導体装置の電極鑞付構造を示しておシ
、機材に接続するための金属4を主表面に配置した半導
体ペレット3を鑞材2,5を介して、ベース1、電極6
で挾んだ構造である。FIG. 1 shows a conventional electrode brazing structure of a semiconductor device. A semiconductor pellet 3 having a metal 4 arranged on its main surface for connection to equipment is connected to a base 1 and an electrode through soldering materials 2 and 5. 6
It has a structure sandwiched between.
半導体装置の場合、実動作時の温度変化により、各部材
間の熱膨張係数の差によシ熱応力が発生する。特に鑞材
2,5の劣化の原因となるのは、変化する繰り返しのせ
ん断芯力と考えられる。In the case of semiconductor devices, thermal stress is generated due to differences in thermal expansion coefficients between members due to temperature changes during actual operation. In particular, it is thought that the cause of the deterioration of the solder materials 2 and 5 is the repeated shear core force that changes.
第1図の半導体装置を実動作させる時には、この半導体
装置に流れる電流の変動により半導体ペレット3で発生
する熱損失の変動を伴い、各部材の温度が変動する。特
に、前記半導体装置を用いた回路の負荷が大きく変動す
る場合には温度の変動幅も大きくなる。従って、鑞材2
,5はせん断芯力を負担し、半導体ペレット3は、引張
り、圧縮応力を負担する事になる。When the semiconductor device shown in FIG. 1 is actually operated, the temperature of each member fluctuates as the heat loss generated in the semiconductor pellet 3 fluctuates due to fluctuations in the current flowing through the semiconductor device. In particular, when the load of a circuit using the semiconductor device fluctuates greatly, the range of temperature fluctuation also increases. Therefore, the brazing material 2
, 5 bear the shear core force, and the semiconductor pellet 3 bears the tensile and compressive stresses.
今、半導体ペレット3の熱膨張係数をα11縦弾性係数
E1、厚みをhl、電極6の熱膨張係数をα2、縦弾性
係数をE2、厚みをh2、鑞材5の横弾性係数をG、厚
みをh3とし、接着部の最大直径を2xoとすれば、せ
ん断遅れの理論を適用すると、鑞材5内のせん断芯力τ
(支)は、温度変動幅をΔTとして近似的に次式となる
。Now, the coefficient of thermal expansion of the semiconductor pellet 3 is α11, the coefficient of longitudinal elasticity E1, the thickness is hl, the coefficient of thermal expansion of the electrode 6 is α2, the modulus of longitudinal elasticity is E2, the thickness is h2, the modulus of transverse elasticity of the solder material 5 is G, the thickness is If h3 is the maximum diameter of the bonded part and 2xo, then applying the shear lag theory, the shear core force τ in the solder material 5 is
(support) is approximated by the following equation, where the temperature fluctuation range is ΔT.
但し、kについては次式となる。However, regarding k, it becomes the following formula.
(1)(2)式で、τ(X)の値が鑞材5の弾性限界τ
0を越えた場合には、τ(幻Στ0となシ、せん断歪γ
は半導体ペレットの中心からの距離Xの2次式に近似で
き次式となる。In equations (1) and (2), the value of τ(X) is the elastic limit τ of the solder material 5.
When it exceeds 0, τ(phantom Στ0 and nashi, shear strain γ
can be approximated to a quadratic equation of the distance X from the center of the semiconductor pellet, and becomes the following equation.
r=a x2+b x+c −(3)
但しa、b、cは、各部材の寸法および物性値よシ決ま
る定数であシ、a>Oである。r=a x2+b x+c - (3) However, a, b, and c are constants determined by the dimensions and physical property values of each member, and a>O.
(1)(2)式でαs =3.5X10−’、α2 =
8 X 10−’ r El ””11X103Kp/
++i 、&=30X103Kp/+i、C+=0.0
78に9Δ−、h1=Q、3閣、 h3=Q、5間、
h” =0.05咽、0.1調。In equations (1) and (2), αs = 3.5X10-', α2 =
8 X 10-' r El ""11X103Kp/
++i, &=30X103Kp/+i, C+=0.0
78 to 9Δ-, h1=Q, 3 cabinets, h3=Q, 5 spaces,
h” = 0.05 throat, 0.1 tone.
ΔT=1000について計算したものを第2図に示す。The calculation for ΔT=1000 is shown in FIG.
第2図より、ぜん断応力τに端の方、つまり、x =
x oにおいて最大となり、中心に近い所では、急激に
零に近づく事がわかる。更に鑞材5の厚みh3が小さい
方がτの最大値が大きくなる。From Fig. 2, we can see that the shear stress τ is towards the end, that is, x =
It can be seen that it reaches a maximum at x o and rapidly approaches zero near the center. Furthermore, the smaller the thickness h3 of the solder material 5, the larger the maximum value of τ.
また、温度変動の繰シ返し回数の耐量Nとしては次式で
成立する事が、別の実験よシ判っでいる。Further, it has been found from another experiment that the following equation holds true as the withstand capacity N for the number of repetitions of temperature fluctuation.
但し、C1は鑞材の種類で決まる定数である。However, C1 is a constant determined by the type of solder material.
(4)式と第2図よシ、繰シ返し耐量Nを向上させるた
めに、従来例として第3図に示す電極鑞付構造がある。According to equation (4) and FIG. 2, there is an electrode brazing structure shown in FIG. 3 as a conventional example in order to improve the repeatability N.
すなわち、鑞材5と接着する電極6の断面形状を凸球面
形にする事により、せん断力τの大きくなる端部での鑞
材5の厚さを大きくする。これによシ、せん断応力τの
最大の値τ□0を小さくする構造である。That is, by making the cross-sectional shape of the electrode 6 which is bonded to the solder material 5 into a convex spherical shape, the thickness of the solder material 5 is increased at the end where the shear force τ is large. This structure reduces the maximum value τ□0 of the shear stress τ.
しかし、第3図の構造においては、半導体ペレット3の
周囲の録材厚が次第に厚くなるため、半導体ペレット3
で発生する熱量が放熱しにくいという欠点がある。つま
シ、一般的な例として、電極6に銅を用い、鑞材にはん
だを用いた場合、はんだの熱伝導率は銅の1/10であ
シ、半導体ペレット3の周囲のはんだで熱抵抗が大きく
なる。However, in the structure shown in FIG. 3, since the thickness of the recording material around the semiconductor pellet 3 gradually increases, the semiconductor pellet 3
The disadvantage is that the amount of heat generated is difficult to dissipate. As a general example, if copper is used for the electrode 6 and solder is used for the solder material, the thermal conductivity of the solder is 1/10 that of copper, and the thermal resistance of the solder around the semiconductor pellet 3 is becomes larger.
従って、半導体装置の放熱性の低下となって現われ、半
導体装置の動作時の温度が上昇し易くなる。Therefore, the heat dissipation performance of the semiconductor device is reduced, and the temperature of the semiconductor device tends to rise during operation.
半導体装置は、動作時の最高保証温度が決められている
事が多く、放熱性の低下は大きな電力を消費できないと
いう欠点になる。Semiconductor devices often have a specified maximum guaranteed temperature during operation, and a reduction in heat dissipation is a drawback in that large amounts of power cannot be consumed.
また、電極6の凸球面形にする加工は、実際においては
、困難さを伴うという点も第3図の構造の実現性を乏し
くしている。Furthermore, the fact that machining the electrode 6 into a convex spherical shape is difficult in practice makes it difficult to realize the structure shown in FIG.
また、第4図も従来例であるが、電極6の半導体ペレッ
ト3に接続する面に垂直な断面の横方向寸法が、半導体
ペレット3のそれよシ小さく、鑞材5を電極6の側面に
もシ上げた構造である。この構造の場合、金属6の半導
体ペレット3に対向する面が平坦である事から第3図の
場合の放熱性の悪い点を改良している。Furthermore, although FIG. 4 is also a conventional example, the lateral dimension of the cross section perpendicular to the surface of the electrode 6 connected to the semiconductor pellet 3 is smaller than that of the semiconductor pellet 3, and the solder material 5 is placed on the side surface of the electrode 6. It also has a raised structure. In this structure, since the surface of the metal 6 facing the semiconductor pellet 3 is flat, the poor heat dissipation of the case shown in FIG. 3 is improved.
しかし、この図の構造では、接着の際、外部よシまき込
む空気を鑞材内部に封じ込め空孔となシやすい。この空
孔には、応力集中が起こシ温度変動の繰シ返し回数の耐
量Nを小さくする事が多く、また内部に封じ込められた
空気の非常に低い熱伝導率のため放熱性も劣るという点
が大きな欠点となっていた。However, with the structure shown in this figure, during bonding, air that enters from the outside is trapped inside the solder material and tends to form voids. Stress concentration occurs in these pores, which often reduces the withstand capacity N for the number of repetitions of temperature fluctuations, and heat dissipation is also poor due to the very low thermal conductivity of the air sealed inside. was a major drawback.
更に第5図も従来例である。図から解かる様に、電極6
の端部に段差を設ける事により、第3図。Furthermore, FIG. 5 is also a conventional example. As can be seen from the figure, electrode 6
By providing a step at the end of Fig. 3.
4図と同様、半導体ペレット3の端部の舷材厚を厚くし
ている。第5図の場合、半導体ペレット3の端部7へは
んだをもり上げない事が目的であるため、半導体装置の
実装動作時の繰ヤ返し温度変化に耐えるという点からは
、下記の欠点がある。As in FIG. 4, the thickness of the sheath material at the end of the semiconductor pellet 3 is increased. In the case of Fig. 5, the purpose is to prevent solder from rising to the end 7 of the semiconductor pellet 3, so there are the following drawbacks in terms of withstanding repeated temperature changes during the mounting operation of semiconductor devices. .
即ち、第4図と同様空孔が鑞材内部に封じ込まれる点で
鑞付の際、半導体ペレット3の中央部で発生した穴孔が
鑞材と共に周辺部に流れ出る際、電極6の段差部8に溜
りやすい。空孔の存在は前記した様に応力集中が起こる
。That is, as shown in FIG. 4, the holes are sealed inside the solder material, and when the holes generated in the center of the semiconductor pellet 3 flow out to the periphery together with the solder material during brazing, the stepped portion of the electrode 6 It tends to accumulate at 8. The presence of pores causes stress concentration as described above.
本発明は、前記した従来技術の欠点をなくし、温度変動
の繰シ返し回数の耐量Nを大きくすると共に、放熱性の
良好な電極鑞付構造を有する半導体装置を提供すること
を目的とするものである。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, increase the withstand capacity N for the number of repetitions of temperature fluctuations, and provide a semiconductor device having an electrode brazing structure with good heat dissipation. It is.
上記目的を達成する本発明の特徴とするところは、電極
が半導体ペレットの主表面に対向する平面と該主表面か
ら遠ざかるに従って該主表面と平行な方向での電極の断
面積を大きくする#I斜斜面面有し、鑞材が上記主表面
と平面および傾斜側面の間に設けられていることにある
。The present invention is characterized in that the cross-sectional area of the electrode increases in the plane facing the main surface of the semiconductor pellet and in the direction parallel to the main surface as the electrode moves away from the main surface. The main surface has a sloped surface, and a brazing material is provided between the main surface and the flat and sloped side surfaces.
第6図に本発明の一実施例を示す。 FIG. 6 shows an embodiment of the present invention.
電極6の半導体ペレット3に接続する面に垂直な断面の
形状が台形であムかつこの底辺の長さが鑞材5に接続す
るための半導体ペレット3に被覆した金属4の寸法より
小さい構造である。The cross section of the electrode 6 perpendicular to the surface connected to the semiconductor pellet 3 has a trapezoidal shape, and the length of the base thereof is smaller than the dimension of the metal 4 coated on the semiconductor pellet 3 for connecting to the solder material 5. be.
前記した様に、半導体ペレット3の周囲に接続する鑞材
の厚さが中央部に比べ厚い事から、くり返しの温度変化
に対する耐量を向上させ、半導体ペレット3の中央部に
接続する鑞材の厚みが薄い事から、鑞材5での熱抵抗を
減少させ1いる。また、本装置の製造の際、鑞材5は、
半導体ペレット3の中央部から周囲に向かって流れる事
になり、流れ出た鑞材5は、電極6の底辺部の高さまで
傾斜側面をもり上がろうとするため、空孔の発生が抑え
られる。As mentioned above, since the thickness of the solder material connected to the periphery of the semiconductor pellet 3 is thicker than that at the center, the resistance against repeated temperature changes is improved, and the thickness of the solder material connected to the center portion of the semiconductor pellet 3 is increased. Since it is thin, the thermal resistance of the solder material 5 is reduced. In addition, when manufacturing this device, the solder material 5 is
The solder material 5 flows from the center of the semiconductor pellet 3 toward the periphery, and since the flowing solder material 5 tends to rise up the inclined side surface to the height of the bottom of the electrode 6, the generation of voids is suppressed.
本発明の第3図、第4図に示す従来列に対して優れてい
る点は第3図に対しては、半導体ペレット3の中央部に
接続する鑞材量が均一でおる事より、半導体ペレット3
で発生する熱が、電極全面に均一に伝わりやすい事。第
4図に対して、半導体ペレット3の周囲に接続する鑞材
が、もり上がり、鑞材量が厚くなるため(2)式よりこ
の部分での鑞材のせん断心力が小さくなる点である。The advantage of the present invention over the conventional rows shown in FIGS. 3 and 4 is that in the case of FIG. pellet 3
The heat generated by the electrode is easily transmitted evenly over the entire surface of the electrode. In contrast to FIG. 4, the solder material connected to the periphery of the semiconductor pellet 3 bulges up and the amount of the solder material becomes thicker, so the shear center force of the solder material in this part becomes smaller according to equation (2).
更に、第3.4.6図3つの構造の半導体装置について
、〈シ返しの温度変化の回数nと鑞材はかれ率の関係の
計算結果を第7図に示す。ここで、Xiは、半導体ペレ
ットの凛材接攬部の周囲を原点として、測定した鑞材の
き裂の寸法を示す。この計算において、鑞材5の体積は
3者共等しい条件で計算している。Furthermore, FIG. 7 shows the calculation results of the relationship between the number n of temperature changes in turning and the peeling rate of the solder material for the semiconductor devices having the three structures shown in FIGS. 3.4.6. Here, Xi represents the dimension of a crack in the solder material measured with the periphery of the solder material contacting part of the semiconductor pellet as the origin. In this calculation, the volume of the solder material 5 is calculated under the same conditions for all three.
第7図において、まず第4図の曲線は第6図のそれを左
側に平行移動した形になっている。この原因は、鑞材劣
化の初期において周辺部よシ@泌が入るが、この際、第
6図の場合、電極6の断面形状が台形のため、第4図に
比べ周辺部の鑞材量が多くなる。この周辺部における鑞
材量の差が、第7図における鑞材はかれ初期値の差であ
る。鑞材のき裂が中央部に向って進行し鑞材量が均一に
領域に入ると両者の構造で、き裂進行速度に差がなくな
る。In FIG. 7, first, the curve in FIG. 4 is obtained by translating the curve in FIG. 6 to the left. The reason for this is that at the beginning of the deterioration of the solder material, the surrounding area leaks, and at this time, in the case of Fig. 6, the cross-sectional shape of the electrode 6 is trapezoidal, so the amount of solder material in the surrounding area is smaller than that in Fig. 4. will increase. The difference in the amount of solder material in this peripheral area is the difference in the initial value of the solder material in FIG. 7. If the crack in the solder material advances toward the center and the amount of solder material is uniform in the area, there will be no difference in the crack growth speed between the two structures.
第3図の構造では、鑞材量が半導体ペレット3の中央部
に向って漸次減少するため、き裂進行の速度は、温度変
化のくり返し数nと共に加速的に増大する。In the structure shown in FIG. 3, since the amount of solder material gradually decreases toward the center of the semiconductor pellet 3, the speed of crack propagation increases at an accelerating rate with the number n of repetitions of temperature change.
また、第5図の場合は、鑞材き裂の開始点である周辺部
においても、電極用金属6がある厚みを持っているため
に、第6図の周辺部の厚みが漸小した電極用金属6に比
べて熱応力が大きくなるのは明白である。即ち、第5図
は第6図に比べ周辺部の熱応力が大きくなる事により、
き裂発生の開始時間が早まる事になり、第7図の関係で
は、第6図の曲線に比べ、小さなnでき裂が開始する事
になる。In addition, in the case of Fig. 5, since the electrode metal 6 has a certain thickness even at the peripheral part, which is the starting point of the solder metal crack, the electrode metal 6 has a certain thickness at the peripheral part as shown in Fig. 6. It is obvious that the thermal stress is greater than that of the metal 6. In other words, in Figure 5, the thermal stress in the peripheral area is larger than in Figure 6, so
This means that the crack initiation time is earlier, and in the relationship shown in FIG. 7, the crack starts at a smaller n than the curve shown in FIG. 6.
以上説明したように、本発明によれば温度変動の繰り返
し回数の耐量Nが大きく、放熱性の良好な電極鑞付構造
を備えた半導体装置を得ることができる。As described above, according to the present invention, it is possible to obtain a semiconductor device having an electrode brazing structure with a large withstand capacity N for the number of repetitions of temperature fluctuations and good heat dissipation.
第1図は従来の半導体装置を示す断面図、第2図は第1
図に示す半導体装置におけるはんだに加わるせん断心力
をはんだの位置との関係を示す図、第3図〜第5図はそ
れぞれ他の従来の半導体装置を示す断面図、第6図は本
発明の一実施例を示す断面図、第7図は第6図の半導体
装置におけるはんだの耐量をはんだの位置との関係で示
す図である。
1・・・ペース、2,5・・・鑞材、3・・・半導体ペ
レット、4・・・金属、6・・・電極。
茅4図
茅 !5 図
第1頁の続き
@発明者藤井 正巳Figure 1 is a cross-sectional view of a conventional semiconductor device, and Figure 2 is a cross-sectional view of a conventional semiconductor device.
3 to 5 are cross-sectional views showing other conventional semiconductor devices, and FIG. FIG. 7, a cross-sectional view showing an embodiment, is a diagram showing the solder tolerance in the semiconductor device of FIG. 6 in relation to the position of the solder. DESCRIPTION OF SYMBOLS 1...Pace, 2,5...Brazing material, 3...Semiconductor pellet, 4...Metal, 6...Electrode. Kaya 4 illustrations! 5 Continuation of figure 1 page @ inventor Masami Fujii
Claims (1)
記−主表面に対向する平面と一生表面から遠ざかるに従
って一生表面と平行な方向での電極の断面積を大きくす
る傾斜側面を有しておシ、鑞材が上記−主表面と平面お
よび傾斜側面の間に設けられていることを特徴とする半
導体装置。1. The electrode to be brazed to the surface of the semiconductor pellet has a plane facing the main surface and an inclined side surface that increases the cross-sectional area of the electrode in a direction parallel to the surface as it moves away from the surface. A semiconductor device characterized in that a brazing material is provided between the main surface and the flat and inclined side surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59087909A JPS60233833A (en) | 1984-05-02 | 1984-05-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59087909A JPS60233833A (en) | 1984-05-02 | 1984-05-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60233833A true JPS60233833A (en) | 1985-11-20 |
Family
ID=13928041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59087909A Pending JPS60233833A (en) | 1984-05-02 | 1984-05-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60233833A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
| US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
-
1984
- 1984-05-02 JP JP59087909A patent/JPS60233833A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
| US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
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