JPS60254631A - Semiconductor ic - Google Patents

Abstract

PURPOSE:To prevent the generation of a useless transistor by increasing the effective gate width by a method wherein N-channel transistors are arranged in parallel in such an arrangement that the channels are disposed in one direction. CONSTITUTION:P-channel transistors QP1 and QP2 and N-channel transistors QN1 and QN2 have independent gate electrodes GP1 and GP2, GN1 and GN2, respectively. Besides, the effective gate width Wa' of the P-channel transistor QP1 is larger than the width Wb' of the P-channel transistor QP2, whereas the effective gate width Wa of the N-channel transistor QN1 is larger than the width Wb of the N-channel transistor QN2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of a semiconductor integrated circuit (LSI) manufactured by applying a mask slicing method.

[Conventional technology]

The mask slicing method removes bulk parts of the transistor, such as p-well diffusion vJ region, n-well diffusion region, gate oxide film, polycrystalline silicon film, selective oxide film, channel stopper, n-type or p-type diffusion region, etc. A wafer created by applying a prescribed pattern (mask) is prepared in advance, and when the user shows a specific circuit configuration,
This method completes an LSI that meets the needs of a specific user by performing wafer processing after wiring creation using a specific mask pattern designed to achieve this.

With this method, a specific LSI is created by only processing after wiring creation, so the product can be completed in a shorter period of time compared to a fully custom LSI, and there is no need to create a special pattern (mask) to form the bulk part. 1. Manufacturing costs are low because there is no Additionally, since the transistor pattern is fixed, there are advantages such as less hearing.

Incidentally, as the integration of LSIs progresses, more and more users are demanding LSIs that incorporate all the functions of one system on one chip.

In such cases, rather than configuring one chip with only random logic circuits like a conventional gate array, it is preferable to use RAM (random access
memory) and ROM (read only me
At the same time, it becomes necessary to install a memory circuit such as memory (Mory).

Conventional so-called CMOS mask slices, also called gate arrays, are fabricated so that their bulk portions are convenient for constructing random logic circuits. Although it is possible to incorporate memory circuits into such gate arrays, it can only be achieved with significantly reduced integration density.

Further, a transmission gate circuit, which is often used when a clock synchronization method is used to control logic circuits, cannot be efficiently realized.

FIG. 13 is a plan view of a main part showing a general LSI pattern formed by applying the mask slicing method.

As can be seen from the figure, there is a pad PD area and a bulk area for the input/output (I10) cell 10G on the periphery of the chip.
A basic cell row BL1. is formed by vertically connecting basic cells. BL2...
BLn are arranged at intervals. Note that the area between the basic cell columns becomes a wiring area.

FIG. 14 is a plan view of essential parts showing the basic cells constituting the basic cell array in FIG. 13 as a specific bulk pattern.

In the figure, l is a p-type impurity diffusion region, 2 is an n-type impurity diffusion region, 3G1 and 3G2 are polycrystalline silicon gate electrodes, 4CN is an n-type substrate contact pattern, and 4CP
represents a p-type substrate contact pattern, QPI and QP2 represent n-channel transistors, and QNI and QN2 represent n-channel transistors, respectively. Note that the p-type impurity diffusion region 1 constitutes the source region or drain region of the n-channel transistors QPI and QP2, and the n-type impurity diffusion region 2 constitutes the n-channel transistor QPI and the drain region.
This constitutes the source region or drain region of the transistors QNI and QN2. In addition, the n-channel transistor part is formed by n-channel transistors QPI and QP2, and the n-channel transistor part is replaced by n-channel transistors QNI and QN2.
They each constitute an n-channel transistor part.

FIG. 15 is an equivalent circuit diagram of the main part of the basic cell l explained in connection with FIG. 14.

In the figure, QPI and QP2 are n-channel transistors, and QNI and QN2 are n-channel transistors, respectively.

Now, in order to construct a circuit using the basic cells described above, it is necessary to form a small-scale circuit called a unit cell by assembling a required number of the basic cells arranged vertically in the basic cell row.
For example, two-man powered NAND circuits, two-man powered NOR circuits, flip-flop circuits, etc. can be configured by forming two layers of aluminum (AN) wiring in the wiring area between basic cell columns. It is completed by connecting.

FIG. 16 is a plan view of a main part showing a bulk pattern when a circuit combining a two-man NAND circuit and an inverter circuit is constructed using two basic cells explained in connection with FIGS. 14 and 15; The same parts as those explained with reference to FIGS. 13 to 15 are indicated by the same symbols.

In the figure, LA is the l wiring in the first layer, LB is the AN wiring in the second layer, NA is the contact part between the AIl wiring LA in the first layer and the semiconductor substrate (white circle: ○), and NB is the contact part between the AIl wiring LA in the first layer and the semiconductor substrate. The contact part between the second layer AN wiring LB and the first layer AJ wiring LA (double circle; ◎), van is the positive power supply level, VSL
l indicates the ground side power supply level.

FIG. 17 is an equivalent circuit diagram of the main part of the circuit shown in FIG. 16.

In the figure, ND represents a two-manpower NAND circuit, INV represents an inverter circuit, AI and A2 represent input signals, and X represents an output signal.

[Problem that the invention seeks to solve]

The basic cells described with respect to FIGS. 14 and 15 are 2
It is effective when creating logic circuits such as manual NAND or two-man NOR, but when configuring circuits such as RAM, ROM1 transmission gate circuit, etc., a large number of transistors are required or a large number of redundant transistors are generated. There are drawbacks.

For example, to form a RAM cell, four basic cells are required, and six unused transistors are required.
Individuals also arise. Furthermore, when forming a transmission gate circuit, since only two sets of the basic cells can be formed, unnecessary transmission gates are often formed, which is wasteful.

The present invention improves the basic cells for configuring LSIs manufactured by applying the mask slicing method as described above, and allows not only the creation of logic circuits such as NAND or NOR, which were previously possible, but also In order to be able to easily configure RAM, ROM, l-transmission gate circuits, etc. with a small number of basic cells, and to avoid the generation of redundant transistors, the occupied area is reduced compared to when using conventional technology. Furthermore, by slightly modifying the bulk pattern, the characteristics can be improved when various types of circuits are constructed.

[Means for solving problems]

In the semiconductor integrated circuit of the present invention, two p-channel transistors are arranged such that channels are aligned in one direction, share a source region or a drain region, and each have independent gate electrodes that determine the effective gate width. a p-channel transistor portion consisting of a p-channel transistor portion, and a gate electrode having channels arranged in the same direction as the one direction, sharing a source region or a drain region, and having different effective gate widths. The configuration includes a basic cell in which n-channel transistor portions each consisting of n-channel transistors are arranged in parallel, or a configuration in which two of the basic cells are combined to form a basic cell.

[Effect]

According to the above configuration, the p-channel transistor portion and the n
The gate electrodes from the channel transistor part are separated from each other, and the two p-channel transistors that make up the p-channel transistor part have one effective gate width larger than the other. The same relationship holds true for the effective gate widths of the two n-channel transistors constituting the n-channel transistor portion.

Therefore, it is possible to configure transmission gate circuits (RAM, ROM, etc.) with a small number of basic cells without unnecessary transistors. Alternatively, a logic circuit such as a NOR can be easily configured, and when a NAND circuit is configured, for example, the rise and fall characteristics can be improved.

〔Example〕

FIG. 1 is a plan view of a main part showing a concrete bulk pattern of a second embodiment of the present invention, and FIGS.
The same parts as those described with respect to the figures are indicated by the same symbols.

In the figure, CN is the n-type substrate contact H1 region, cp is the p
Type substrate contact area, GPI, GP2°GNl, CN
2 is a polycrystalline silicon gate electrode, w,,w,',wb
, wb' is the effective gate width of the transistor, BLP is p
Channel transistor rows and BLN respectively indicate n-channel transistor rows. Incidentally, the relationship between the effective gate widths is W,=w,'>wb=wb'.

This embodiment differs from the conventional example explained with reference to FIGS. 14 and 15 in that p-channel transistors QPI and QP2, n-channel transistors QNI and CN2
are independent gate electrodes GPI and GP2, G
NI and GN2, and the effective gate width W8' of the n-channel transistor QPI is greater than the effective gate width Wb' of the n-channel transistor QP2;
Further, the effective gate width W8 of the n-channel transistor QNI is larger than the effective gate width Wb of the n-channel transistor QN2. Figure 2 is the first
It is an equivalent circuit diagram of the main part of the basic cell explained with reference to the figure,
The same parts as those described with reference to FIG. 2 are indicated by the same symbols.

By combining two sets of the basic cells described with reference to FIGS. 1 and 2, a very distinctive circuit configuration can be obtained.

That is, an 8-transistor basic cell can be configured with an area increase of about 30% compared to the conventional 4-transistor basic cell explained with reference to FIG. It is possible to easily configure the cell, and since the 8-transistor basic cell includes two types of transistors with different effective gate widths in one conductivity type channel transistor, NAND, NOR, inverter, etc. It is possible to realize several types of circuits with different characteristics, and it is possible to construct a logic circuit group that can be fine-tuned with regard to drive capability, delay time, noise margin, etc.

FIG. 3 is a plan view of the main parts of an 8-transistor basic cell, which is a combination of two basic cells shown in FIG. The same parts as those explained in connection with FIG. 16 are indicated by the same symbols.

In the figure, 1' is a p-type impurity diffusion region, 2' is an n-type impurity diffusion region, and QPI' and QP2' are n-channel impurity diffusion regions.
The transistors QNI' and QN2' are n-channel
Transistor, GPI', GP2'.

GNI' and GN2' indicate polycrystalline silicon gate electrodes, respectively.

FIG. 4 is an equivalent circuit diagram of a main part of the basic cell explained in connection with FIG. 3, and the same parts as those explained in connection with FIG. 3 are indicated by the same symbols.

Next, cases in which various circuits are constructed using the basic cells described with reference to FIGS. 3 and 4 will be explained by way of example.

FIG. 5 is a plan view of the main parts showing the bulk pattern when a NAND circuit is configured, and FIGS. 1 to 4 and 1
The same parts as those explained with reference to FIGS. 3 to 17 are indicated by the same symbols.

In the figure, X and X2 represent input terminals, and Y represents an output terminal.

FIG. 6 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 5, and the same parts as those explained with respect to FIGS. be.

In the NAND circuit shown in FIGS. 5 and 6, n-channel transistors QPI and Q with large effective gate widths are used.
PI', n-channel transistors QNI and QNI'
The circuit is constructed using only

By the way, in this embodiment, considering the impedance seen from the output terminal Y of each transistor, n-channel transistors QPI and QPI' are in parallel, and n-channel transistors QNI and QNI' are in series, so Each has a different impedance, and as a NAND circuit, the rising and falling characteristics are asymmetrical.

Therefore, QP whose effective gate width is small as n-channel transistors in parallel, that is, Wb'
2 and QP2' in series.
If QNI and QNI' are used as transistors, their impedances will be the same, so the rise and fall characteristics can be made symmetrical.

FIG. 7 is a plan view of the main part of the bulk pattern of the NAND circuit, which takes into account the impedance alignment as described above, and is the same as the part explained in connection with FIGS. 1 to 6 and 13 to 17. Parts are indicated by the same symbol.

FIG. 8 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 7, and the same parts as those explained with respect to FIGS. 1 to 7 and 13 to 17 are designated with the same symbols. be.

In the NAND circuit shown in FIGS. 7 and 8, n-channel transistors QP2 and Q
It is clear that P2' and n-channel transistors QNI and QNI' with large effective gate widths are used.

FIG. 9 is a plan view of the main part showing the bulk pattern of the clock synchronization gate circuit in configurations 1 to 1, and the same parts as those explained with respect to FIGS. 1 to 8 and 13 to 17 are It is indicated by the same symbol.

In the figure, CK and CK are input terminals for a clock signal and an inverted clock signal.

FIG. 10 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 9, and the same parts as those explained with respect to FIGS. 1 to 9 and 13 to 17 are designated with the same symbols. be.

In the clock synchronized gate circuit shown in FIGS. 9 and 10, an n-channel transistor Q with a large effective gate width is used.
Like PI and QPI', n-channel transistors QNI and QNI' having large effective gate widths are connected in series.

FIG. 11 is a plan view of a main part showing a bulk pattern when a 6-transistor RAM cell is configured, and the same parts as those explained with respect to FIGS. 1 to 1θ and FIGS. 13 to 17 have the same symbols. This is the instruction.

FIG. 12 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 11, and the same parts as those explained with respect to FIGS. 1 to 11 and FIGS. 13 to 17 are designated with the same symbols. be.

In the figure, XBL and XBL' represent bit lines, and WL represents a word line.

In the six-transistor RAM cell shown in FIGS. 11 and 12, n-channel transistor QP1' and n-channel transistor QN2' form one inverter, and n-channel transistor QPI and n-channel transistor QN2 form one inverter. further constitute one inverter each, and the n-channel transistors QNI' and QNI
constitutes a transmission gate.

Note that since the p and n channels are separated and independent, it is clear that the transmission gate circuit can be realized easily and efficiently.

〔Effect of the invention〕

A semiconductor integrated circuit of the present invention includes two n-channel transistors each having independent gate electrodes having channels arranged in one direction, sharing a source region or a drain region, and having different effective gate widths. and an n-channel transistor portion, each independently having a gate electrode arranged so that the channels are aligned in the same direction as the one direction, sharing a source region or a drain region, and having different effective gate widths. n of pieces
The configuration includes a basic cell in which n-channel transistor portions each consisting of a channel transistor are arranged in parallel, or a configuration in which two of the basic cells are combined to form a basic cell.

These basic cells contain 4 to 8 transistors, and a basic cell with 8 transistors is about 30% smaller than a conventional basic cell with 4 transistors. This is achieved by increasing the area of
Each basic cell has a transistor with a large effective gate width and a transistor with a small effective gate width for each conductivity type of p and n. It is possible to configure the structure so as to avoid unnecessary transistors.
Furthermore, of course, logic circuits such as NAND or NOR can be easily constructed in the same way as conventional basic cells, and since transistors with different effective gate widths are included, for example, a NAND circuit can be constructed. In this case, the rise and fall characteristics can be improved to be symmetrical.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part showing a bulk pattern of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a main part of the embodiment shown in FIG. 1, and FIG. FIG. 4 is a plan view of the main part showing the bulk pattern of the embodiment, FIG. 4 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 3, and FIG. 6 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 5, and FIG. 7 is a plan view of another NAND circuit constructed using the basic cell of the present invention. FIG. 8 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 7, and FIG. 9 is a plan view of the main part showing the bulk pattern of the embodiment shown in FIG. 10 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 9, and FIG. 11 is a 6-transistor row AM cell constructed using the basic cell of the present invention. 12 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 11, FIG. 13 is a plan view of the main part of the gate array,
FIG. 14 is a plan view of the main part showing the bulk pattern of a conventional basic cell, FIG. 15 is an equivalent circuit diagram of the main part of the basic cell shown in FIG. When configuring a human-powered NAND circuit and an inverter, the bulk
FIG. 17 is a plan view of the main part showing the pattern, and an equivalent circuit diagram of the main part of the conventional example shown in FIG. 16. In the figure, PD is band, IOC is I10 cell, BL
I, BL2...BLn is the basic cell row, 1 and 1'
are p-type impurity diffusion regions, 2 and 2' are n-type impurity diffusion regions, 3G1.3G2. 'G.P.I. CP2. GNI, CN2 are polycrystalline silicon gate electrodes, CN and 4CN are n-type substrate contact regions, CP and 4CP are p-type substrate contact regions, QPI, CP2. Q
PI', QP2' are p-channel channel transistors, QN
I, QN2. QNI'. QN2' is an n-channel transistor, LA is the first layer A/I wiring, LB is the second layer Aβ wiring, NA is AA
Contact part between wiring LA and semiconductor substrate/board, NB is A
E wiring LB! =A! Contact part with wiring LA, V
DD is the positive power supply level, VSS is the ground power supply level, B
LP is an n-channel transistor string, BLN is an n-channel transistor string, w,, w,' , wb, wb '
is the effective gate width of the transistor, X and X2 are input terminals, Y is output terminal, CK and CK are clock signals and inverted clock signals, XBL and XBL' are bit lines, WL
indicate word lines, respectively. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Akira Aitani Representative Patent Attorney: Hiroshi Watanabe - Kazuno () Figure 6 Figure 8 Figure 12 Figure 13 Figure 14

Claims (2)

[Claims] (1) Channels are arranged in one direction, share a source region or a drain region, and have independent gate electrodes with different effective gate widths.2
a p-channel transistor portion consisting of p-channel transistors, and a gate electrode whose channels are arranged in the same direction as the one direction, share a source region or a drain region, and have different effective gate widths. 1. A semiconductor integrated circuit comprising a basic cell in which n-channel transistor portions each consisting of two independent n-channel transistors are arranged in parallel. (2) The semiconductor integrated circuit according to claim 1, wherein two of the basic cells are combined to form a basic cell.