JPS60257573A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60257573A JPS60257573A JP59113185A JP11318584A JPS60257573A JP S60257573 A JPS60257573 A JP S60257573A JP 59113185 A JP59113185 A JP 59113185A JP 11318584 A JP11318584 A JP 11318584A JP S60257573 A JPS60257573 A JP S60257573A
- Authority
- JP
- Japan
- Prior art keywords
- frequency characteristics
- load
- input terminal
- input
- detecting section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 230000000694 effects Effects 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、半導体装置に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device.
（従来例の構成とその問題点）
半導体素子と９わけＭＯ８型素子は、その構造上外部か
らの入力端子もしくは出力端子に高電圧が加わると絶縁
破壊によって＃Ｊが正常に動作しなくなる。これを防ぐ
ため、はとんどの半導体素子には抵抗性領域、ダイオー
ド、保護用ケ゛−ト電極、もしくはと扛らを組み合わせ
だ入力保護回路が設けられている。(Structure of conventional example and its problems) Because of the structure of the semiconductor element and the 9-part MO8 type element, if a high voltage is applied to the input terminal or output terminal from the outside, #J will not operate normally due to dielectric breakdown. To prevent this, most semiconductor devices are equipped with input protection circuits that include resistive regions, diodes, protective gate electrodes, or a combination of these.
この種の入力保護回路の従来例を第１図を用いて説明す
る。第１図において、半導体素子ｌの中に入力端子２が
あり、それに抵抗性領域３、ダイオード４が設けられて
おシ、負荷５に接続されている。この例は、入力端子２
には基板１に対して正電圧が印加される場合の例である
。ところがこの構成では、入力端子２に高周波クロック
ｚｅルスが印加され、負荷５が大容量性の場合、この容
量と抵抗性領域３の抵抗のために、入力端子２に印加し
たクロ、クパルスがなまってしまい、好捷しくない動作
になることがある。この欠点を改善するだめに、第２図
に示したように、負荷を複数個の負荷５ ａ ＋ ５
ｂに分割し、それぞれに独立した入力端子２ａ、２ｂか
らクロック・ぐルスを印加するようにした構成もある。A conventional example of this type of input protection circuit will be explained with reference to FIG. In FIG. 1, there is an input terminal 2 in a semiconductor element 1, which is provided with a resistive region 3, a diode 4, and is connected to a load 5. In this example, input terminal 2
This is an example in which a positive voltage is applied to the substrate 1. However, in this configuration, when a high frequency clock pulse is applied to the input terminal 2 and the load 5 has a large capacitance, the clock pulses applied to the input terminal 2 are distorted due to this capacitance and the resistance of the resistive region 3. This may result in undesirable behavior. In order to improve this drawback, as shown in FIG.
There is also a configuration in which the circuit is divided into two parts, and a clock signal is applied to each part from independent input terminals 2a and 2b.
抵抗性領域３ａ 、３ｂ、ダイオード４ａ、４ｂもそれ
ぞれ各回路毎に設ける。しかしこの構成では、独立した
入力端子が、負荷を分割した数だけ必要であり、半導体
素子のビン数が増してしまうという欠点があった。Resistive regions 3a, 3b and diodes 4a, 4b are also provided for each circuit. However, this configuration requires as many independent input terminals as the number of divided loads, and has the disadvantage that the number of semiconductor element bins increases.
（発明の目的）
本発明は、上記従来技術の欠点に鑑み、込力端十数を増
すことなく、周波数特性の劣化をなくす半導体装置を提
供するものである。(Object of the Invention) In view of the drawbacks of the prior art described above, the present invention provides a semiconductor device that eliminates deterioration of frequency characteristics without increasing the input power.
（発明の構成）
上記目的を達成するために、本発明は、一つの入力端子
に複数個の抵抗性領域の各一端をそれぞれ共通に接続し
て構成するものである。(Structure of the Invention) In order to achieve the above object, the present invention is configured by commonly connecting one end of each of a plurality of resistive regions to one input terminal.
（実施例の説明）
第３図は、本発明の一実施例を示したものである。一つ
の入力端子２にそれぞれ一端が共通に接続された抵抗性
領域３ａ 、３ｂを形成し、それぞれにダイオード４ａ
、４ｂを設けることによって独立した入力保護装置を
形成している。そして、それぞれに負荷５ａ、５ｂを接
続している。この構成によって、第２図と同等の周波数
特性が得られるのは明らかであり、かつ入力端子は１つ
でよいため、半導体素子のピン数は第１図の場合と同じ
である。(Description of Embodiment) FIG. 3 shows an embodiment of the present invention. Resistive regions 3a and 3b each having one end commonly connected to one input terminal 2 are formed, and a diode 4a is connected to each of the resistive regions 3a and 3b.
, 4b form an independent input protection device. Loads 5a and 5b are connected to each of them. It is clear that with this configuration, frequency characteristics equivalent to those in FIG. 2 can be obtained, and since only one input terminal is required, the number of pins of the semiconductor element is the same as in the case of FIG. 1.
このような構成によれば、電荷転送素子の出力１・ 信
号の周波数特性を向上させる上で効果が太きい、すなわ
ち同一クロックパルスを印加する転送電極のうちの電荷
検知部の直前の転送電極を第３図の負荷５ａとして用い
、負荷５ｂとして残りの電極を用いる。こうすることに
よって電荷検知部直前の転送電極には、周波数特性の高
いクロックパルスが印加されるため、電荷検知部からの
出力も高い周波数特性が得らｎる。According to such a configuration, the effect of improving the frequency characteristics of the output 1 signal of the charge transfer element is large, that is, the transfer electrode immediately before the charge detection section among the transfer electrodes to which the same clock pulse is applied is The electrodes are used as the load 5a in FIG. 3, and the remaining electrodes are used as the load 5b. By doing this, a clock pulse with high frequency characteristics is applied to the transfer electrode immediately before the charge detection section, so that the output from the charge detection section can also have high frequency characteristics.
以上述べた実施例は、入力保護装置として、抵抗性領域
とダイオードを備えた場合であるが、抵抗性領域３ａ、
３ｂを含んでおれば、ダイオードの代りにツェナーダイ
オード、保護用ケ゛−ト電極等の他の素子を使用した構
成でも効果は同様である。なお抵抗性領域には不純物拡
麩層がよく使用さ扛ている。また−導電型の半導体基板
上に設けられた反対導電型領域内に入力保護回路、半導
体素子の能動領域が形成されている場合も有効であるこ
とはもちろんである。The embodiment described above is a case where a resistive region and a diode are provided as the input protection device, but the resistive region 3a,
3b is included, the same effect can be obtained even if other elements such as a Zener diode or a protective gate electrode are used in place of the diode. Note that an impurity diffusion layer is often used in the resistive region. Of course, it is also effective when the input protection circuit and the active region of the semiconductor element are formed in a region of the opposite conductivity type provided on the -conductivity type semiconductor substrate.
（発明の効果）
以上説明したように、本発明によれば、一つの入力端子
にそｎぞれ一端が共通接続された複数個の抵抗性領域を
形成することによって、半導体素子の一ン数を増すこと
なく、高い周波数特性を得ることができ、その実用的効
果は犬なるものがある。(Effects of the Invention) As explained above, according to the present invention, by forming a plurality of resistive regions each having one end commonly connected to one input terminal, one number of resistive regions of a semiconductor element can be reduced. High frequency characteristics can be obtained without increasing the frequency, and its practical effects are significant.
第１図は、 半導体素子における入力保護回路の従来例
を示す図、第２図は、周波数特性を保つために保護回路
を分割した従来例を示す図、第３図は、本発明の一実施
例の構成図である。
１・・半導体素子、２・・・入力端子、３ａ、３ｂ・・
・抵抗性領域、４ａ 、４ｂ・・・ダイオード、５ａ、
５ｂ・・・負荷。
第１図
第２図
■
１１
Ｌ、 ＪFig. 1 shows a conventional example of an input protection circuit for a semiconductor device, Fig. 2 shows a conventional example in which the protection circuit is divided to maintain frequency characteristics, and Fig. 3 shows an example of an implementation of the present invention. It is a block diagram of an example. 1...Semiconductor element, 2...Input terminal, 3a, 3b...
・Resistive region, 4a, 4b...diode, 5a,
5b...Load. Figure 1 Figure 2 ■ 11 L, J
Claims (1)
の抵抗性領域をそなえたことを特徴とする半導体装置。A semiconductor device comprising a plurality of resistive regions each having one end commonly connected to one input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59113185A JPH0666345B2 (en) | 1984-06-04 | 1984-06-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59113185A JPH0666345B2 (en) | 1984-06-04 | 1984-06-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60257573A true JPS60257573A (en) | 1985-12-19 |
| JPH0666345B2 JPH0666345B2 (en) | 1994-08-24 |
Family
ID=14605706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59113185A Expired - Lifetime JPH0666345B2 (en) | 1984-06-04 | 1984-06-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666345B2 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826196A (en) * | 1971-08-06 | 1973-04-05 | ||
| JPS5645067A (en) * | 1979-09-21 | 1981-04-24 | Hitachi Ltd | Integrated circuit device |
| JPS57148373A (en) * | 1981-03-09 | 1982-09-13 | Sony Corp | Charge transfer method |
| JPS57148372A (en) * | 1981-03-09 | 1982-09-13 | Sony Corp | Method for charge transfer |
| JPS58103172A (en) * | 1981-12-16 | 1983-06-20 | Nec Corp | charge transfer device |
-
1984
- 1984-06-04 JP JP59113185A patent/JPH0666345B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826196A (en) * | 1971-08-06 | 1973-04-05 | ||
| JPS5645067A (en) * | 1979-09-21 | 1981-04-24 | Hitachi Ltd | Integrated circuit device |
| JPS57148373A (en) * | 1981-03-09 | 1982-09-13 | Sony Corp | Charge transfer method |
| JPS57148372A (en) * | 1981-03-09 | 1982-09-13 | Sony Corp | Method for charge transfer |
| JPS58103172A (en) * | 1981-12-16 | 1983-06-20 | Nec Corp | charge transfer device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0666345B2 (en) | 1994-08-24 |
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