JPS60257576A - Input protection circuit for MIS type field effect semiconductor device - Google Patents
Input protection circuit for MIS type field effect semiconductor deviceInfo
- Publication number
- JPS60257576A JPS60257576A JP59115894A JP11589484A JPS60257576A JP S60257576 A JPS60257576 A JP S60257576A JP 59115894 A JP59115894 A JP 59115894A JP 11589484 A JP11589484 A JP 11589484A JP S60257576 A JPS60257576 A JP S60257576A
- Authority
- JP
- Japan
- Prior art keywords
- input
- input protection
- protection resistor
- diode
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はＭＩＳ形（ｍｅｔａｌ １ｎｓｕｌａｔｏｒ
ａｅｍｉｃｏｎｄｕｅｔｏｒ ）電界効果半導体装置に
用いる入力保護回路に関する０
〔従来技術〕
従来この種の入力保護回路として、第１図に示すように
ＭＩＳ形電界効果トランジスタ（以下、ＭＩＳ −ＦＥ
Ｔと称する）１のゲート２に入力保護回路３を接続し、
この抵抗３とゲート２との接続点４にダイオード５．ダ
イオード６を接続し、さらにダイオード５のカソードを
高電位電源端子ｖｃｃに、またダイオード６のアノード
を低電位電源端子ＧＮＤに接続したものがある。この入
力保護回路は入力端子７に過大入力電圧が加わった場合
速やかにダイオード５，６を介して電流を流出させ、入
力電圧をクランプしてＭＩＳ−ＦＥＴＩのゲート２にゲ
ート・ソース間の絶縁破壊耐圧以上の電圧が印加されな
いようにしている。例えば、入力端子７に加わる過大入
力電圧が正の時は、その時の等価回路を第２図に示すよ
うに、過大入力電圧８によシ生ずる電流を入力保護抵抗
３を介してダイオード５により流出させ、これによって
ＭＩ Ｓ −ＦＥＴ１のゲート２に絶縁破壊耐圧以上の
電圧が印加されないようにしている１゜一方、入力端子
７に加わる過大入力電圧が負の時は（等価回路は図示し
ていないが）同様にしてダイオード６を介して電流を流
出させてＭＩＳ−ＦＥＴＩのゲート２に絶縁破壊耐圧以
上の電圧が印加されないようにしている。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an MIS type (metal insulator)
[Prior Art] Conventionally, as this type of input protection circuit, as shown in FIG.
Connect the input protection circuit 3 to the gate 2 of 1 (referred to as T),
A diode 5 is connected to the connection point 4 between this resistor 3 and the gate 2. There is one in which a diode 6 is connected, the cathode of the diode 5 is connected to the high potential power supply terminal VCC, and the anode of the diode 6 is connected to the low potential power supply terminal GND. When an excessive input voltage is applied to the input terminal 7, this input protection circuit immediately drains current through the diodes 5 and 6, clamps the input voltage, and prevents gate-source dielectric breakdown at the gate 2 of the MIS-FETI. A voltage higher than the withstand voltage is not applied. For example, when the excessive input voltage applied to the input terminal 7 is positive, the equivalent circuit at that time is shown in FIG. This prevents a voltage higher than the dielectric breakdown voltage from being applied to the gate 2 of the MIS-FET 1. On the other hand, when the excessive input voltage applied to the input terminal 7 is negative (the equivalent circuit is not shown) (b) Similarly, current is caused to flow out through the diode 6 to prevent a voltage higher than the dielectric breakdown voltage from being applied to the gate 2 of the MIS-FETI.
このとき、入力保護抵抗３はダイオード５およびダイオ
ード６に流れる電流を制限し、これらダイオード５，６
が過電流のために破壊してしまうのを防止している。ま
た、このときの入力保護抵抗３に加わるパワーｐ’１式
で表わすと次式のようになる。At this time, the input protection resistor 3 limits the current flowing through the diode 5 and the diode 6.
This prevents damage caused by overcurrent. Further, the power applied to the input protection resistor 3 at this time is expressed by the following equation.
ここでＶは入力端子７に印加される過大入力電圧（、）
、Ｒは入力保護抵抗３の抵抗値（Ω）である。Here, V is the excessive input voltage applied to input terminal 7 (,)
, R is the resistance value (Ω) of the input protection resistor 3.
但し、ダイオードに分圧される電圧は無視するものとす
る。また、ダイオードに流れる電流Ｉは次式で表わされ
る。However, the voltage divided by the diode is ignored. Further, the current I flowing through the diode is expressed by the following equation.
・、ｊ′Ｌ″ｌ＞ｈ Ｌｆｔ −Ｉｒｅ ９・ｉ＊ｏ
ａ （７）”５１”０１１１ によると入力端子７に印
加された過大入力電圧のパワーが入力保護抵抗３に集中
してｌ、ｔい、このパワーによって入力保護抵抗３が破
壊してしまう虞れがあった。・,j′L″l>h Lft −Ire 9・i＊o
According to a (7) "51" 0111, the power of the excessive input voltage applied to the input terminal 7 is concentrated on the input protection resistor 3, and there is a risk that the input protection resistor 3 may be destroyed by this power. was there.
本発明は従来のこのような点に鑑みてなされたもので、
その目的とするところは、入力保護能力を向上させたＭ
ＩＳ形電界効果半導体装置の入力保護回路を提供するこ
とにある。The present invention has been made in view of these conventional points, and
The purpose is to improve the input protection ability of M
An object of the present invention is to provide an input protection circuit for an IS type field effect semiconductor device.
このような目的を達成するために本発明は、第１の入力
保護抵抗をＭＩＳ形電界効果半導体装置のゲートに接続
するとともに、この第１の入力保護抵抗に直列に第２の
入力保護抵抗を接続し、この第２の入力保護抵抗と第１
の入力保護回路との接続点に第３の入力保護抵抗とダイ
オードとからなる直列回路を接続したものである。In order to achieve such an object, the present invention connects a first input protection resistor to the gate of the MIS type field effect semiconductor device, and connects a second input protection resistor in series with the first input protection resistor. This second input protection resistor and the first
A series circuit consisting of a third input protection resistor and a diode is connected to the connection point with the input protection circuit.
第３図は本発明に係るＭＩＳ形電界効果半導体装置の入
力保護回路の一実施例を示す回路図である。FIG. 3 is a circuit diagram showing an embodiment of the input protection circuit for the MIS type field effect semiconductor device according to the present invention.
図において、第１図と同一符号は同一要素を・示しその
説明は省略する。図において、９け接続点４に接続され
た第１の入力保護回路、１０１−ｉこの第１の入力保護
抵抗９に直列に接続された第２の入力保護抵抗である。In the figure, the same reference numerals as in FIG. 1 indicate the same elements, and the explanation thereof will be omitted. In the figure, a first input protection circuit 101-i is connected to the connection point 4, and a second input protection resistor 101-i is connected in series to the first input protection resistor 9.
この第２の入力保護抵抗１０と第１の入力保護抵抗９と
の接続点１１には第３の入力保護抵抗１２とダイオード
１３とからなる第１の直列回路と第４の入力保護抵抗１
４とダイオード１５とからなる第２の直列回路とが接続
されている。そしてダイオード１３のカソードは高電位
電源端子ｖｃｃに、ダイオード１５のアノードは低電位
電源端子ＧＮＤに夫々接続されている。At a connection point 11 between the second input protection resistor 10 and the first input protection resistor 9, a first series circuit consisting of a third input protection resistor 12 and a diode 13 and a fourth input protection resistor 1 are connected.
4 and a second series circuit consisting of a diode 15 are connected. The cathode of the diode 13 is connected to the high potential power terminal VCC, and the anode of the diode 15 is connected to the low potential power terminal GND.
以下、このように構成された本発明のＭＩＳ形電界効果
半導体装置の入力保護回路の動作を説明する。第４図に
この回路の入力端子Ｔに正の過大入力電圧が加わった時
の等価回路を示す。入力端子７に正の過大入力電圧８が
印加されると、これによって生じる電流は第２の入力保
護抵抗１０を流れ、さらに第３の入力保護抵抗１２およ
び第１の入力保護抵抗９によシ分流されダイオード１３
およびダイオード５を介して速やかに流出する。一方、
入力端子７に負の過大入力電圧が加わると（等価回路は
図示していないが）上述と同様にこれによって生じる電
流は第４の入力保護抵抗１４および第１の入力保護抵抗
９により分流され、ダイオード１５およびダイオード６
を介して速やかに流出する。これによって従来と同様に
入力電圧がクランプされＭＩＳ−ＦＥＴ１のゲート２に
絶縁破壊耐圧以上の電圧が印加されないように保亡され
る。The operation of the input protection circuit of the MIS type field effect semiconductor device of the present invention configured as described above will be explained below. FIG. 4 shows an equivalent circuit when an excessive positive input voltage is applied to the input terminal T of this circuit. When a positive excessive input voltage 8 is applied to the input terminal 7, the current generated thereby flows through the second input protection resistor 10, and is further shunted through the third input protection resistor 12 and the first input protection resistor 9. Shunted diode 13
and quickly flows out via diode 5. on the other hand,
When an excessive negative input voltage is applied to the input terminal 7 (the equivalent circuit is not shown), the current generated thereby is shunted by the fourth input protection resistor 14 and the first input protection resistor 9, as described above. Diode 15 and diode 6
It flows out quickly through the. As a result, the input voltage is clamped in the same way as in the prior art, and maintained so that a voltage higher than the dielectric breakdown voltage is not applied to the gate 2 of the MIS-FET 1.
ここで、各入力保護抵抗に加わる過大入力電圧のパワー
Ｐおよび各ダイオードに流れる電流■ｆｃ正の過大入力
電圧８が加わった時を例に従来のものと比較してみる。Here, we will compare the power P of the excessive input voltage applied to each input protection resistor and the current (fc) flowing through each diode with the conventional one, taking as an example a case where a positive excessive input voltage 8 is applied.
但し、ＭＯＳ−ＦＥＴ １のスイッチング速度に影響を
与えないようにするために第１の入力保護抵抗９の値と
第２の入力保護抵抗１０の値との和は従来の入力保護抵
抗３の値に等しいものとする。また、これら各抵抗の値
は任意ではあるが、計算上従来の入力保護抵抗３の値ｅ
Ｒ（Ω）とし、第１の入力保護抵抗９の値ｋ ”１５
Ｒ（Ω）、第２の入力保護抵抗１０の値ｋ Ｖｓ ’Ｒ
（Ω）、第３の入力保護回路１２の値ｆ：４１５Ｒ（Ω
）と定める。However, in order to avoid affecting the switching speed of MOS-FET 1, the sum of the value of the first input protection resistor 9 and the value of the second input protection resistor 10 is the same as the value of the conventional input protection resistor 3. shall be equal to In addition, although the value of each of these resistors is arbitrary, the value e of the conventional input protection resistor 3 is calculated based on the calculation.
R (Ω), and the value of the first input protection resistor 9 is k ”15
R (Ω), value of the second input protection resistor 10 k Vs 'R
(Ω), value f of the third input protection circuit 12: 415R (Ω)
).
正の過大入力電圧８をＶ （ｖ）とすれば各入力保護抵
抗９，１０．１２に夫々加わるパワーＰ９ ＋Ｐ＋ｏ
ｒ Ｐ＋ｚは次式で表わされる。If the positive excessive input voltage 8 is V (v), the power applied to each input protection resistor 9, 10.12 is P9 +P+o
rP+z is expressed by the following formula.
寸だ、ダイオード５およびダイオード１３に夫々流れる
電流Ｉ５ ｔ ＩＩ３は、
ｖ
■５＝−×−・・・・・・・・・（６）Ｒ
ｖ
１１３＝Ｘ−・−・・・・・・・（７） Ｒ
となる。従来の入力保護抵抗３に加わるパワーＰおよび
ダイオード５に流れる電流工は式（１）および（２）よ
り
２
Ｐ−−・・・・・・・・・（１）
ｊ９ Ｒ
□Ｉ
■
■＝−・・・・・・・・・（２）
であり、したがってＰ＞Ｐ９ ＝Ｐ１０ ＝Ｐ１２ 、
Ｉ ＞ Ｉ ｓ ＝ １１３という関係で表わせ、従
来に比して入力保護回路に加わるパワーおよびダイオー
ドに流れる電流は小さくなる。また、入力端子Ｔに負の
過大入力電圧が加わった時も第４の入力保護抵抗１４の
値を４／ｓＲ（Ω）と定めれば同様の式で表わされ入力
保護抵抗に加わるパワーおよびダイオードに流れる電流
は小さくなる。The currents I5 t II3 flowing through diode 5 and diode 13 are as follows: v ■5=-×-... (6) R v 113=X-...・(7) becomes R. The power P applied to the conventional input protection resistor 3 and the current flowing to the diode 5 are calculated from equations (1) and (2) as follows: 2 P−−・・・・・・・・・(1) j9 R □I ■ ■= −・・・・・・・・・(2) Therefore, P>P9 =P10 =P12,
This can be expressed by the relationship I > I s = 113, and the power applied to the input protection circuit and the current flowing through the diode are smaller than in the past. Also, when a negative excessive input voltage is applied to the input terminal T, if the value of the fourth input protection resistor 14 is set as 4/sR (Ω), the power applied to the input protection resistor and The current flowing through the diode becomes smaller.
このように入力保護抵抗を分割し、第１の入力保護抵抗
９と第２の入力保護抵抗１０との接続点１１に入力保護
抵抗とダイオードとからなる直列回路を接続したので、
入力保護抵抗に加わる過大入力電圧のパワーが分散され
、入力保護抵抗に対する保護能力は従来に比して向上す
る。さらに、ダイオードに流れる電流もこれと同時に分
散され小さくなるのでダイオードに対する保護能力も従
来に比して向上することになる。なお、本実施例では第
１の入力保護抵抗９と第２の入力保護抵抗１０との接続
点１１に接続する入力保護抵抗とダイオードからなる直
列回路は正負の過大入力電圧に対して１つずつとしたが
、これに限ることはなく複数個並列に設ければさらに入
力保護抵抗に対する保護能力およびダイオードに対する
保護能力は向上する。また、各入力保護抵抗の値は設計
者の意図により任意に設定することが可能である。Since the input protection resistor is divided in this way and a series circuit consisting of an input protection resistor and a diode is connected to the connection point 11 between the first input protection resistor 9 and the second input protection resistor 10,
The power of excessive input voltage applied to the input protection resistor is dispersed, and the protection ability for the input protection resistor is improved compared to the conventional one. Furthermore, since the current flowing through the diode is also dispersed and reduced at the same time, the protection ability for the diode is improved compared to the prior art. In addition, in this embodiment, the series circuit consisting of an input protection resistor and a diode connected to the connection point 11 between the first input protection resistor 9 and the second input protection resistor 10 is connected to one input protection resistor and one diode each for positive and negative excessive input voltages. However, the present invention is not limited to this, and if a plurality of resistors are provided in parallel, the protection ability against the input protection resistor and the protection ability against the diode can be further improved. Further, the value of each input protection resistor can be arbitrarily set according to the designer's intention.
以上説明したように本発明によるＭＩＳ形電界効果半導
体装置の入力保護回路によれば、第１の入力保護抵抗と
第２の入力保護抵抗との接続点に第３の入力保護抵抗と
ダイオードとからなる直列回路を接続することにより、
入力保護抵抗に加わる過大入力↑ｂ−圧によるパワーを
分散させることができ、入力保護回路に対する保蝕能力
を向上させることができる。また、同時にダイオードに
対する保護能力も向上きせることかできる。As explained above, according to the input protection circuit for the MIS type field effect semiconductor device according to the present invention, the third input protection resistor and the diode are connected to the connection point between the first input protection resistor and the second input protection resistor. By connecting a series circuit,
Power due to excessive input ↑b-pressure applied to the input protection resistor can be dispersed, and the maintenance ability of the input protection circuit can be improved. At the same time, the protection ability for diodes can also be improved.
第１図は従来のＭＩＳ形電界効果半導体装置の入力保護
回路を示す回路図、第２図はこの回路に正の過大入力端
子が印加したときの等価回路図、第３図は本発明に係る
ＭＩＳ形電界効果半導体装置の入力回路の一実施例を示
す回路図、第４図はこの回路に正の過大入力電圧が印加
したときの等価回路図である。
１ ・ ・ ・・ＭＩＳ−ＦＥＴ、２ ・ ・ ・ ・
ゲート、５゜６．１３．１５・拳・・ダイオード、９・
・・・第１の入力保護抵抗、１０・・・・第２の入力保
護抵抗、１２・・・・第３の入力採機抵抗、１４・・・
・第４の入力保護抵抗。
代理人 大岩増ガ１；Fig. 1 is a circuit diagram showing an input protection circuit of a conventional MIS type field effect semiconductor device, Fig. 2 is an equivalent circuit diagram when an excessively positive input terminal is applied to this circuit, and Fig. 3 is a circuit diagram showing an input protection circuit of a conventional MIS type field effect semiconductor device. FIG. 4 is a circuit diagram showing one embodiment of an input circuit of a MIS type field effect semiconductor device, and is an equivalent circuit diagram when an excessive positive input voltage is applied to this circuit. 1 ・ ・ ・ MIS-FET, 2 ・ ・ ・ ・
Gate, 5゜6.13.15・Fist・Diode, 9・
...First input protection resistor, 10...Second input protection resistance, 12...Third input sampling resistance, 14...
・Fourth input protection resistor. Agent Masuga Oiwa 1;
Claims (1)
の入力保護抵抗と、この入力保護抵抗と前記半導体装置
のケートとの接続点に接続されたダイオードと、前記第
１の入力保護抵抗に直列に接続された第２の入力保護抵
抗と、この入力保護抵抗と前記第１の入力保護抵抗との
接続点に接続された、第３の入力保護抵抗とダイオード
とからなる直列回路とを備えたＭＩＳ形電界効果半導体
装置の入力保護回路。The first one connected to the gate of the MIS type field effect semiconductor device.
an input protection resistor, a diode connected to a connection point between the input protection resistor and the gate of the semiconductor device, a second input protection resistor connected in series to the first input protection resistor, and a second input protection resistor connected in series to the first input protection resistor; An input protection circuit for an MIS type field effect semiconductor device, comprising a series circuit including a third input protection resistor and a diode, connected to a connection point between the protection resistor and the first input protection resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59115894A JPS60257576A (en) | 1984-06-04 | 1984-06-04 | Input protection circuit for MIS type field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59115894A JPS60257576A (en) | 1984-06-04 | 1984-06-04 | Input protection circuit for MIS type field effect semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60257576A true JPS60257576A (en) | 1985-12-19 |
Family
ID=14673826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59115894A Pending JPS60257576A (en) | 1984-06-04 | 1984-06-04 | Input protection circuit for MIS type field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60257576A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4763184A (en) * | 1985-04-30 | 1988-08-09 | Waferscale Integration, Inc. | Input circuit for protecting against damage caused by electrostatic discharge |
| JPH02135774A (en) * | 1988-11-17 | 1990-05-24 | Seiko Epson Corp | semiconductor equipment |
| US5032742A (en) * | 1989-07-28 | 1991-07-16 | Dallas Semiconductor Corporation | ESD circuit for input which exceeds power supplies in normal operation |
| US5081514A (en) * | 1988-12-27 | 1992-01-14 | Nec Corporation | Protection circuit associated with input terminal of semiconductor device |
| US5130760A (en) * | 1991-06-11 | 1992-07-14 | Honeywell Inc. | Bidirectional surge suppressor Zener diode circuit with guard rings |
| US5227655A (en) * | 1990-02-15 | 1993-07-13 | Nec Corporation | Field effect transistor capable of easily adjusting switching speed thereof |
| US5691557A (en) * | 1993-12-17 | 1997-11-25 | Nec Corporation | Semiconductor circuit having input protective circuit |
-
1984
- 1984-06-04 JP JP59115894A patent/JPS60257576A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4763184A (en) * | 1985-04-30 | 1988-08-09 | Waferscale Integration, Inc. | Input circuit for protecting against damage caused by electrostatic discharge |
| JPH02135774A (en) * | 1988-11-17 | 1990-05-24 | Seiko Epson Corp | semiconductor equipment |
| US5081514A (en) * | 1988-12-27 | 1992-01-14 | Nec Corporation | Protection circuit associated with input terminal of semiconductor device |
| US5032742A (en) * | 1989-07-28 | 1991-07-16 | Dallas Semiconductor Corporation | ESD circuit for input which exceeds power supplies in normal operation |
| US5227655A (en) * | 1990-02-15 | 1993-07-13 | Nec Corporation | Field effect transistor capable of easily adjusting switching speed thereof |
| US5130760A (en) * | 1991-06-11 | 1992-07-14 | Honeywell Inc. | Bidirectional surge suppressor Zener diode circuit with guard rings |
| US5691557A (en) * | 1993-12-17 | 1997-11-25 | Nec Corporation | Semiconductor circuit having input protective circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3582713A (en) | Overcurrent and overvoltage protection circuit for a voltage regulator | |
| US6809561B2 (en) | Semiconductor power converting apparatus | |
| JP3547135B2 (en) | Protection device using field effect transistor | |
| JPS60257576A (en) | Input protection circuit for MIS type field effect semiconductor device | |
| JPS5917862A (en) | Parallel connector for gate turn-off thyristor | |
| CA1175503A (en) | Cmos turn-on circuit | |
| US5737200A (en) | Semiconductor device protection method | |
| US4075510A (en) | Thyristor voltage switching circuits | |
| JP2000341848A (en) | Reverse-polarity input protective device | |
| JPS62147914A (en) | solid power contacts | |
| US6069493A (en) | Input circuit and method for protecting the input circuit | |
| US4740723A (en) | Semiconductor switch | |
| JPS6037018A (en) | Current limiter | |
| US20060250736A1 (en) | Transient blocking apparatus with electrostatic discharge protection | |
| JP3919624B2 (en) | Power device drive circuit | |
| US3256448A (en) | Protection circuit of a transistor type direct current constant voltage device | |
| JP3542703B2 (en) | Overcurrent protection circuit | |
| JPS61285821A (en) | electronic switch | |
| JPH0336450B2 (en) | ||
| JPS6052444B2 (en) | Multi-power supply overvoltage prevention circuit | |
| JPS61255067A (en) | Protection circuit of mos gate | |
| JPH01196913A (en) | Output overcurrent limit circuit | |
| JPH0323805Y2 (en) | ||
| JP2808950B2 (en) | Semiconductor module | |
| JP3112593B2 (en) | IC with built-in protection circuit |