JPS602695B2 - 3-bit slice recipe generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a RESIDUE generation method for 3-bit slices, and particularly to a method for generating RESIDUEs for different types of slice areas using the same recipe generator even for 3-bit slices. Regarding the recipe generation method.

For example, when a calculation is performed in a data processing device, one method for identifying whether or not the calculation result is correct is a recipe check method.

For example, as shown in Figure 1, when performing an operation on 8-bit data, the result of 1 or 2 is determined by the weight, so the result of the input data is determined, and the result of the operation is determined. The results are compared to check whether the calculation results were performed correctly. In this case, the recipe is usually calculated by slicing every 2 bits, such as 20 and 21, 22 and 23, . . . 26 and 27, or slicing every 4 bits. In this case, since the recipe patterns for each slice are the same pattern, it is possible to use recipe generation units having the same configuration. however,
When the data processing device is configured with an LSI, it is required to reduce the number of melons 1 as much as possible.

Therefore, depending on the LSI, the circuit must be configured as densely as possible, and as a result, a recipe must be generated using a 3-bit slice. in this case,
As shown in FIG. 2, the recipe pattern of the lower three bits 2o to 22 and the recipe pattern of the next three bits 23 to 25 are as shown in type Q and type 8.
121'' and ``212'', it was generally considered that these could not be configured with the same recipe generation unit. The inventors of the present invention have improved this problem and made it possible to generate 3-bit slices with the same recipe generation unit even in the case of 3-bit slices with different non-result patterns. be.

For this purpose, the 3-bit slice recipe generation method of the present invention has an input section into which a recipe based on data divided into 3 bits of N-bit data is input, and an output section where the calculation result of the recipe is output. The present invention is characterized in that a recipe generation section having the same configuration as the output section is provided, and a changing means is provided for changing the extraction position of the output section according to the digit of the N bits, thereby generating the recipe in units of 3 bits. shall be.

An embodiment of the present invention will be described below based on FIGS. 3 to 5.

FIG. 3 is a diagram illustrating the operating principle of the present invention, FIG. 4 is a recipe generating section used in the present invention, and FIG. 5 is an 8-bit recipe generating device.

In the figure, 1 is a type Q recipe generation unit, 2 is a type 8 recipe generation unit, 3 is a recipe generation unit, 4 to 6 are recipe generation units, 7 to 9 are recipe output units, and 10 is a recipe generation unit. The creation section and 11 are the output section.

Before explaining the construction of an embodiment of the present invention, the operating principle of the present invention will be explained based on the truth value explanatory diagram shown in FIG. 3 and with reference to FIGS. 2 and 4.

Now, in Figure 2, if digit 2o = "1" is input, Shiju 1 will occur, if 21 = "1" is input, Shiju 2 will occur, and if 22 = "1" is input, Shiju 1 will occur. arise.

In the type Q pattern, an output as shown in recipe Q in FIG. 3 is produced according to each input state.
For example, if 20 to 22 are all "1", the recipe is 1.
123 = 4 and 4 ÷ 3 = 1...The remainder is 1, so 1
occurs. Similarly, the type 8 pattern also produces an output as shown in recipe 3 in FIG. 3 depending on each input state. Therefore, from this Figure 3, if the type is 22 = A, 21 = B, 20 = C, RESO
=ABC ten ABC+ABC.・・・． ．．・．．
．． mRESI=ABC+ABC+ABC...
…{2) RES2=ABC+ABC ………
{3} Also in type 8, 25 = A', 24:B'
, 23=C', then RESO'=A'BC'+A'B
C'+A'BC'...'41RESI'=A'8C
'+A'BC'...{5'RES2'=
A'BC'+A'BC'+A'BC'...{6}.

By comparing these formulas, we can see that formulas '11 and '2} have the same logic, formulas (21 and '6) have the same logic, and formulas [31 and '5' have the same logic. .

Therefore, based on the above formulas [1], '21, and '3', the recipe generation unit 1 in FIG. 4 is configured, and the above formula {4}
, [5-, '6), when the recipe generating section 2 is configured, the output terminal RESI in the recipe generating section 1 is
is used as the output terminal RES2' of the recipe generating section 2,
If the output device RES2 is also used as the output terminal RESI, the recipe generation sections 1 and 2 can have exactly the same configuration.

Therefore, as shown in FIG. 5, there is a recipe generation section 3 that outputs a recipe according to each bit of 2o to 27, a recipe generation section 4, 5, 6 having the same configuration, and a recipe output section 7, 8, 9. will be established.

Then, 0 is always input to the input terminal A of the recipe generating section 6. In this case, the recipe output units 7 and 9 are connected so that the outputs of the recipe generators 4 and 6 are output as they are. However, the recipe output section 8 is configured so that recipe 1 and recipe 2 are outputted interchangeably. In other words, when the recipe generation section 5 outputs the recipe, the recipe output section 8 outputs the recipe 2, and when the recipe generation section 5 outputs the recipe 2, the recipe output section 8 outputs the recipe 1. . Then, the recipe outputted from each recipe output unit 7 to 9 in this way is applied to a regular recipe generation unit 1 to create, for example, 8-bit data, and the recipe output unit 11
This 8-bit recipe is sent from. Therefore, when this device is configured by dividing LSI chips 1, 0, and m into 3-bit slices as shown by the dashed line in FIG. It is possible to have the same configuration, which is very effective when integrated into LSI.

As described above, according to the present invention, even when a recipe is generated by 3-pin slices, the same recipe generation section can be used, which is very effective when implementing an LSI.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the cutting process, Fig. 2 is an explanatory diagram of problems when slicing 3 bits, Fig. 3 is an explanatory diagram of the operating principle of the present invention,
FIG. 4 shows a recipe generator used in the present invention, and FIG. 5 shows an 8-bit recipe generator. In the figure, 1 is a type Q recipe generation unit, 2 is a type P recipe generation unit, 3 is a recipe generation unit, 4 to 6 are recipe generation units, 7 to 9 are recipe output units, and 10' is a recipe generation unit. 11 shows a creation unit, and 11 shows a transfer unit, respectively. 1 spear 2 spears 3 spears 4 spears 5 spots

Claims (1)

[Claims] 1. A recipe generating section having the same configuration is provided, which has an input section into which a recipe based on data obtained by dividing N-bit data into 3-bit data is input, and an output section from which the calculation result of the recipe is output. A 3-bit slice recipe generation method, characterized in that the recipe is generated in units of 3 bits by providing a changing means for changing the extraction position of the output section according to the digit of the bit.