JPS6027213B2 - Decision feedback automatic equalizer - Google Patents

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to an equalizer for data transmission using eight-phase phase modulation, and particularly to an improvement of a decision feedback automatic equalizer. [Overview of the prior art and its problems] In data transmission using 8-phase phase modulation, a decision feedback automatic equalizer, which is often used in data transmission using general polyphase phase modulation, is conventionally used. It is used. Decision feedback automatic equalizers are often used in these various data transmissions because the in-phase components when the transmitted data is displayed on a two-dimensional plane, and the orthogonal components can be expressed as integer values by appropriate normalization. The main reason for this is that it has the advantage of requiring only addition and subtraction without multiplication, or only with a very small number of additions and subtractions. However, in data transmission using polyphase phase modulation, when the conventional decision feedback automatic equalizer has a large number of phases of data that serves as a decision criterion, and the number of equalizer taps is large, The above-mentioned advantages cannot be enjoyed, and therefore the configuration is complicated and the predetermined calculation processing time is long. If the arithmetic processing time is to be shortened, the speed of the device must be increased, which poses a technical problem. In other words, the decision feedback automatic equalizer has t
=nT (n is a positive integer, T is the data transmission interval) Interference from preceding data included in the equalizer input signal is determined using M pieces of data (M is the number of taps of the equalizer) that have already been determined. The intersymbol interference is removed by estimating the input signal and subtracting this interference from the input signal. The M tap gains are given by estimating sample values of the impulse response of the transmission system observed at the equalizer input. That is, the impulse response sample value of the transmission system is xk (k = - target), the transmission data at t = nT is An, its estimated value is public n, and the m-th tap gain is Cm (m; 1 ~M), then the sample value Yn of the equalizer output signal at t=nT' is Yn:k≧-
Ak However, it is assumed that all the variables in formula '1} are expressed by complex numbers whose real parts correspond to in-phase components and whose imaginary parts correspond to orthogonal components. In addition, in the MS type automatic equalization method, the difference between Yn and the estimated value common n of An obtained by estimating from this Yn is En (En = Yn - common n), and the squared error of this En is at most 4.
N tap gain false ten, = C needle Q. Public engineering m. Bn
(Corrected by 21. The * mark here means the complex conjugate and Q' is an appropriate correction coefficient. Therefore, the tap gain of the equalizer is modified to converge to the optimal value, and the equalizer To get the output signal, 0
It becomes necessary to perform the arithmetic operation on the second term on the right side of equations 1 and 2. Since it is an estimated value of the data of one of the two variables that is multiplied by the correction coefficient Q', and it is a quantity that takes a predetermined finite number of values, if these finite values can be expressed by a simple integer. It becomes possible to use addition instead of multiplication, which is one of the advantages of the decision feedback automatic equalizer as mentioned earlier, but generally speaking, multiplication is is necessary. And like 8-phase phase modulation, An
The possible values of , where i is an imaginary unit, are ±1, ±-rock (
・In the case of 10i), ±− direction (1-i)・±i,

[
1} and ■ to execute the equations as they are, no matter what kind of normalization is performed, a multiplication corresponding to the voice is required, and the number of required multiplications is proportional to the number of taps, so if there are many taps, may require very fast multiplication. [Object of the Invention] Therefore, an object of the present invention is to provide a decision feedback type automatic equalizer for a data transmission system using eight-phase phase modulation, which is simple in structure and requires short processing time. [Summary and Effects of the Invention] To summarize, the present invention for achieving the above-mentioned object converts 8-phase phase modulation data into integral multiples of 900 and 45
The data involved in convolution is stored separately as odd multiples of 0, and data that is an integer multiple of 90o is subjected to the convolution operation as is, while data that is an integer multiple of 45o is rotated by 450 times. After convolution, the result is reversely rotated by 450,
As a result, the multiplication of the taps that occur in each term of the operation is completed only ・times, and for correction of the tap gain,
The operation of multiplying by a correction coefficient is replaced with a bit shift, so that the number of multiplications can be reduced to only two by using a simple storage device. Next, the configuration will be specifically explained. [Specific configuration of the invention] The decision feedback type automatic equalizer of the present invention is a transmission device using eight-phase phase modulation, and receives an input signal obtained from a received signal of the automatic equalizer and makes a decision. , a determiner that determines the phase of the transmission data corresponding to the input signal, and a series of data determined by this determiner to be divided into data having a phase of an integral multiple of 90o and data having a phase of an odd multiple of 45o. a storage means for storing data in a state that allows the characters to be distinguished;
A first convolution thin sum of a plurality of pairs of variable tap gains having in-phase component and quadrature component values, a data set having a phase that is an integer multiple of the 9p, and the plurality of pairs of variable tap gains, Select two out of four values: the value of the in-phase component of the variable tap gain and the value obtained by reversing its magnetism, and the value of the orthogonal component of the variable tap gain and the value obtained by reversing its polarity. means for accumulating one of the two in an in-phase component accumulator as an in-phase component and the other as a quadrature component and accumulating a quadrature component in an accumulator as a quadrature component; and the second of the plurality of pairs of variable tap gains.
The sum of convolution products is obtained by calculating the accumulation of in-phase components and the accumulation of orthogonal components in the same manner as the above-mentioned means, and calculating the difference and sum of the accumulated results of the in-phase components and the orthogonal components. means for obtaining the multiplied components as an in-phase component and a quadrature component, respectively; two addition means for adding the in-phase component and quadrature component of the first and second convolution product sums, respectively; and these two addition means subtracting means for obtaining the input signal by subtracting the addition results from the in-phase and quadrature components of the received signal, means for subtracting the judgment result of the judge from the input signal to obtain an error signal; The value of the in-phase component of the signal, the value obtained by inverting its channel characteristic, the value of the orthogonal component of the error signal, the value obtained by inverting its polarity, the sum value and the difference value of the in-phase component and orthogonal component of the error signal, and the value of the difference thereof; Two values are selected from a total of eight values, each with the polarity of the two values reversed, one of the values is used to modify the value of the in-phase component of the variable tap gain, and the other is used to modify the value of the in-phase component of the variable tap gain. It includes means for modifying the values of the orthogonal components of the variable tap gain, and requires two multiplications to perform automatic equalization.
This is an automatic equalizer that only requires a few times. [Principle of the Invention] The present invention makes it possible to perform equalization with two multiplications regardless of the number of taps in data transmission using eight-phase phase modulation, which may involve a large number of multiplications as described above. The principle of the present invention will now be described. The multiplication required for normal decision-feedback automatic equalization is the convolution of the data in the second term on the right side of equation '1} with the tap gain. It is expressed as skin n○=1 sword 2 force ten eisu [mEk2Cm (public ``me-hiro'')]'3}. Here, k is the display ratio of the transmitted data point on a two-dimensional plane and 1
Let K2 be the set of m, which is the set of integer land phases of this public skin.
represents a set of m whose common nm is a topology of an odd multiple of a cow in a two-dimensional plane. In formula '31, the first term of the right-hand side, Kim nm, and the second term, Kimikawa me→mine, are either Earth 1 or Shij. By the way, the multiplication result of complex numbers C and A can be expressed as follows by notating the real and imaginary parts as Re{ } and lm{ }.C・A![Re{C}・Re{A} - -lm{C}・lm{A}] 10j[Re{C}・lm{A} 10lm{C}・lm{A}] '4} Here, the court official of the first term of the paste formula or {3 }Public publication/e- of the second term of the formula
If we consider j raw as A of the '4-formula and Cm of {3 wipes as C of the {4) formula, then if A=±1, it is C. A Re{C}・s starvation [Re{A}] If A=±j, it becomes C, A ni−lm{C}s starvation [lm{A}]. Therefore, the sum of products on the right side of the equation is performed by selecting and accumulating the real part or imaginary part of the tap gain and its polarity, and after completing the accumulation for M taps, It is obtained by performing multiple multiplications of the contents of the accumulator by ei - shou (10i). Therefore, the required number of multiplications is only two, regardless of the number of taps. Next, do the multiplication included in the correction of the tap gain in the formula.
Therefore, when the plate is a raw odd number, consider substituting it with the common nm, and if the data sequence {An} is random, this will keep the average value of the tap gain unchanged. Therefore, the magnitude of the correction coefficient that is equivalently thought to change the correction coefficient Q is determined by the convergence speed and steady tap gain fluctuations, deterioration effects, etc. Known to have no effect. Therefore, the multiplication in the second term of equation (2) is performed by selecting the real part and imaginary part of the error signal, as well as adding, subtracting, and polarity processing, and does not require any multiplication at all. This can be done by a simple shift in digital processing. Next, an embodiment of the present invention will be explained with reference to FIG. The in-phase component and quadrature component of the baseband signal are subjected to two-way synchronous detection in the synchronous detector 2 and sent out to the lines 3 and 4, respectively. The in-phase component of the feedback signal, which will be described later, is subtracted.Similarly, the quadrature component of the baseband signal flowing through the line 4 is subtracted by the quadrature component of the feedback signal, which will be described later, flowing through the line 8. The output, that is, the input signal to the determiner 9 corresponds to the real part and the imaginary part of the equalizer output signal Y shown by equation {1), respectively.The determiner 9 receives this input signal and makes a determination,
It is determined which phase of the eight phases the transmission data corresponding to this input signal was in, and the determination result is expressed as an integer from 0 to 7. Here the value o' is the signal point 10io,
Value 1'ma-kata (・10i) order 2'mao+i, value 3'maho (
-10i)・other 10io, value 5 is -Ryo(-1-i)
It is assumed that the value is output when the determination result is 6'o-i and 7' (1-i). An M-stage shift register 11 (
11-1, 11-1, ......11-M). M-stage shift register 11 stores the determination results of M-1 pieces of data sent in advance of the input data. The shift register 111 is connected to a first selector 12 formed of a logic circuit and a second selector 13 via this selector. M pairs of variable tap gains 14 (14-1, 14-2, . . . 14-M) are connected to the first selector 12. One of these pairs corresponds to the real part of C, ˜Cm of formula [1}, and the other corresponds to its imaginary part. First, the operations related to the numbers stored in the first stage 11-1 of the M-stage shift register will be explained. is variable tap gain 1
The value corresponding to the real part of the pair 4-1 is input to the register 7 connected via the switch 16 controlled by the clock pulse flowing through the line 15, and the value corresponding to the imaginary part is input to the register 7 in the same way. Enter 18. (ii) When the stored number is 2 or 3, input the value corresponding to the real part of the variable tap gain 14-1 to the register 8 connected via the opening/closing part turtle 6, and set the polarity of the imaginary part. The inverted value is input to the register 17. (iii) When the stored number is 4 or 5, input the value with the real part of the variable tap gain Kame-1 inverted in the gutter character to register Ki7, and input the value with the gutter character of the imaginary part inverted. is input into the register 18. When the stored number of Q is 6 or 7, the variable tap gain 14
- Input a value with the polarity of the real part of the turtle reversed into the register 18, and input the imaginary part into the register T. The above operation is ``When 0 or 1, A=1, when 2 or 3, A=j, 4
Or when A=-1 when 5 or A=-j when 6 or 7, input the real part and imaginary part into register 7 and register 181 when performing complex multiplication of C and ×A, respectively. Correspondingly, when the number stored in the last stage of the shift register 1 is an even number, the second selector quantity 3 selects the accumulators 19 and 2.
Select 0 and store the contents of register amount 7 in accumulator 19 (real number)
Then, the contents of register 18 are accumulated in accumulator 20 (imaginary number), and when the stored number is an odd number, accumulators 21 and 22 are selected, and the contents of register 7 are accumulated in accumulator 21 (imaginary number).
L to register 18 (real number) to accumulator 22 (imaginary number)
are accumulated respectively. Among the above operations, if the memorized number is an even number, it corresponds to the accumulation for m = 1 of the first term on the right side of the expression {3}, but if it is an odd number, it corresponds to the square brackets of the second term on the right side of the expression {3'. This corresponds to the accumulation for m=1 in . The series of selector and accumulation operations by the first and second selectors 12 and 13 described above relate to the numbers stored in the first stage of shift register 1, but similar operations can be performed for the number of stages of shift register 1. By repeating the number of times corresponding to , the sum of products with the first term on the right side of equation '3} and the sum of products in the square brackets of the second term are completed. However, this second term needs to be multiplied by eJ raw, so "to explain below, the accumulation result of the accumulator 21 is subtracted by the accumulation result of the accumulator 22 in the subtracter 23, and the result of the subtraction is is multiplied by the multiplier 24, and added to the accumulated result of the accumulator 22 by the adder 25, and divided by the skin sea bream rice multiplier 26' and multiplied by 1. The above operation is performed by formula [3] The content of the brackets in the second term on the right side is ei
It corresponds to obtaining the real part and imaginary part of the raw data. Therefore, the multiplication result (real part) of the multiplier 24 and the accumulator ig
If the cumulative result (real part) of is added in the adder 27, it is output to the line 6 as a feedback signal in-phase component indicating the real part of the glue equation, and the multiplication result (imaginary part) of the multiplier 26 and the accumulator When the 20 accumulation results (imaginary parts) are added in the adder 28, they are outputted to the line 8 as a feedback signal orthogonal component indicating the imaginary part of the Lake equation. Then, as described above, the in-phase and quadrature components of the baseband signals flowing through the lines 3 and 4 are subtracted in the subtracters 5 and 7', respectively. As described above, this subtracted baseband signal becomes the input signal of the determiner 9. The determiner 9 that receives this input signal not only determines the phase of the baseband signal as described above, but also determines the cosine component (in-phase component of the determination result) and sine component (orthogonal component of the determination result) of the phase. ) are output on lines 29 and 301 respectively. Therefore, from the in-phase component of the baseband signal flowing through the line 3, the cosine component signal flowing through the line 29 is subtracted by the subtracter 31, and the in-phase component of the error signal E appearing in the second term on the right side of equation (2) is transmitted to the line 32. The value is output, and after being shifted by the shifter 33 a number of times corresponding to the correction coefficient Q, the value is stored in the register 34. From the orthogonal component of the baseband signal flowing through the line 4 of the same machine, the above-mentioned sine component signal flowing through the line 30 is subtracted by the subtracter 35, the sine component of the error signal is outputted to the line 36, and the shifter 37 converts it into a correction coefficient. It is stored in the register 38 after being shifted the corresponding number of times. Here, the clock pulse flowing through the line 15 connects the switch 16 to the registers 34 and 38, and connects the switch 16 to the registers 34 and 38.
The selector 12 first inputs the real part of the complex multiplication of the error signal E and the transmission data A to the register 17 and its imaginary part to the register 18 in accordance with the contents of the final stage of the shift register 11 in the same manner as described above. . Then, the contents of register 7 are added to the contents of register 18 by an adder 39 on one side, and the contents of register 8 are subtracted from the contents of register 8 in a subtracter 40 on the other side. Adder 39 and subtractor 4 are connected to second selector 13, as are registers 17 and 18. This second selector 13 selects registers 17 and 18 when the final stage number of the shift register 11 is an even number,
increasing the values of the real part and imaginary part of the variable tap gain 14-1 by the contents of registers 17 and 18, respectively;
When the final stage number of the shift register 11 is an odd number, the adder 39 and the subtracter 40 are selected, and the variable tap gain is 1.
The values of the real part and imaginary part of 4-1 are increased by the addition result of the adder 39 and the subtraction result of the subtracter 40, respectively. The result is written to the variable tap gain 14 via the first selector 12 to modify the tap gain {Cm}. The modification of this variable tap gain is carried out sequentially in steps 14-2 and 14-2.
・・・・・・・・・・・・・・Conducted until 141M. By the above operations, brush writing is completed and each variable tap gain is successively set to the optimum positive value. Note that clock pulses 10 and 15 are sent out from a clock pulse generator 41.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. Explanation of symbols; 2 is a synchronization detector, 5 and 7 are subtractors t
9 is a judger, 11' is a shift register, 12 is a first selector, turtle 3 is a second selector, 14 is a variable tap gain,
16 is a switch, 17 and 18 are resistors. 19-2
2 is an accumulator, 23 is a subtractor to 2W multiplier, 25 is an adder, 26 is a multiplier, 27 and 28G are adders,
31 is a subtracter, 33 is a shifter t, 34 is a register, 35
37' is a subtracter, 37' is a shifter, 38 is a register, 39 is an adder, 48 is a subtracter, and 41 is a clock pulse generator. Figure 1

Claims (1)

[Claims] 1. In an automatic equalizer in a data transmission device using 8-phase phase modulation, an input signal obtained from the reception signal of this automatic equalizer is received and determined, and the phase of transmission data corresponding to the input signal is determined. A memory for storing a series of data determined by this determiner in such a state that data having a phase of an integral multiple of 90° and data having a phase of an odd multiple of 45° can be distinguished. means, a plurality of pairs of variable tap gains having in-phase component values and quadrature component values, and a first convolution product of the plurality of pairs of variable tap gains and a data set having a phase that is an integral multiple of 90°. The sum is selected from two of four values: the value of the in-phase component of the variable tap gain and a value with its polarity inverted, and the value of the orthogonal component of the variable tap gain and a value with its polarity inverted. means for accumulating one of the two in an in-phase component accumulator as an in-phase component and accumulating the other in a quadrature component accumulator as a quadrature component; A set of data with double the phase and a second set of the plurality of pairs of variable tap gains.
The sum of convolution products is obtained by calculating the accumulation of in-phase components and the accumulation of orthogonal components in the same manner as the above-mentioned means, and the difference and sum of the accumulated results of the in-phase components and the orthogonal components are calculated by 1. /√(
2) means for obtaining the multiplied components as an in-phase component and a quadrature component, respectively; two adding means for adding the in-phase component and quadrature component of the first and second convolution product sums, respectively; subtraction means for obtaining the input signal by subtracting the addition result by the addition means from the in-phase component and quadrature component of the received signal, means for subtracting the judgment result of the judge from the input signal to obtain an error signal; The value of the in-phase component of the signal and the value with its polarity inverted, the value of the orthogonal component of the error signal and the value with its polarity inverted, the value of the sum and the difference between the in-phase component and the orthogonal component of the error signal, and the value of the difference between these two. Select two values from a total of eight values, each with the polarity of two values reversed, and use one of the values to modify the value of the in-phase component of the variable tap gain, and use the other value to modify the value of the in-phase component of the variable tap gain. A decision feedback type automatic equalizer that includes means for modifying the value of an orthogonal component of , and requires only two multiplications to perform automatic equalization.