JPS6027976A - First-in first-out memory device - Google Patents

Abstract

PURPOSE:To perform data transfer between processors in a multiprocessor system at a high speed through small hardware, and give flexibility to access within one data segment by providing a state control circuit. CONSTITUTION:Every time a signal WT becomes active, the output of an ENDADR register 23 is selected by an SEL26 in a data transfer circuit and (m)- bit address information is sent to an RAM. At the same time, a counter 21 counts up, and if one data segment becomes full of data owing to a carry, a one-segment write end signal is outputted to add one to the contents of a register 23. Similarly, every time a signal OE becomes active, a counter 22 counts up by one to increase the contents of the register 24 by one. Consequently, a state control circuit 25 outputs a signal EMP showing a data empty state and a signal FUL showing a data full state. Thus, the data transfer is speeded up and access in one data segment is given flexibility.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a first-in, first-out memory device used as a data transfer means between a plurality of data processing devices.

2. Description of the Prior Art Structure and its Problems In recent years, due to advances in semiconductor technology, microprocessors have become extremely inexpensive. Therefore, instead of processing data in parallel using a plurality of microprocessors, it has become easier to adopt a structure that increases the processing performance of the system, that is, a multiprocessor structure. In a multiprocessor, it is necessary to exchange data between processors at high speed, and several data transfer means are used.

Below, a first conventional example of means for transmitting data between professionals and staff will be explained.

Figure 1 shows the configuration of a multiprocessor using a shared memory device, which is a conventional means of data transfer between processors. 8 is a local memory device, 8 is a shared memory device, 5 is a bus arbiter that arbitrates access to the shared bus CB, and 6 and 7 are buffers that connect/disconnect each local bus and the shared bus. The operation will be explained below. The CPU 1 stores the data to be transferred to the CPU 2 in the shared memory device 8, and after confirming that the data has been transferred to the Kuwabi, the CPU 2 imports the predetermined data into the local memory device 4 and performs processing based on it. Start. When this method is used, disadvantages include an increase in the amount of hardware needed to arbitrate and control access conflicts for the shared memory, and a decrease in performance due to software management of data segments to be transferred.

Next, a second conventional example of inter-processor data transfer means will be described. FIG. 2 shows the configuration of a multiprocessor using a first-in, first-out memory device, which is a conventional inter-processor data transfer means.
0 is a memory device, 11 is a conventional first-in first-out memory device,
It is interposed between the bus for CPU1 and the bus for CPU2.

The operation will be explained below.

CPU1 sends the data that it wants to transfer to CPU2,
After confirming that the first-in, first-out device 11 is not full, data is sequentially written to its input terminal. If the first-in first-out memory device is not empty, the CPU 2 sequentially reads data word by word from the output end and starts processing based on these data.

In the above configuration, the directionality of data transfer is fixed in terms of hardware, which causes the disadvantages of the first conventional example: an increase in the amount of hardware and a decrease in performance due to software management of data exchange. However, due to the inherent feature of the first-in, first-out memory device that it is possible to read only in the order in which it was written, it has the following drawbacks. That is, C
When the input data that becomes the processing eye position of PU2 is multiple words, the manual data of multiple words cannot be read in any order, so C
Since the PU 2 adopts a method of once transferring the contents of the first-in, first-out memory device 11 to the memory 10 that can be randomly accessed and then processing them, performance degradation may occur due to the transfer procedure.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and is capable of reducing the amount of hardware required for data transfer between multiprocessors, performing high-speed transfer, and providing data access within one data segment. An object of the present invention is to provide a randomly accessible first-in, first-out memory device.

Structure of the Invention The present invention provides a RAM that can read and write data, and a RAM that can read and write data in order to transfer data between data processing devices.
The first data segment register has the function of storing the first address to be read from M, the last data segment register has the function of storing the final address to be written from RAM, and whether the data in RAM is full or empty. This is a first-in, first-out memory device equipped with a state management circuit that indicates whether the data is being transferred or not.By enabling data writing and data reading within one data segment to be performed independently at register registers, it is possible to create and reference transfer data. It can be done efficiently.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a diagram for explaining a method of specifying a RAM address of a first-in, first-out memory device in an embodiment of the present invention. Figure 3a shows the structure of a RAM in a first-in, first-out memory device.
Data is stored in 2m data segments each having a memory capacity of n>1). FIG. 3 shows how to specify an address using the address line. The upper m bits specify a data segment address, and the lower n bits specify an address within the data segment.

FIG. 4 shows a first-time first-out memory device according to an embodiment of the present invention. In Figure 4, 1 is C on the data sending side.
PU, 2 is a CPU on the data receiving side.

20(,12m+”i)
AM, 12 an address decoder that generates a chip select signal in order to write data into the triCPUl or the RAM 20, 13 an address decoder that generates a chip select signal in order for the CPU 2 to read data from the RAM 20, 14 a data write; R/W control circuit that controls read timing; 16; address selector (hereinafter referred to as 5ELA) that selects one of the two n-bit address information output from CPU1 and CPU2; 17; is a data selector (
5ELD (hereinafter referred to as 5ELD), 15 outputs m-bit address information specifying the data segment address, and R
This is a data transfer control circuit that determines whether the data in AM20 is empty or full and controls writing and reading of data. 18 is a full status flag (hereinafter referred to as FULF) indicating whether the data in the RAM 20 is full or not; 19 is an empty status flag (hereinafter referred to as EMPF) indicating whether the data in the RAM 20 is empty or not.

The operation of the first-in, first-out memory device of this embodiment constructed as described above will be described below.

When data to be transferred is generated, the CPU 1 sends FULFl, which indicates whether the first-in first-out memory device is full.
If the FUL signal, which is the output signal of G, is not full, the write signal WR is activated, address information is sent to the address recorder 12, and the C81 signal is activated. The R/W control circuit 14 also controls the C output when the CPU 2 is accessing the FIFO memory device.
If the 82 signal is not active, the WT double signal is activated. Then, the WT double signal data transfer control circuit 15
A total of (m+n) bits of address information is applied to the RAM 20, including the m-bit data segment address information that is output when input to the CPU 1 or the n-bit address information that specifies the address within the data segment through the 5ELA 16. and sends write data through the 5ELD17. Thereafter, when the CPU 1 receives the AK multiplication signal from the R/W control circuit 14, it stops writing.

The CPU 1 randomly writes 1 into the data segment memory based on the n-bit address information.

Next, when the CPU 2 requires transfer data, an EMP indicating whether or not this first-in, first-out memory device is in an empty state is sent.
The output signal EMP of l9 is checked, and if it is not empty, the read signal RD double signal is activated, address information is sent to the address decoder 13, and the C82 signal is activated. Further, the R/W control circuit 14 activates the OE multiplication signal when C31, which is output when the CPU 1 is accessing the first-in, first-out memory device, is not active. Then, the sum (m+n) of the OE double signal, the m-bit data segment address information outputted when input to the data transfer control unit 15, and the n-bit address information that the CPU 2 arbitrarily specifies an address within the data segment through the 5ELA 16. Bit address information in RAM2
0 to read data through 5ELD17.

Thereafter, when the CPU 2 receives the AK multiplication signal, the R/W control circuit 14 stops reading. The CPU 2 randomly reads data from the memory within the data segment using n-bit address information.

FIG. 5 shows a block diagram of the data transfer control circuit 15 in the embodiment. 21 is a 2n-ary counter that increments by 1 each time data is written, and 22 is a 2n-adic counter that increments by 1 each time data is read. 23 is the final address of the data segment (hereinafter referred to as E
This is the final data segment register (hereinafter referred to as the ENDADH register) indicating the END address), and is
4 is a start data segment register (hereinafter referred to as TOPADH register) indicating the start address of the data segment (hereinafter referred to as ToP address). E
The ND address indicates the data segment address to be written next, and the TOP address indicates the data segment address to be read next. Reference numeral 26 denotes SEL for selecting which of the END address and the TOP address is applied to the RAM 20. 25 is a state management circuit that generates a FUL signal and an END signal indicating whether the data in the RAM 20 is empty or full.

The operation of the data transfer control circuit 15 of this embodiment configured as described above will be explained.

Every time the WT double signal becomes active, E from 5EL26
Select the output of the NDADR register 23 and load it into the RAM 2
0 iCm bit address information is sent and at the same time the 2n-adic counter 21 is incremented by 1, and when a carry occurs and the data in one data segment becomes full, a one data segment write end signal (hereinafter referred to as 0VFE signal) is output, and 1 is added to the ENDADH register 23. Similarly, each time the ○E times signal becomes active, the 2n-ary counter 22 is incremented by 1, and a carry occurs and all the data in one data segment is read out one data segment end number (hereinafter referred to as 0VFT (referred to as other number) is output and the contents of the TOPADH register 24 are incremented by 1. Then, in the EMP and FUL signal generation block 25,
Based on the conditions of the TOP address and the END address, the state management circuit 25 outputs an EMP signal indicating that the data is empty and an F'UL signal indicating that the data is full.

FIGS. 6 and 7 show two embodiments of the state management circuit 25. FIG.

FIG. 6 shows EMP depending on the presence or absence of data in the RAM 20.

In this example, 27 is an R-S flip-flop, and 28 is a TOP-END comparison circuit that compares the values of the TOP address and the END address. To explain the operation below, when the CPU 2 reads the data and the RD double signal becomes active, the EMP signal is output when the ToP address and the END address are equal, and conversely, the CPU 1 writes the data and outputs the WR double signal. When activated, V outputs a FUL signal when the TOP address and END address are equal. The example in Figure 7 is To
PADH register, ENDADi (same figure (a)
), carry flags CT and Ce are provided which are inverted every time the address exceeds 2m and reaches Q.

In the initial state, both CT and Ce are set to O.

As shown in the same figure (b), when the carry flags CT and Ce are equal, if the TQP address and the END address are equal, an EMP signal is output, and C/r and Ce are different and TO
When the P address and the END address are equal, a FUL signal is output.

As described above, according to this embodiment, by providing a data transfer control circuit that outputs an m-bit data sector address, FUL, and EMP signals, and a RAM having a capacity of 2111'h n words, a first-in, first-out Reading and reading operations from the memory device can be performed in any order within one data segment, and addresses can be specified independently by CPU1 and CPU2, making it extremely flexible to create transfer data or refer to received data. can be done.

In the embodiment, in the data control circuit shown in FIG. 5, the ENDADH register and the TOPADH register's 0VFE signal and 0VFT are output in the data control circuit 15 in terms of hardware when the binary counter is carried up. This was done by signals, but CPU1 and CP
In U2, ENDADH register and TOPAD
It goes without saying that a 1 data segment read end signal and a 1 data segment write end signal may be generated in order to count the H register.

In addition, in the detailed description of the present invention, the case of data transfer from CPU1 to CPU2 using the first-in, first-out memory device of the present invention was explained, but data transfer from CPU2 to CPU1 is also applicable to the first-in, first-out of the present invention. What memory devices can do is clear.

Effects of the Invention The first-in, first-out memory device of the present invention has a readable and writable R
AM, a final data segment register that has the function of storing the final data segment address to be written next to this RAM, a first data segment register that has the function of storing the first data segment address to be read next, and RA.
By providing a state management circuit that indicates whether the data in M is full or empty, data transfer between processors in Multi-Glo Nanosa can be performed at high speed with a small amount of hardware. Access within the data segment can be flexible,
Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an inter-processor data transfer device using a conventionally known common memory device, and FIG. 2 is a block diagram of an inter-processor data transfer device using a conventionally known first-in, first-out memory device. 2J43 Figure (a), (
b) is a diagram for explaining the RAM structure and addressing method of a first-in-first-out memory device in an embodiment of the present invention; FIG. 4 is a block diagram of a first-in-first-out memory device in an embodiment of the present invention; Figure 6 is a block diagram of the data transfer control circuit in the same embodiment, and Figures 6 and 7 (a), (
b) is a block diagram of a state management circuit in the same data transfer control circuit and a diagram showing address states. 16...Address selector (SELA), 17
...Data selector (SELD), 20...
...RAM. 23...Final data segment register (EN
DAD) register), 24...Top data segment register (TOPADH register L 25...
...State management circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 5 Figure 6 Figure 7

Claims (2)

[Claims] (1) A writable/continued RAM with a storage capacity of 2 rl'l + n words (m≧1.n≧1), and a first
When accessing from the port, the m memory has the function of storing the address information of the data segment to be accessed (having a capacity of 2n) in the RAM, storing the information, and incrementing the information when a 1 data segment write end signal is input manually. A final data segment register consisting of bits has a function of storing the address information of the data segment to be accessed in the RAM when accessing from the second port, and incrementing it when a read end signal of one data segment is input. inputting the information of the first data segment register consisting of m bits, the last data segment register and the first data segment register, and generating a status signal indicating whether the RAM is full of data or empty. a state management circuit that outputs;
first address information consisting of a total of (m+n) bits of m-bit address information supplied from the first port and m-bit address information of the final data segment register; and n bits supplied from the second port. and second address information consisting of a total of (m+n) bits of the m-bit address information of the first data segment register, and when accessing from the first port, the first an address selector that supplies address information to the RAM, and a data signal of the first port when accessing from the first port; line and the data signal line of the RAM are connected and supplied to the RAM, and during an access operation from the second port, the data signal line of the RAM is connected.
A first-in, first-out memory device comprising a data signal line of a port of the RAM and a data selector that connects a data signal line of the RAM. (2) A writable/continued RAM with a storage capacity of 2 m+n words (m≧1.n≧1), and a data segment to be accessed in the RAM when accessing from a write port ( When accessing from the read port, there is a final data segment register consisting of m bits which stores the address information of the address information (having a capacity of 2n) and increments when one data segment write end signal is input manually. a first data segment register consisting of m bits and having a function of storing address information of a data segment (having a capacity of 2n) to be accessed and incrementing when a read end signal of one data segment is input; and the last data segment. A status control circuit inputs the information of the register and the first data segment register, and outputs a status signal indicating whether data is full or empty in the 1J RAM, and is supplied from the write port. first address information consisting of (m+n) bits of m-bit address information of the last data segment register; n-bit address information supplied from the read port; and the first address information of the first data segment. Both of the second address information consisting of it (m + n) bits of the m-bit address information of the register are input, and when accessing from the write port, the first address information is also input from the read port. During an access operation, the address selector supplies second address information to the RAM, and during a write operation, one word of write data supplied from the write port is supplied to the RAM, and during a read operation, the R
A first-in, first-out memory device including a data selector that outputs one word of data read from an AM to a read port.