JPS6028343A - Packet transmission and reception system - Google Patents

Abstract

PURPOSE:To avoid un accessable state of a network only by the processing in terms of hardware by adding a pattern for initial setting of a packet reception circuit at least one of bits just before a head flag of a packet and just after a trailing flag. CONSTITUTION:It is supposed that a head flag FH102 is modified by a bit error on a ring form network. Since the head flag FH102 is not detected at first, a packet reception circuit 10 is brought into the packet arrival state when the trailing flag FT108 is inputted. Since an added pattern A109 is inputtednext on the other hand, the packet reception circuit 10 is applied with initial set. A packet transmission circuit 11 adds respectively added patterns A101 and A109 to the bit just before and just after the trailing flat FT108. Thus, the trailing flag FT108 is detected as an ineffective flag and circulated on the ring form network without giving any effect on the other packet.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a packet transmission/reception system, and particularly relates to a distributed deaf packet transmission/reception system in a distributed deaf packet switching device having a ring network using a token passing system. In the 1-switching device, a packet identification code called a flag pattern is provided at the beginning and end of the packet as a means of recognizing the packet strength, and as an address detection method, a method of checking whether the node is the own node or not is used. It is taken. Therefore, if the flag pattern is corrupted due to a bit error on the ring network, if the idle pattern of the transmission line is corrupted into a flag pattern, or if the address part is similarly corrupted, the address will not match the own node address, and other Processed as a packet destined for a node. As a result, there is a problem in that if invalid JL packets and packets continue to circulate on the ring network, access to the network becomes inoperable. In order to solve this problem, a first method is to provide a center stage 7 to erase defective packets even though the network includes a distributed packet switching device.

A second method has been considered in which the idle pattern is increased by +13 by repeating the flag pattern and the area other than the flag pattern is used as a packet.

However, in the first method, since the center station and other node stages differ in terms of hardware and software, if the center station goes down, there is a high possibility that the system will go down, so the merits of a distributed system are In addition, in the second method, since the idle pattern is a continuous repetition of the flag pattern, there is a drawback that switching control between the bucket area and the idle pattern area is complicated. This method eliminates the above drawback by adding a pattern for initializing the bucket receiving circuit to at least one of the buckets immediately before the first flag and immediately after the last flag. Another object of the present invention is to provide a bucket transmission/reception method that can avoid the inaccessible state of the network only by processing on hardware.

According to the present invention, in a distributed bucket switching device having a ring network using a token passing method, a packet receiving circuit is initially set immediately before the first flag of an output packet and immediately after the last flag of the output bucket. A packet transmission/reception system is obtained which is characterized in that the means for adding a pattern is a gold film.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram showing an embodiment of the bucket transmission/reception system of the present invention, and FIG. 2 is an output bucket former of the node station in FIG.

FIG.

In FIG. 1, the bucket transmission/reception system consists of node stages (hereinafter simply referred to as mates) 1.2.3 which are distributed bucket processing devices in a ring network. That is, the nodes 1, 2, and 3 are connected in a ring-like manner by branches 40, 41, and 42, which are one transmission path of the ring network. Each node 1, 2.3 has the same function. For example, node 1 has a bucket receiving circuit 10, a packet receiving circuit 1, a transmitting circuit 11, a sending/receiving port, and a sending/receiving circuit 12.
Equipped with. The packet receiving circuit 10 performs address detection based on the input packets from the branch 42, and depending on the result, the packet transmitting circuit lit or the transmitting/receiving buffer 12
0 packet transmission circuit 11 expansion bucket to transfer the bucket to
The state of the bucket receiver circuit 10 is monitored, its state transition is detected, and the bucket receiver circuit initial setting eyebrow pattern is added to at least one of the immediately before the head flag and immediately after the end flag and sent to the branch 40. In addition, the transmitter/receiver bar, 7A1
2 receives the bucket from the packet receiving circuit 10 just in case the destination address matches the own node address.

Next, in FIG. 2, the output bucket former.

The start flag PH102 indicates the start of the bucket, and the destination address DA103. Source address 5A104, bucket type code 0TL105. Data 1106. It has a configuration in which an error detection code FO8IQ7 and a tail flag Ft 108 indicating the tail of the bucket are arranged in order. Idle packets before and after the bucket area y)IPIOo, 110 are idle patterns of ring transmission paths other than the bucket area, and are arbitrary patterns other than the 7-lag pattern. Here, the first 7 lags Fu102. Both trailing flags F-10B are '
01111110", and all other patterns are 11" to identify flag patterns.
It is a promise that "OI+" is inserted after the 5-bit continuous pattern of "111110xx", that is, a bead pattern of "111110xx", and a bucket is added immediately before the first flag Fu102 and immediately after the last flag FT108. Pattern Al0I.

109 is defined as "11111111", but this is only a definition as a unique pattern of the idle pattern.

Next, the operation of this embodiment will be explained. The output of node 1 is input to node 2 via branch 40, similarly the output of node 2 is input to node 3 via branch 41, and its output is input to node 1 via branch 42, resulting in a unified overall output. When a bucket from the 0 branch 42 forming a directional ring network is manually input to node 1, p is added according to the additional pattern Al0L of the bucket.
The receiving circuit 10 is initialized and forced into a waiting state. Next, the packet receiving circuit 10 detects the arrival of the packet based on the received head flag FT1102 and starts address detection. Destination address DA1
When 03 matches the own node address, the packet receiving circuit 10 takes the packet into the transmitting/receiving buffer 12 and starts detecting an error in packets 1 and 1. If the destination address DA103 does not match the own node address, the packet is received, and the receiving circuit 10 receives the packet as is.

This is the tail flag FT10.
The process ends upon detection of 8. Next, the packet receiving circuit 10
is initialized again upon receiving the additional pattern A109.

In the packet transmitting circuit 11, when a transfer packet is input from the packet receiving circuit 10 while the self-node is not transmitting back or forwards, a new additional pattern Al0L,
109 are added immediately before the first seven lags Fn 102 and immediately after the last flag Ft 108 and transmitted to the branch 40. However, the packet receiving circuit 1 is the packet receiving circuit 11.
Monitor the state of 0 and its state transition is packet waiting state →
Pake.

It detects whether the packet arrival state is in the packet arrival state or the packet arrival state is in the packet waiting state, and if it is the former, the first flag Fn 10
If it is the latter, the additional patterns Al0I and 109 are added immediately after the tail flag FT108, respectively. When transmitting a packet from its own node, the packet transmitting circuit 11 automatically adds additional patterns A101 and 109 immediately before the first seven lags Fu 102 and immediately after the last flag FT108, respectively. At the time of this packet transmission, all signals inputted from the packet receiving circuit 10 to the packet transmitting circuit 11 are erased.

Assuming that the head flag PH102 has been altered due to a bit error on the ring network, first the head flag Fu102 cannot be detected, so the tail flag F
When T 108 is input, the packet receiving port path 10 enters the packet arrival state. However, then additional pattern A1
09 is entered manually, the packet receiving circuit 10 is initialized, and the destination address DA is set to the additional pattern A.
Since 109 is an abnormal pattern for the address area, the packet is transferred to the packet transmitting circuit 11, which can be the own node address. The packet transmitting circuit 11 detects that the state of the packet receiving circuit 10 changes from the packet waiting state to the packet arrival state to the packet waiting state before and after the last flag l"rios, and then changes the state immediately before and after the last flag FT 108. Additional patterns Al0I and 109 are added to each. Therefore, the tail flag FT 108 is transmitted to branch 40 in a form sandwiched between additional patterns A101 and 109. ), the same operation is performed, so the tail flag FT 108 is detected as an invalid flag, and the packet passes through the ring network without affecting other packets.

The operation is the same as that described above when the tail flag FT 108 is altered, the idle pattern is altered into a flag pattern, or the address field is altered into a flag pattern, so the explanation will be omitted.

It should be noted that all the constituent elements of the no)° station in this embodiment can be easily realized using conventional techniques.

In this embodiment, a ring-type net lake including three node stations is shown, but it goes without saying that the number of node stations may be any number.

As is clear from the above explanation, according to the packet transmission/reception method of the present invention, by adding the initial setting pattern of the packet receiving circuit immediately before the head flag and immediately after the tail flag of the packet, the center stage, It is possible to make a difference with simple hardware processing without the need for installation of a control panel or complicated switching control between the packet area and the idle pattern area.
Detect the packet and display the invalid flag9, so
This has the effect of avoiding the inaccessible state of the ring type network.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the packet transmission/reception system of the present invention, and FIG. 2 shows the output packet former of the node stage and node in FIG. FIG. In the figure, L 2,3 old-node stage, n,
10...Bucket receiving circuit, 11...
Pake. transmission circuit, 12...transmission/reception buffer, 4o; 41.42...Brunch, 100,110...
...Idle pattern IP, 101,109・old・
・Additional pattern A, 102・Old...First 7 lugs FH, 1
03...Destination address DA, ;104...
... Source address 8A1105 ... Packet type code OTL.

Claims (1)

[Claims] A ring type network using a token passing method. In a distributed packet switching device having a network, the packet is characterized in that means is provided for adding a pattern for initializing a packet receiving circuit to at least one of immediately before a head flag of an output packet and immediately after a tail flag of the output packet. Transmission and reception method.