JPS6028368A - Data transfer system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data transfer method for exchanging image signals between a facsimile device and an image signal storage device.

[Prior Art] In recent years, facsimile machines have been put into practical use that are capable of realizing various functions such as sequential report communication and time-specified transmission by adding both signal storage devices with large-capacity image memories to facsimile machines.

In such devices, a double buffer circuit shown in FIG. 1 has conventionally been used to exchange image signals between the facsimile device and the image signal storage device.

This double buffer circuit uses two line buffers Bl and B2 with a capacity that can store image signals for one main scanning line (for example, 2048 bits for B4 size and 1728 bits for A4 size) for facsimile equipment. switching circuit SWI on the side and the image signal storage device side.

This is switched by SW2 to increase the apparent data transfer speed.

That is, for example, when transferring an image signal from a facsimile device to an image signal storage device, the facsimile device switches the switching circuit Sw1 as shown by the solid line to store the image signal for one line in the line buffer B1, and then sends a message to that effect. Notify the image signal storage device.

As a result, the image signal storage device switches the switching circuit Sli+2 as shown in the broken line to store the image signal for a while, and at the same time, the facsimile machine switches the switching circuit SWI as shown in the broken line to send the image signal for the next line. is stored in line buffer B2. When this storage is completed, the image signal storage device is notified of this in the same manner as described above.

Then, the above steps are repeated in order to transfer the image signal to the image signal storage device.

In this way, while one side is writing to the buffer, the other side can read data from another buffer, thereby increasing the apparent data transfer speed.

By the way, as is well known, facsimile machines encode and transmit image signals, so the received signal is restored to the original image signal line by line and then transferred to the image signal storage device, and both signals are In order to effectively use the image memory in the storage device, both signals are encoded and data compressed before being stored in the image memory.

Generally, the encoding methods of a facsimile machine and an image signal storage device are often different, and the amount of information of an image signal differs for each line. Therefore, the time required for encoding and decoding image signals differs between facsimile machines and image signal storage devices, and even for the same device, the time required to encode and decode image signals differs.
Different for each line. Therefore, the data transfer rate also changes line by line.

For this reason, in the conventional data transfer method using a double buffer circuit, when the reading speed of both signal storage devices becomes faster than the writing speed of the facsimile device, or vice versa, it is difficult to transfer both data. When the transfer speeds are different, the processing with the faster data transfer speed is assigned, resulting in a problem of poor data transfer efficiency.

[Object] An object of the present invention is to solve the above-mentioned problems and provide a data transfer method that can absorb differences in data transfer speed by using a FIFO buffer.

[Configuration] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a facsimile machine l according to an embodiment of the present invention.
and image signal storage device (hereinafter simply referred to as storage device) 2
It shows.

In the figure, 1a is a scanner that plane-scans a transmission document and photoelectrically converts it to form a transmission image signal, 1b is a printer that prints a dot pattern, and 1d is a scanner that converts the output signal of scanner 1a into an 8-bit parallel signal. It is also a buffer that converts the output of the code compression/expansion circuit 1d into a serial signal and outputs it to the printer lb, and the code compression/expansion circuit 1d encodes and compresses the data added from the buffer lc and the management information addition circuit 1g to the modem. 1e
At the same time, the received data added from the modem 1e is decoded, data is expanded, and the data is output to the buffer IC.

1f is a network control circuit for controlling a transmission line network such as a telephone line network to establish and disconnect a transmission line; 1h is the above-mentioned scanner la, printer lb, buffer lc, code compression/expansion circuit 1d, modem le, and network A CPU (central processing unit) that controls the control circuit 1f and the management i-information addition circuit 1g, respectively.
, 11 is R that stores the program executed by the CPU 1h.
OM (read only memory), 1j is CPU1h
A RAM (Random Access Memory) is used as a work area, etc., and 1 is an external memory interface circuit for transmitting and receiving data between the facsimile device 1 and the storage device 2.

In addition, the buffer lc, network control circuit If, management information addition circuit 1g, CPU 1h, ROM 1i, RAM 1j, and external memory interface circuit 1 are connected to the system path line SB), and the data in the buffer lc is connected to the system path line SB). Writing and reading are performed by the cpuih via the SB.

2a is a facsimile interface circuit connected to the external memory interface circuit 1 described above to exchange data between the facsimile device 1 and the storage device 2;
In order to effectively use the image memory 2c, b is code compression for the image data added via the facsimile interface circuit 2a, and code compression for decoding and decompressing the data stored in the image memory 2c to restore the original image data. The decompression circuit and 2d are clock circuits.

2e is a cPU that controls the facsimile interface circuit 2a, code compression/expansion circuit 2b, image memory 2c, and clock circuit 2d, respectively; 2f is a ROM that stores the program executed by the CPU 2e; and 2g is a FIFO that forms the work area of the CPLI 2e and will be described later. The RAM and 2h for forming a buffer are input units consisting of a numeric keypad, fan keys, etc. This input section 2h
Each key is arranged on the operation panel (not shown) of the storage device 2.

Also, a facsimile interface circuit 2a.

Code compression/expansion circuit 2b, image memory 2c, clock circuit 2d
.

CPU2e, ROM2f, RAM2g and input section 2h
are connected to the internal path line IB, and all data exchange between these elements is done via the internal path line IB.

FIG. 3 shows a FIFO (first in, first out) buffer 20 formed in the RAM 2g. In this way, the FIFO
Buffer 20 consists of 32 line buffers, and further.

Each line buffer is provided with an error counter 22 corresponding to its line number.

The number of line buffers in the FIFO buffer 20 is set depending on the processing speed of the code compression/expansion circuits 1d and 2b of the facsimile device 1 and the storage device 2, and the amount of data to be processed. Further, arrow νP is a write pointer that indicates a line buffer in which an image signal is written in a write process described later, and arrow RP is a read pointer that indicates a line buffer from which an image signal is read in a successive process described later. The input pointer 1llP and the read pointer RP each have an address (reference address) in the RAM 2g of the corresponding line buffer as a value.

Considering the case where the facsimile device 1 restores the received signal to the original image signal with the above configuration and stores this image signal in the storage device 2, first, the CPU 1h of the facsimile device 1 must be in the image signal storage mode. , the system path line S
B, via external memory interface lk, facsimile interface 2a and internal path line IB,
The CPU 2e of the storage device 2 is notified.

Then, when the facsimile device 1 actually starts receiving, the code compression/expansion circuit 1d decodes the received signal for one line into the original image signal, and at the same time, the number of bits of the decoded image signal increases to the bits for one line. If the numbers do not match, it is determined as a line error and notified to the CPUIH. However,
Each time the decoding process for one line is completed, the CPU 1h transfers command information indicating whether or not a line error has occurred to the CPU 2e prior to the image signal.

Through the write process shown in FIG. 4, the CPU 2e first determines from the contents of the command information whether or not the next image signal to be sent is from a line containing an error (101);
If it is an error line, the error counter 22 corresponding to the write pointer l1lP is incremented by 1 (processing 102).

Then, the image signal that is subsequently transferred to the external memory interface 1 and via the facsimile interface 2a is stored in the line buffer indicated by the write pointer P (processing 103).

When the image signal of a line with an error is stored in the line buffer in this way, the write pointer vP is not moved, and therefore the stored contents of this line buffer are rewritten with the image signal of the next line to be transferred. .

Furthermore, if the transferred image signal is not from an error line and the result of judgment 101 is NO, and if the immediately preceding line is not an error (result of judgment 105 is YES), the error counter corresponding to the write pointer wP is 22 to 0 (process 2o6), and if the immediately preceding line is an error line (the result of judgment 105 is No), process 106 is skipped. Then, in the same way as described above, after this, the external memory interface lk and the facsimile interface 2a are
The image signal transferred via the line buffer is stored in the line buffer indicated by the write pointer IjP (process 107), and the position of the write pointer P is slightly updated for the next line (process 10).
8).

In this way, when writing the image signal to the FIFO buffer 2o, the image signal of the line with the error is rewritten with the image signal of the next transferred line, and the error counter 22 stores the image signal contained in the corresponding line buffer. The number of error lines is stored.

That is, for example, if the image signal of a normal line is transferred after two consecutive error lines, the image signal of the last normal line is stored in the line buffer, and the error counter 22 corresponding to this line buffer is stored. is "2"
is memorized. In addition, when there are consecutive normal lines, the error counter 22 corresponding to each line buffer is
"0" is stored in .

When reading the image signal from the FIFO buffer 20, the CP
U2e executes the continuation process shown in FIG.

First, it is determined whether the successive pointer RP is equal to the write pointer vP (determination 110). If the result of this judgment 110 is YES, there is no image signal to be read out in the FIFO buffer 20, so the process ends.

If the result of the judgment 110 is No, the value of the error counter 22 corresponding to the read pointer RP is checked to see if it is "0", that is, the line buffer indicated by the read pointer RP contains an error line. It is determined whether the content is not included or included (determination 111).

If the result of this judgment 111 is YES, it means that no error line is included, so the image signal of the line buffer indicated by the read pointer RP is read out (112), the successive pointer RP is advanced by one, and the next line buffer is read out. Specify (process 113).

If the result of the judgment 111 is NO, it means that the error line contains only the value of the error counter 22, and the CPU
2e decrements the value of this error counter 22 (
Process 115), the read pointer RP is returned to the previous line (line number is small) and the image signal of the previous line is read out. Process 116), the image signal of the error line is replaced with both signals of the immediately previous line.

In this case, process 113 is executed to set the read pointer RP to 1.
If you advance one step further, this means specifying the error line again. Therefore, the result of judgment 111 is YES.
Processes 115 and 116 are repeated until the image signal stored in the line buffer with one line number smaller than this line buffer is continuously stored in the error line by the number of error lines, that is, the value of the error counter 22. It is read out instead.

Now, it is not possible to write or read one line of image signals to or from the line buffer in one operation, and the CPU
2e writes to and reads from the line buffer the amount that can be transferred at one time by the pass line IB, for example, 1 byte (=8 bits).

In other words, if one line consists of 256 bytes (=2048 bits) of image signals, both signals for one line will be transferred in 256 write cycles or successive cycles. Processes 103 and 107 during the write process are processes that execute 256 write cycles, and processes 112 and 1 during the read process are processes that execute 256 write cycles.
16 is a process of executing 256 read cycles.

Therefore, in the embodiment described above, the write operation and the read operation to the FIFO buffer 20 are performed alternately for each byte of the image signal, so that the write operation and the read operation for each line buffer of the FIFO buffer 20 are simultaneously executed. This enables parallel processing.

As a result, the write processing and read processing described above are executed in parallel, and if the speed at which one line of image signals is written to the FIFO buffer 20 and the speed at which one line of image signals is read from the FIFO buffer 20 are different. However, this difference in speed has no effect on the writing and reading processes of the single image signal, and therefore, the facsimile device 1 and the storage device 2 can perform data transfer in an optimal state.

On the other hand, when the data stored in the image memory 2c is restored to the original image signal by the code compression/expansion circuit 2b and transferred to the facsimile device 1 via the facsimile interface 2a and the external memory interface 1k, in this case, one line of data is returned to the original image signal. No errors occur in the image signal. Therefore, among the write processes described above, processes 107 and 1
It is possible to write both signals to the FIFO buffer 20 with only 08, and the read processing judgment 1102 judgment 112
In steps 113 and 113, the image signal can be read out from the FIFO buffer 20.

Note that even in this case, the write process and the read process are executed in parallel in the same manner as described above. - By the way, in the above embodiment, 32 line buffers were configured, but the invention is not limited to this, and depending on the conditions, a FIFO/< sofa can be configured with 3 line buffers.

[Effects] As explained above, according to the present invention, data is transferred between the facsimile device and the image signal storage device via the FIFO buffer, so that the data of each of the facsimile device and the image signal storage device is transferred. Even if the processing speeds are different, image signals can be transferred in an optimal manner. Also,
Since the error counter is associated with the line buffer constituting the FIFO buffer to store the number of error lines, there is an advantage that image signals can be replaced with error lines very easily.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example of a data transfer system, FIG. 2 is a block diagram illustrating a device according to an embodiment of the present invention, FIG. 3 is a memory map diagram illustrating an error counter and a FIFO buffer, and FIG. FIG. 4 is a flowchart showing an example of write processing. FIG. 5 is a flowchart showing an example of the reading process. 1...Facsimile device, 2...Picture signal storage device,
ld, 2b... code compression/expansion circuit, lh, 2e...
CPU (central processing unit), li, 2f...ROM (
read-only memory), lj, 2g...RAM
(Random access memo January, Ik...external memory interface, 2a...facsimile interface, 2c...image memory, 20...FIFO
(First-in, first-out) buffer, 22...Error counter. 33 Figure 3 1 Figure 4 Figure 5

Claims (1)

[Claims] (1) In a data transfer method between a facsimile device that encodes and transmits image signals and an image signal storage device that encodes and stores one image signal, at least Three FIFO buffers are formed in sequence, and an error counter is provided corresponding to each line buffer. means for writing to each line buffer;
If there is an error, it repeatedly writes to the same line buffer until the error disappears, and also increments an error counter corresponding to this line buffer, and when reading both signals from the FIFO buffer, if the value of the error counter is 0. means for sequentially reading out image signals for each main scanning line from each of the line buffers in the order in which they were written; and, if the value of the error counter is 1 or more, the error counter is decremented, and the above-mentioned image signal corresponding to this error counter is A data transfer method characterized by comprising means for reading an image signal from the line buffer immediately before the line buffer. (2. In claim 1, the above FIF
A data transfer method characterized in that O buffers are formed in a circular manner.