JPS6030286A - Display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a display circuit in a character image information system such as Teletext or Videotex.

BACKGROUND TECHNOLOGY AND PROBLEMS First, the outline of a general television teletext receiver will be explained with reference to FIG.

ffi L figure nioiite, (11ha Ai frequency IHJ
aia II! lN A tuner circuit including up to a color video IJ9 detection circuit, (2) a video circuit that performs processing such as color demodulation, and (3) a color picture tube. When receiving normal television broadcasting, the color video signal from the tuner circuit (1) is supplied to the video circuit (2), where the three primary color signals are extracted, and this signal is supplied to the picture tube (3), where the color video signal from the broadcast li! ll1H! .

is played.

At this time, the color video signal from the tuner circuit (11) is supplied to the synchronization pulse forming circuit (4), and the vertical synchronization pulse VD + horizontal synchronization pulse Ho and clock GK are taken out, and the pulses VD and HD are biased. A circuit (5) is supplied to form vertical and horizontal deflection currents, which are supplied to the deflection circuit (6) of the picture tube (3).

In addition, GO+ indicates a microcomputer for generating 4Q color images by teletext broadcasting, (11) is a CPU with 8-bit parallel processing, and (12) is written with a program for reproducing color images by teletext broadcasting. R
OM, (13) is the RAM for the work area, (14) is the keyboard for selecting teletext, etc., (15) is the interface for analog human power, and these circuits (12)
~(15) connects the ζCPU (1) through the system bus (19).
1).

Furthermore, (I6) is one page (one screen) of teletext broadcasting.
(17) is a memory controller that forms address signals and read/write signals, etc.; and (18) is a display controller, which are interconnected and connected to the system (19) +-s N! The controller (17) is also supplied with pulses VD, Ho, and CK.

Then, ζ, when teletext is selected using the keyboard (14), this is notified to the CPU (11) by an interrupt.
Which teletext is needed is stored in RAM (13).

On the other hand, the color video signal from the tuner circuit (1) is supplied to the interface (15), the teletext signal during the 'ζζ direct blanking period is taken out, and this signal is once sent to the interface (15), and
The CPU (11) is informed by an interrupt that this teletext signal has been buffered. Then, the CPU (11) checks whether the buffered teletext signal is the signal of the page selected with the keyboard (14), and if it is not the signal of the page selected with the keyboard (14), it is ignored. However, the keyboard (1
When the signal is for the page selected in step 4), the buffered teletext signal is processed by the CPU (11) and supplied to the video RAM (16), and the write address signal and write signal are sent from the CPU (11). iJI] of the controller (17) and is supplied to the RAM (16).

At this time, the display data of the teletext signal selected by the keyboard (14) is sequentially loaded into the RAM (16) by the CPU (11) one scanning line at a time.

At this time, a directing address signal and a read signal synchronized with the vertical scanning and horizontal scanning are formed in the controller (17), and these signals are stored in the memory (16) in a time-sharing manner with respect to the signal 71. RA supplied
Display data of M (16) is read out sequentially in synchronization with vertical scanning and horizontal scanning, and this read display data is decoded into three primary color signals R, G, B and a luminance signal Y by a controller (18). (Each of the signals R-Y is a 1-bit serial signal, and the total "ζ" is 4 hints in parallel.) Then, the signal R-!1lllR~Y
However, video episode 128 (through 21 °C reception (! & tube (3)
), and therefore both color images of teletext are produced on the picture tube (3).

Below is an outline of a typical television text spinning wheel broadcast receiver.

By the way, the screen display of TV teletext broadcasting includes a energization display as shown in FIG. 2 and an Ili as shown in FIG.
There is a density table I<. In other words, the energization display (Figure 2)
In this case, one page of the screen consists of 248 dots horizontally x 204 dots vertically, and in the areal density display (Figure 3), one page of the screen consists of 496 dots horizontally x 408 dots vertically.
The information density of the IJ+ density display is twice that of the Hqs+ display in both the horizontal and vertical directions. In either display mode, one dot is represented by one bit, so the broadcasting station will have to transmit four times as much display data during high-density display as compared to during street display.

In addition, for receivers that use a medium-resolution picture tube (3), it is possible to use a JJn regular display, and a receiver that uses a high-resolution picture tube (3). For receivers with normal tables >l< and 11. It is possible to display both density and ζ. Therefore, ζ, the energization display b) is +iJ
If the memory cells and contents of the video RAM (16) of a capable receiver are schematically shown in FIG.
The memory cells and contents of M (16) will be blanked out as shown in Figure 3, and the capacity of the video RAM (16) of the receiver, which is capable of energization display and high-density display, will be reduced to 1 for only energization display.
1” capable receiver bidet number 1? This is four times the capacity of static (16).

However, as shown above, the capacity of the video RAM (16) is 4.
If the angle is doubled, as is clear from FIGS. 2 and 3, one focus point of the display data corresponds to four dosos I during the energization display. Therefore, if the video RAM (16) has a 1-bit/1-address memory, during normal display, the hint display data must be written to four addresses in the video RAM (16); Since the number of writes increases four times, the speed per stroke becomes slower by 1^゛. Furthermore, since the write address must be calculated four times for each l bit, the program for writing display data becomes complicated and also causes a decrease in the l'i'/i image speed.

Moreover, in reality, an 8-bit/1-address memory is used as the video RAM (16), and the horizontal 8 tons 1~ corresponds to one address, making the processing even more complicated. That is, as shown in FIG.
(11) transfers 1 byte of table data to the video RAM (
16) If you want to write 7F into two consecutive addresses, the processing program needs only a simple transfer instruction,
Although it is very simple, in reality, as shown in Figure 5, CP
Since U (11) must store 1 byte of display data bit by bit into 29 consecutive bits of video RAM (16), its processing program must include bit processing. It ends up being a double 5'1t thing. Therefore, the drawing speed becomes even slower.

OBJECT OF THE INVENTION The present invention attempts to solve these problems.

Summary of the Invention Therefore, in this invention, a video RAM (16)
has a capacity suitable for high-density display, but during normal display, display data is accessed only in the area of the video RAM (16), and 'ζ1ffi'/W display is performed.

FIG. 6 shows an example of the embodiment with a box, and in this figure, for simplicity, the controller (17) is a video RAM.
(16) shows the period during which display data is read.

In addition, in this example, the Noculus HD is multiplied by 2, and the clock CK is multiplied by 4 from 1 to 1.
! +i +I+i u; L non-interlaced display is “ζ”.

Then, the video RAM (16) has the capacity indicated in the +l'li density table box and has addresses specified by A□4 to Ao, and the toe address is as shown in the seventh screen. ]Rus A6~
Ao specifies the horizontal address, -1.address A14
86 specifies the vertical address.

In addition, (31) and (32) are constructed by D-flip-flop = ['flip-flop, (33)
.

(34) is the data selector, (35) is the RS flinozofrosob, the clock CK (frequency is 4 times) is supplied to the tritub flop (31), and the pulse H of the frequency
CK, and this frequency-divided pulse HcK is sent to the selector (
33) and the clock CK is supplied to the input 13 of the selector (33). Then, the output Q of the solve flop (35) is supplied to select 1 - human power S of the selector (33), and the output Y of the selector (33)
When S-“0”, Y=A; when S-“1”, Y=B
It is said that

Therefore, from the selector (33), the solve flop (
The °ζ pulse HCK or clock CK is taken out corresponding to the output Q of 35).

The output Y of this selector (33) is supplied to the clock input CLH of the horizontal address forming circuit (37). This formation circuit (37) is composed of a 6-bit counter, etc., and when the clock CLK and the clock CK (Jli) are supplied, it is synchronized with the dock CI (as shown in FIG. This is to form Ao to water − + l A ry 1 Rusu Detective 8 5 which changes every 8 clocks.Roughly speaking, at this time, the formation circuit (4)
This signal A5-A is supplied to the clear manual CLR of the forming circuit (37) by horizontal synchronizing pulses from
O is 1 in synchronization with clock GK for each horizontal scanning period.
0" to l"5:, 1.The horizontal address signal A5 to 〇 indicates the video RAM.
(16) is supplied to -to addresses A5 to Ao.

In addition, in the formation circuit (37), a read signal RD and a load signal LD are also formed for each change in the signals A5 to Ao and in synchronization with the clock GK, and the signal RD is applied to the read power R of the video RAM (16). Supplied.

Further, the pulse Ho (frequency is doubled) is supplied to the flip-flop (32) and divided into a pulse HHD with a frequency of "ζ", and this divided pulse HHo is supplied to the human power A of the selector (34). , Pulse HD is the selector (3
4) Supplied to manpower B.

Then, the output Q of the flip-flop (35) is supplied to the selector S of the selector (34), and from the output Y of the selector (34),
5) Corresponding to the output Q, °ζ pulse Ho or pulse HH
o is taken out.

The output Y of this selector (34) is supplied to the clock CLK of the vertical address forming circuit (3B). This forming circuit (38) is composed of a 9-bit counter, etc., and when a pulse HD is supplied as the clock CLK, a vertical address signal changes in synchronization with the pulse Ho as shown in FIG. 7E and F. A14-A
6. Furthermore, at this time, the vertical synchronizing pulse VO from the forming circuit (4) is transmitted to the forming circuit (38).
Vertical by being supplied with clear human power CLH? +
The response signals A14 to A6 are synchronized with the pulse HD in each vertical scanning period and take values of ζ10 to f407J. Then, this vertical address signal A14~
A6 is the upper address of the video RAM (16) A14~
A6 is supplied.

In addition, the cent input S and reset input R of the flip-flop (35) are connected to the system bus (19), and the flip-flop (35) is reset when it is connected to the CI) U (11) and the power is displayed. It is set when .

Furthermore, (41) shows an 8-bit parallel-in serial-output shift register to which display data from the video RAM (16) is supplied as data inputs A-H and input from the forming circuit (37). The load signal LD is supplied as a load input, and the output Y of the selector (33) is supplied as a clock input CLK.

According to such a configuration, in the case of quotient density display, CP
Flip-flop (35) is cented by U (11). Therefore, ζ, in this case, the selector (33), (
34), the clock CK and pulse HD are set to seleno I-
As shown in FIG. 7C and F, the clock CK and pulse Hoe:: are supplied to the ζ forming circuits (37) and (38), respectively, so that the clock CK and the pulse Hoe:: are supplied to the horizontal address signal which changes in degrees Celsius correspondingly. Ao and vertical address signals A14 to A6
is formed and supplied to the video RAM (16), and a read signal RD is supplied to the video RAM (1G).

Therefore, the video RA is synchronized with horizontal scanning and vertical scanning.
The display data obtained by filling out the M (16) force/ra display data 1 by 1 - at a time is supplied to the register (41).

At this time, the load signal LD is simultaneously supplied from the formation circuit (37) to the register (41), and the °C clock CK is supplied to the register (41) through the selector (33).
), the display data is taken out in series from the register (old), and the luminance signal Y is taken out as well.

Therefore, in this case, 496 of the video RAM (16)
/ 8 bytes (horizontal address) x 40B bytes (
Since reading is performed from the area of the vertical address), if the CPU (11) writes the display data of the 111 density table moon to this area, this will be taken out as the luminance signal QY.

On the other hand, in the case of the current display, the solve flop (35) is reset by the CPU (11). Therefore, in this case, Kuro Tsuku CK and Norusu H.

The pulses HCK and HHo of the frequency A of the selector (
33) and (34) to form the circuit (3).
7) , (3B) respectively, the progress of the horizontal address signals A5 to Ao and the vertical address signals A14 to 8G is as follows: Each 〃Nage ζ video RAM (1
At the same time, the speed of the read signal RD becomes A and is supplied to the video RAM (10).

Therefore, in this case, video I? A M (16)
Reading of display data for 1111 is performed from the area A at the end of the 1111 density table, that is, only in the second quadrant of the area of RAM (10) shown in the seventh image.

Then, the display data read from this second quadrant is supplied to the register (41), and the pulse IICK of frequency 2 is supplied to the register (4I). taken out.

Therefore, in this case, the CPLJ (11) puts the display data for the energization display into the second quadrant of the area (seventh image) of the video RAM (16), and this is taken out as the luminance signal Y. .

Thus, according to the present invention, it is possible to display 3111 and high density display, but in this case, especially according to this invention, the video RAM (Hi) guest room can be displayed in accordance with the high density table 21K. In addition to the magnitude, when lightning is displayed, the horizontal address signals A5 to Ao, (jp Naoko address signals A44 to
86 read signal RI) and 2 when density is displayed in II.
The display data is read out from area A of the video RAM (16) (therefore, when the power is on, the display data is simply read out from the corresponding address by one layer, just like when the high-density display is displayed. It is only necessary to enter the fifth
Bit processing as shown in the figure is not necessary, so the processing program can be simplified, and the drawing speed can be increased by +uj.Furthermore, the simple same 1?δ (31) ~
It is only necessary to add (35), the configuration is simple, and there is almost no cost amplifier.

In the neo example shown in FIG. 8, address signals A5 to Ao,
By setting Δ14 to A6 to 2 and using it as an address signal for energization display, the clock CK and pulse HD are supplied to the forming circuit (37) by shifting 1 bit by 1 bit.
(Similar to the example in Fig. 6, 5 to Ao to the horizontal address signal,
A read signal RI) and a load signal LD are formed, and a second load signal 1- of two frequencies of signals I and D is generated.
I L l) is also formed.

The signals A5 to A1 are the human power Ag of the selector (51).
- Human power A of the selector (51) supplied to AA.

is set to uO, and the signals A5 to A.

is supplied to the human power BF-BA of the selector (51).

Also, the output Q of the flip-flop (35) is connected to the selector (
51) is supplied to Select I/Human Power S. Therefore, when the output YF"YA of the selector (51) is S-"1", Yp"YA=A6 to AO, and s="
o”, it is shifted by 1 bit and becomes YF-“0”.
",Y.-YA"'As~A1.

``Then, this selector output Yp=YA is supplied to the lower addresses A5 to Ao of the video RAM (16). Therefore, when S="l", the horizontal address signal A
To O/Ao, the F-order addresses A5 to Ao of the video RAM (16) are addressed to addresses 10'' to 161'', but when S="0", addresses ``0'' to I'30J are addressed.

Similarly, the pulses I-ID and VD are supplied to the forming circuit (38) to form vertical address signals A14 to A6, and the signals A14 to A7 are supplied to the human power AH-AA of the selector (52). 1 to human power is set to "0", and signals AI4 to A6 are sent to the selector (52).
is supplied to the human power B+~B^, and the free knob flop (3
The output Q of 5) is supplied to the selection power S of the selector (52). Then, the selector output YI"YA is supplied to the video R at the upper addresses 814 to A6 of M(1(i). Therefore, as in the case of the horizontal -71 pulse, S-"'
1'', the upper addresses AI4 to A6 of the video RAM (+6) are set by the vertical address signals 14 to A6.
Address r407J is addressed to “0” and S-“
Oo", addresses 10" to I-203J are addressed.

Then, the read signal RI) from the forming circuit (37) is supplied to the video RAM (16).
) is supplied to the shift register (41).

Furthermore, the rotor signal HLD, Ll) is sent to the selector (53).
Input A. At the same time, the output Q of the free knob flop (35) is supplied to the selector S of the selector (53).
The selector output Y is supplied to the shift register (4
1) The load is supplied by hand. In addition, pulse H C
K and ri 1ko Tsuku CK is Serefta (54) human power A
, B, and the output Q of the flip-flop (35) is supplied to the selector (54) as the selection power S, and the selection output Y is supplied to the register (4I) glue 1:
Supplied to J-tsuku human power CLK.

Therefore, even in this example, when the crystal density table is
Display data is read from the area shown in FIG. 7A of AM (16), and during normal display, it is read out from the video RAM (16).
Since the display data is extracted from the area of the second quadrant in FIG. 7, the CPU (11)
It is only necessary to print the display data once, and therefore the drawing speed can be improved commercially.

Effects of the Invention Even when the CPU (if) writes display data during normal display to the video RAM (16) having a capacity for displaying areal density, the display data only needs to be written once. , the processing program can be simplified, and the drawing speed can be increased to three times faster.Moreover, it is only necessary to add a simple IC.

[Brief explanation of drawings]

1 to 5 and 7 are diagrams for explaining this invention, and FIGS. 6 and 8 are system diagrams of an example of this invention. a[ is a microcomputer, (■6) is a bidet No. 178 H5 (37) is a horizontal address forming circuit, and (38) is a vertical address forming circuit. Figure 2 Figure 3

Claims (1)

[Claims] a video RAM having a capacity corresponding to the first display mode;
When displaying in the first display mode, display data is read out from the corresponding first area of the video RAM and displayed, and when displaying in the second display mode, the display data is read out from the corresponding first area of the video RAM.
A display circuit configured to read display data from a part of the first area of the screen and perform display.