JPS603227A - Ecl signal transmission circuit - Google Patents
Ecl signal transmission circuitInfo
- Publication number
- JPS603227A JPS603227A JP58112244A JP11224483A JPS603227A JP S603227 A JPS603227 A JP S603227A JP 58112244 A JP58112244 A JP 58112244A JP 11224483 A JP11224483 A JP 11224483A JP S603227 A JPS603227 A JP S603227A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- circuit
- signal transmission
- power supply
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008054 signal transmission Effects 0.000 title claims description 21
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 230000005540 biological transmission Effects 0.000 claims description 9
- 102200049817 rs74626221 Human genes 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01825—Coupling arrangements, impedance matching circuits
- H03K19/01831—Coupling arrangements, impedance matching circuits with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Power Engineering (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
（ハ 発明の属する技術分野の説明
本発明は、ＢＯＬ信号伝送回路、特に、８０５回路で伝
送線路を駆動する場合に伝送線路の両端を終端する必要
のあるＦｉＯＬ信号伝送回路に関する。Detailed Description of the Invention (c) Description of the technical field to which the invention pertains The present invention relates to a BOL signal transmission circuit, particularly to a FiOL signal transmission circuit that requires termination of both ends of a transmission line when driving a transmission line with an 805 circuit. Regarding circuits.
（コ）従来技術の説明
第１図は従来のＥＣＬ信号伝送回路の一例を示す回路図
であシ、ＥＣＬ回路１０からＥＯＬ回路回路信号を伝送
する場合に用いられるＥＣＬ信号伝送回路を複数回路示
したものである。(J) Description of Prior Art FIG. 1 is a circuit diagram showing an example of a conventional ECL signal transmission circuit, and shows a plurality of ECL signal transmission circuits used when transmitting an EOL circuit signal from an ECL circuit 10. It is something that
伝送線路３０ｄＢＯＬ回路１０からＦｊＯＬ回路曜回路
号を伝送するためのものであり、第１図には示されてい
ないが実際には直流抵抗ｒをもっている。ＫＯＬ回路回
路／用力はそれぞれ抵抗ｙθを介して電源ＶＥｍに接続
されている。又、）Ｌｉｅ：Ｌ＋回回路の入力にはそれ
ぞれ抵抗ｇｏを介して電源ＶＴに接続されている。The transmission line is for transmitting the FjOL circuit number from the 30 dBOL circuit 10, and actually has a DC resistance r although it is not shown in FIG. The KOL circuits/utilities are each connected to the power source VEm via a resistor yθ. Furthermore, the inputs of the )Lie:L+ circuit are each connected to the power supply VT via a resistor go.
ＥＣＬ回路回路及びｍは一般的なＦｔＯＬ回路であるの
で、詳細な動作説明は省略するが、Ｆｉ（！Ｌ回路１０
では入力端子／／における端子電圧ｖｌｌと比較電圧稲
。Ｆとを比較して端子電圧■□、が高ければ出力端子／
コにおける端子電圧■ が高レベルＶ□、Ｈになｐ１低
２
ければ端子電圧■ が低レベル■１２Ｌになるよう動２
作する。ＥＯＬ回路回路間様な動作をする。一般に、高
レベルｖ１２Ｈは約−ｏ、ｇｖ、低レベルｖ１２Ｌは約
−／、ＡＶであり、ＶＩｎ）！ｉは−５，Ｊ Ｖ テあ
る。電源ｖＴは低レベル時と高レベル時の雑音余裕が等
しく実質的に最大となるように決められる。このために
、第２図に示すように、直流抵抗ｒによる電圧降下が高
レベル時と低レベル時で等しくなるように決められてい
る。すなわち、ＥＯＬ回路の出力電圧の低レベルを■。Since the ECL circuit and m are general FtOL circuits, a detailed explanation of their operation will be omitted, but Fi(!L circuit 10
Now, the terminal voltage vll and the comparison voltage at the input terminal //. If the terminal voltage □ is higher than F, the output terminal/
If the terminal voltage (■) at p1 reaches the high level V□, H, the terminal voltage (2) operates so that the terminal voltage (2) becomes the low level (■12L). It operates like an EOL circuit. Generally, the high level v12H is about -o,gv, the low level v12L is about -/,AV, and VIn)! i is -5, J V Te. The power supply vT is determined so that the noise margins at low level and high level are equal and are substantially maximized. For this reason, as shown in FIG. 2, it is determined that the voltage drop due to the DC resistance r is equal at high level and at low level. In other words, the low level of the output voltage of the EOL circuit is ■.
Ｌ、高レベルを■。１（とすると、雑音余裕の減少を低
レベルと高レベルで等しく実質的に最小とするためには
、Ｉｎ −（ＶＯＲＶＴ ）ｒ／（Ｒ−１−ｒ）＝（ｖ
Ｔ ＶＯＬ） ｒ／ （Ｒ＋ ｒ ） ＝工ＬｖＴ−（
ｖｏＨ＋■。Ｌ）／２ となり、低レベルと高レベルの
中間の値（約−／、ＪＶ）に選ばれていた。このために
、−／、２Ｖの電源ｖＴが必要となる欠点があった。L, high level■. 1 (then, in order to substantially minimize the noise margin reduction equally at low and high levels, In − (VORVT )r/(R−1−r) = (v
T VOL) r/ (R+ r) = Engineering LvT-(
voH+■. L)/2, which was chosen to be an intermediate value (approximately -/, JV) between low and high levels. For this reason, there is a drawback that a power supply vT of -/2V is required.
（３）発明の詳細な説明
本発明は従来の上記欠点を除去する為になされたもので
あり、従って本発明の目的は、実質的な雑音余裕を最大
にしておいて電源ｖＴを省くことができる新規なｌＩＣ
０Ｌ信号伝送回路を提供することにある。(3) Detailed Description of the Invention The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and therefore, an object of the present invention is to maximize the practical noise margin and omit the power supply vT. New IC that can be used
An object of the present invention is to provide a 0L signal transmission circuit.
すなわち、従来技術では実質的な雑音余裕を最大にする
にはＥＯ’Ｌ回路の出力電圧の高レベルと低レベルの中
間の電圧■。が必要であったが、本発明によシ実質的な
雑音余裕を減少させることなく、電源Ｖ、を省くことが
できるＥＯＬ信号伝送回路を提供するものである。That is, in the prior art, in order to maximize the practical noise margin, the voltage (2) is intermediate between the high level and low level of the output voltage of the EO'L circuit. However, the present invention provides an EOL signal transmission circuit that can omit the power supply V without substantially reducing the noise margin.
（ｌＩ）発明の構成
上記目的を達成する為に、本発明に係るＢＯＬ信号伝送
回路は、伝送線路の一端に接続された第１のＥＯＬ回路
の出力端子と、前記伝送線路の他端に接続された第一〇
ＥＯＬ回路の入力端子と、前記第１のＥＯＬ回路の出力
端子の第１状態を示す第１の出力電圧及び第一状態を示
す第一の出力電圧のいずれよりも低い電源電圧をもつ第
１の電源と、前記第１のＥＣＬ回路の出力端子と前記第
１の電源との間に接続された第１の抵抗とから成るｌ！
ｉＯＬ信号伝送回路が複数個存在するＥＯＬ信号伝送系
において、それぞれの前記第一のＥＯＬ回路の入力端子
と前記第１あるいは他の電源に接続されない１つの共通
線との間に接続された第一の抵抗群と、さらに前記共通
線と接地電位との間に接続されたコンデンサとを具備し
て構成される。さらに、前記第１の抵抗と第１の電源の
代９に電流源を用いた前記ＦｉＯＬ信号伝送回路も本発
明に含まれる。(lI) Structure of the Invention In order to achieve the above object, a BOL signal transmission circuit according to the present invention has an output terminal of a first EOL circuit connected to one end of a transmission line, and an output terminal connected to the other end of the transmission line. a first output voltage indicating a first state of the input terminal of the first EOL circuit and the output terminal of the first EOL circuit, and a power supply voltage lower than either of the first output voltage indicating the first state; and a first resistor connected between the output terminal of the first ECL circuit and the first power source.
In an EOL signal transmission system including a plurality of iOL signal transmission circuits, a first iOL signal transmission circuit connected between the input terminal of each of the first EOL circuits and one common line that is not connected to the first or other power source. and a capacitor connected between the common line and ground potential. Furthermore, the present invention also includes the FiOL signal transmission circuit in which a current source is used in place of the first resistor and the first power source.
（５） 発明の原理と作用の説明
ＢＣＬ信号伝送回路は低レベル、高レベルの状態があり
、これらが複数個存在すれば確率的には低レベル状態の
回路数と高レベル状態の回路数がほぼ１／２ずつとなる
。したがって、電源■１にははとんど電流が流れないた
めに電源ＶＴは不要であシ、その代り共通線の電位を安
定化させるためにコンデンサを追加しておく。(5) Explanation of the principle and operation of the invention BCL signal transmission circuits have low-level and high-level states, and if multiple of these exist, the number of circuits in the low-level state and the number of circuits in the high-level state will increase with probability. It will be approximately 1/2 each. Therefore, since almost no current flows through the power source 1, the power source VT is not necessary, and instead a capacitor is added to stabilize the potential of the common line.
（Ａ） 発明の詳細な説明
次に、本発明をその好ましい一実施例について第３図を
参照して具体的に説明する。(A) Detailed Description of the Invention Next, a preferred embodiment of the present invention will be specifically described with reference to FIG.
第３図は本発明の一実施例を示す回路構成図であシ、Ｆ
ｌＩＣＩ、回路１０，２０、伝送線路３０．抵抗ｔｉｏ
、！ｒ。FIG. 3 is a circuit configuration diagram showing one embodiment of the present invention.
lICI, circuits 10, 20, transmission line 30. resistance tio
,! r.
よ構成るＥＯＬ信号伝送回路が複数回路で構成されてい
るＥＯＬ信号伝送系を示したものである。This figure shows an EOL signal transmission system including a plurality of EOL signal transmission circuits.
共通線６０及びコンデンサ７０は本発明によるものであ
る。ＥＯＬ信号伝送回路は低レベル、高レベルの１つの
状態があるが、前記ＢＯＬ信号回路が多数あるために、
確率的には低レベル状態の回路数と高レベル状態にある
回路数はほぼ１／、ずっとなっている。これらの回路が
共通線ＡＯに接続されており、シたがって、たとえ共通
線ＡＯが電源ｖＴに接続されていたとしても電源ｖＴに
流れ込む電流あるいは電源■、から流れ出る電流はほと
んど零に近い。Common line 60 and capacitor 70 are in accordance with the present invention. The EOL signal transmission circuit has one state of low level and one high level, but since there are many BOL signal circuits,
In terms of probability, the number of circuits in a low level state and the number of circuits in a high level state are approximately 1/1. These circuits are connected to the common line AO, and therefore, even if the common line AO is connected to the power supply vT, the current flowing into the power supply vT or the current flowing out from the power supply 2 is almost zero.
このために、共通線６０の電位は前記電源Ｖ、がなくて
もＥＯＬ回路の低レベルと高レベルの中間の電位にほぼ
等しい電位となる。従って、前記の電源Ｖ、は不要とな
る。第３図においては本発明により電源Ｖ、が省かれて
いる。Therefore, the potential of the common line 60 becomes almost equal to the potential between the low level and the high level of the EOL circuit even without the power supply V. Therefore, the power supply V described above becomes unnecessary. In FIG. 3, the power supply V is omitted according to the invention.
さらに、コンデンサ７０は共通線１０の電位を安定化さ
せる為に、本発明により追加したものである。Furthermore, a capacitor 70 is added according to the present invention in order to stabilize the potential of the common line 10.
抵抗９００代りに定電流回路であっても同様の動作をす
るために、本発明の変形として、抵抗ｑＯ０代りに定電
流源を用いて回路構成し、本発明に含ませることができ
る。In order to perform the same operation even if a constant current circuit is used instead of the resistor 900, as a modification of the present invention, a constant current source can be used instead of the resistor qO0 to configure the circuit and it can be included in the present invention.
（７）発明の詳細な説明
本発明は、以上説明したように、複数のＥＯＬ信号伝送
回路の受端側の終端抵抗の一端を共通線に接続し、さら
に共通線と接地電位の間にコンデンサを接続する構成を
とることにより、終端用電源ｖＴを省くことができると
いう効果がある。(7) Detailed Description of the Invention As explained above, the present invention connects one end of the terminating resistor on the receiving end side of a plurality of EOL signal transmission circuits to a common line, and furthermore, a capacitor is connected between the common line and the ground potential. By adopting a configuration in which the terminals are connected, there is an effect that the termination power supply vT can be omitted.
第１図は従来技術によるＦｉＯＬ信号伝送回路を示す図
、第２図は従来技術を説明するための詳細図、第３図は
本発明の一実施例を示す回路構成図である。
１０．２０・・・ＫＯＬ回路、３０・・・伝送線路、１
０・・・共通線特許出願人 日本電気株式会社
代 理 人 弁理士 熊谷雄太部
第１図
１３５−
第２図FIG. 1 is a diagram showing a FiOL signal transmission circuit according to the prior art, FIG. 2 is a detailed diagram for explaining the prior art, and FIG. 3 is a circuit configuration diagram showing an embodiment of the present invention. 10.20...KOL circuit, 30...transmission line, 1
0...Common line patent applicant NEC Corporation Agent Patent attorney Yutabe Kumagai Figure 1 135- Figure 2
Claims (1)
ＣＩ７回路の出力端子と、前記伝送線路の他端に接続さ
れた第一のＢＯＬ回路の入力端子と、前記第１のｖａｈ
回路の出力端子の第１状態を示す第１の出力電圧及び第
一状態を示す第一の出力電圧のいずれよりも低い電源電
圧をもつ第１（ＤＴＬ源と、前記第１の８０５回路の出
力９Ｌ子と前記第１の電源との間に接続された第１の抵
抗とから成るＥＣＬ信号伝送回路が複数個存在するＫＣ
Ｌ情号伝号伝送系いて、それぞれの前記第一の８０５回
路の入力端子と前記第１あるいは他の電源に接続されな
い１つの共通線との間に接続された第２の抵抗群と、さ
らにｆｉｉＪ記共通線と接地？［位との間に接続された
コンデンサを有するととを特徴としプこＥＯＬ信号伝送
回路。 （−２） ｒｉｉｆ記第１の抵抗とＭｉＪ記第１の電源
の代りに電流源を用いたことを特徴とする特許請求の範
囲第（１））項に記載のＥＯＩ、信号伝送回路。(1) 1st OD connected to one end of the transmission line]1iI
an output terminal of the CI7 circuit, an input terminal of the first BOL circuit connected to the other end of the transmission line, and the first vah
a first (DTL source) having a power supply voltage lower than either a first output voltage indicative of a first state of an output terminal of the circuit and a first output voltage indicative of the first state; A KC including a plurality of ECL signal transmission circuits each including a 9L element and a first resistor connected between the first power source and the first resistor.
a second resistor group connected between the input terminal of each of the first 805 circuits and one common line not connected to the first or other power source; fiiJ common line and ground? [An EOL signal transmission circuit characterized by having a capacitor connected between the terminal and the terminal. (-2) The EOI and signal transmission circuit according to claim (1), characterized in that a current source is used in place of the first resistor in Riif and the first power source in MiJ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58112244A JPS603227A (en) | 1983-06-21 | 1983-06-21 | Ecl signal transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58112244A JPS603227A (en) | 1983-06-21 | 1983-06-21 | Ecl signal transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS603227A true JPS603227A (en) | 1985-01-09 |
Family
ID=14581846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58112244A Pending JPS603227A (en) | 1983-06-21 | 1983-06-21 | Ecl signal transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603227A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4727265A (en) * | 1984-07-20 | 1988-02-23 | Hitachi, Ltd. | Semiconductor circuit having a current switch circuit which imparts a latch function to an input buffer for generating high amplitude signals |
-
1983
- 1983-06-21 JP JP58112244A patent/JPS603227A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4727265A (en) * | 1984-07-20 | 1988-02-23 | Hitachi, Ltd. | Semiconductor circuit having a current switch circuit which imparts a latch function to an input buffer for generating high amplitude signals |
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