JPS603568A - Timing signal generating device - Google Patents

Abstract

PURPOSE:To generate the next timing signal without a hindrance even in case no timing signal exists, by generating the next selecting signal by driving a selecting signal generating circuit by an open data. CONSTITUTION:A multiplexer 31 selects and fetches one of delay data divided and held by FFs 21-24, basing on a selecting signal generated from a counter 15, and gives it to a very small delaying circuit 17. The very small delaying circuit 17 applies a very small delay to a timing signal formed by a timing forming circuit 16, basing on the given delay data, and outputs a timing signal of a high resolution. A multiplexer 32 selects and outputs one of open data divided and held by FFs 25-28, basing on the selecting signal generated from the counter 15. A decoder 12 distributes it to each FFs 25-28 and supplies it as a reset signal. An OR circuit 13 supplies the timing signal and the open data to the counter 15, and drives counting. In this way, other timing signal can be generated without a hindrance even in case a timing signal corresponding to some reference timing signal is not generated.

Description

DETAILED DESCRIPTION OF THE INVENTION <Background of the Invention> The present invention relates to a timing signal generation device that is used, for example, to test semiconductor integrated circuits and that generates various timing signals having different phases with respect to a reference timing signal. .

For example, when testing logic circuits such as semiconductor integrated circuits, it is necessary to generate various timing signals with different phases and apply them to the logic circuit under test in response to a reference timing signal that is repeatedly generated at a predetermined period. be. An example of a conventional configuration of such a timing signal generator is shown in FIG. In this example, in order to obtain a timing signal with a phase larger than the period of the reference timing signal with high resolution, the delay data is spatially divided into multiple parts, and in this figure, the descendants are divided into four parts. ing.

In FIG. 1, reference numeral 16 denotes a timing forming circuit, which generates timing signals having various phases synchronized with a clock signal applied from a terminal 45, using the reference timing signal applied from a terminal 44 as a reference. For a specific example of this timing forming circuit, see Japanese Patent Application No. 57-97, for example.
415 G is detailed. Reference numeral 17 denotes a minute delay circuit, which generates a timing signal G formed by the timing forming circuit 16 based on the given delay data. A timing signal with a resolution of 1 is generated at terminal 46. 21 to 24 are D-type flip-flops, and the delayed data from the terminal 41 is commonly applied to the D terminal. 11 is a decoder which selects one of the D-type flip-flops 21 to 24 according to selection signals supplied from terminals 42 and 43;
A clock signal is supplied to the clock terminal of the selected flip-flop 1 at a timing determined by the reference timing signal applied from the flip-flop 4.

A multiplexer 31 selects one of the delay data from the flip-flops 21 to 24 based on the selection signal given from the counter 5 and supplies it to the minute delay circuit 17. The counter 5 is given a timing signal from the minute delay circuit 17, and by counting this =3-timing signal, it increments the selection signal supplied to the multiplexer 31G.

The operation of this conventional timing signal generator will be explained with reference to FIG. The reference timing signal 104 is applied from the terminal 44 to the timing forming circuit 16 at a predetermined period, and the timing forming circuit 16 generates various timing signals 106 corresponding to each reference timing signal in synchronization with the clock 105 from the terminal 45. Output. Delayed data 101 is applied from terminal 41 to flip-flops 21 to 24 in a time slot with the same period as reference timing signal 104, and selection signal 102.10 is applied from terminal 42.43.
The signal is taken into the flip-flop selected by No. 3 at a timing based on the reference timing signal.

In other words, the delay data D+, D2, Da, etc. are divided for each time slot and sent to each flip-flop 2.
The output data 107, 108, 109, 110 of each flip-flop 21 to 24 is data whose phase differs by one time slot and has a valid period of four time slots as shown in the figure. - The delay data space-divided into four pieces is given to the multiplexer 31, where the selection signal 1 from the counter 15 is sent to the multiplexer 31.
15.116, one of the delay data is sequentially selected and applied to the minute delay circuit 17G, and based on the delay data Q, a minute delay is added to the timing signal 106 from the timing forming circuit 16, and the delay data is A resolution timing signal 111 is generated.

That is, when generating the timing signal M1 based on the reference timing signal R1, the selection signal 115.
116 are both at low level, the output 107 of the flip-flop 21 is selected by the multiplexer 31, and the delay data D1 is provided to the minute delay circuit 17G. The minute delay circuit 17 converts the timing signal L1 from the timing forming circuit 16 into a minute time d based on the delay data D1.
The timing signal M1 delayed by the amount of time is output. The counter 15 is incremented by the timing signal M1, the selection signal 115 becomes high level, the output 108 of the flip-flop 22 is selected by the multiplexer 31, and the delay data D2 is provided to the minute delay circuit 17. As a result, the timing signal L2 corresponding to the reference timing signal R2
Then, a timing signal M2 to which a slight delay determined by the delay data D2 is added is output. By sequentially repeating this operation, a timing signal with a resolution higher than that of the clock 105 can be obtained. Furthermore, in this timing signal generator, if the timing signal to be generated is delayed from the reference timing signal by one time slot of the reference timing signal,
For example, even in the case of the timing signal M2 corresponding to the reference timing signal R2G in the figure, delay data is spatially divided into G timeslots and held for more than one time slot, so this may cause problems. It is possible to obtain timing signals without any need.

However, in this conventional timing signal generator,
If the corresponding timing signals are not generated for three reference timing signals, for example, in FIG. 2G, the timing signal L3 corresponding to the reference timing signal R3,
If settings are made so that M3 does not occur, subsequent operations cannot be performed normally. That is, in this timing signal generation device, the counter 15 is incremented by the timing signal 111 to select the delay data for the next timing signal. Therefore, for example, when the timing signal M3 is not generated, Since the delay data D4 used by the timing signal M4G is not selected and the delay data D3 remains given to the minute delay circuit 17, the selection order is distorted, so that subsequent operations will not be performed normally. .

As described above, conventional timing signal generators have the disadvantage that they cannot be set to generate other timing signals without generating a timing signal corresponding to a certain reference timing signal (heating). there were.

<Objectives of the Invention> 1. The present invention aims to eliminate the above-mentioned drawbacks and provide a timing signal generating device that does not cause any trouble in operation even if the timing arming signal is open.

<Summary of the Invention> According to the present invention, a signal (open data) indicating that a timing signal corresponding to a certain reference timing signal is not generated is given to each time slot corresponding to that reference timing.

This open data is divided into n spaces Q and held by the open data division circuit, similarly to the case of delayed data. The space-divided open data is given to a multiplexer, and one open data is selected and taken out by a selection signal from a selection signal generation circuit. The retrieved open data resets the open data division circuit that divides and holds the open data, and also advances the selection signal generation circuit to output delay data for the next timing signal.

Therefore, even if a timing signal corresponding to a reference timing signal is not generated, open data indicating that it is not generated is output, and the selection signal generation circuit is incremented by the open data to proceed to the next step. In order to generate the selection signal, delay data for delaying the next reference timing signal and the corresponding timing signal is taken out and applied to the minute delay circuit. Thus, according to the present invention, even if a timing signal is missing, the next timing signal can be generated without any problem.

<Embodiments of the invention> The configuration of one embodiment of this invention is shown in FIG.

This example shows a case in which delayed data is spatially divided into four parts, as in the case of FIG. With reference to FIG. 3, parts common to those in FIG. 1 are indicated by the same numbers. 25~ in the figure
28 is a D-type flip-flop, and the open data from the terminal 47 is commonly given to each D terminal. 21 to 24 are flip-flops similar to those in FIG. 1, to which delay data from the terminal 41 is commonly applied.

These D-type flip-flops 21 to 28 may be replaced with latch circuits. The decoder 11 transfers the reference timing signal applied from the terminal 44 to a pair of flip-flops 25 and 21.26 based on the selection signal from the terminal 42.43.
・Distributed to 22.27, 23.28, and 24 respectively and supplied as clock signals.

31 is a multiplexer, and flip-flops 21~
1 of the delayed data divided and held by 24
One is selected and taken out based on the selection signal generated by the counter 15 and applied to the minute delay circuit 17. The minute delay circuit 17 adds a minute delay to the timing signal formed by the timing forming circuit 16 based on the supplied delay data, and outputs a high-resolution timing signal. 32 is a multiplexer, and a flip-flop 25
-28G One of the divided and held open data is selected and output based on the selection signal generated by the counter 15. A decoder 12 distributes the open data output from the multiplexer 32 to each of the flip-flops 25 to 28 based on the selection signal generated by the counter 15, and supplies the divided data as a reset signal.

13 is an OR circuit, which supplies the timing signal output from the minute delay circuit 17 and the open data output from the multiplexer 32 to the counter 15, and increments the count of the counter 15.

The operation of this embodiment will be explained with reference to FIG. FIG. 4 shows the operation when no timing signal corresponding to the reference timing signal R3 is generated. The timing forming circuit 16 receives a reference timing signal 104 applied from a terminal 44 and a clock 105 applied from a terminal 45.
As a result, a timing signal 106 having a resolution of the clock cycle is generated and transmitted to the minute delay circuit 17. At this time, a timing signal corresponding to the reference timing signal R3 is not generated. Delayed data 101 is commonly applied to each flip-flop 21 to 24 from terminal 41.
9 Ibx o y h@(7)%Ngi,”Dl,
D2, D3, . . . are taken into each flip-flop selected by the selection signals 102 and 103 at the timing determined by the reference timing signal.

Therefore, the delay data 101 is spatially divided into G timeslots and taken into the flip-flops 21 to 24G, and the delay data 101 taken into each flip-flop is
07.108.109.110 have starting phases that differ from each other by one time slot, and have a valid period of four time slots.

Open data 120 indicating that a certain reference timing signal will not generate a corresponding timing signal is provided from a terminal 47, and each flip-flop 25 to
Common features can be added to 28. Similar to the case of delayed data, this open data is taken in by the flip-flop selected by the filter selection signals 102 and 103 at the timing determined by the reference timing signal. In this example, since the timing signal corresponding to the reference timing signal R3 is not generated, the open data 120 becomes 12-high level in the time slot corresponding to Ra. Therefore, open data] 20 is a flip-flop 27 at the timing of the reference timing signal R3.
, and its output 121 becomes high level.

Selection signals 115 and 116 generated by counter 15 are commonly applied to multiplexers 31 and 32 and decoder 12. Since the selection signals 115 and 116 are both at low level at the start of operation, the multiplexer 31 selects the output data 107 held in the flip-flop 21 and supplies it to the minute delay circuit 17. Therefore, the delay data D1 corresponding to the reference timing signal klG is given to the minute delay circuit 17, and the minute delay circuit 17 receives the delay data DI from L1&this in the timing signal 106 formed by the timing forming circuit 16. A timing signal M1 to which a minute delay determined by G is added is generated. The timing signal M1 is output from the terminal 46 (via the 20R circuit 13) and is applied to the counter 15 for counting. Therefore, the selection signal 115 becomes high level, and the multiplexer 31 outputs the output 1 of the logic flop 22.
．． 08 and sends the delay data D2 to the minute delay circuit 17.
give to The minute delay circuit 17 is a timing forming circuit]
A timing signal M2 is generated by adding a minute delay determined by the delay data D2G to the timing signal L2 from 6.

The counter 15 is incremented by the timing signal IVh and generates the next selection signal 115 and 116.

Therefore, the multiplexer 31 selects the delayed data lJ3 and applies it to the minute delay circuit 17, and at the same time, the multiplexer 32 selects the open data 121 held in the flip-flop 27 and outputs it (
122). This output open data 122 is given to the decoder 12 and then given to the counter 15 via the OL circuit 13. Based on the selection signal from the counter 15, the decoder 12 supplies a reset signal to the reset terminal of the flip-flop 27 at the timing of the open data 122. Therefore, the output 121 of the flip-flop 27 is at a low level. The open data 122 and the selection signals 115 and 116 applied to the counter 15 at the same time advance to the next state, and the delay data D4 corresponding to the reference timing signal R4G is selected by the multiplexer 31 and applied to the minute delay circuit 17. In this case, the timing for generating the reset signal from the decoder 12 to the flip-flop 27 is as follows:
Open data 122 is sent to counter 1 via OR circuit.
5 and a selection signal 115.5. 116 is assumed to be earlier than the timing of change. OR circuit 13
, because of the operation delay time of the counter 15. If the selection signal 115, 116 changes earlier than the reset signal is output, the reset signal is output to the next flip-flop 28.
, so that the flip-flop 27 cannot actually be reset. In order to perform this operation reliably, a delay circuit may be inserted between the multiplexer 32 and the OR circuit 13, for example.

In this way, when the timing signal corresponding to the reference timing signal R3 is not generated, the counter 15 does not increment by 1 timing signal, but it is incremented by the open data output from the multiplexer 32. , the next delay data D4 is given to the minute delay circuit 17, and the next timing signal M4 can be generated.

Thereafter, the timing signals M5, M6...
is generated. In this embodiment, the purpose of resetting the flip-flop holding the open data by the output 122 from the multiplexer 32 is to ensure that the open data does not interfere with operation even if the open data spans two or more consecutive time slots. This is to prevent any damage. In other words, if the setting is made so as not to generate timing signals corresponding to successive reference timing signals of 2 or more, the open data will be at the level of the corresponding time slots of 2 or more. The output level of the corresponding flip-flops 25 to 28, which spatially divide and hold open data, is held. Each flip-flop holds four quimslots of time-open data when no reset signal is applied. Therefore, the selection output 122 of the multiplexer 32 remains at the Akane level even if the selection of the output of the flip-flop holding open data is switched, and the count of the counter 15 is not incremented, so that the subsequent selection order of delayed data is normal. It will no longer be. Therefore, in this embodiment, the flip-flop holding open data is reset when the open data is selected and output by the multiplexer 32.

As described above, according to the present invention, even when a timing signal corresponding to a certain reference timing signal is not generated, other timing signals can be generated without any problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional timing signal generating device, FIG. 2 is a time chart for explaining the operation of the timing signal generating device shown in FIG. 1, and FIG. 3 is a timing chart according to the present invention. FIG. 4 is a block diagram showing the configuration of one embodiment of the signal generation device, and is a time chart for explaining the operation of the timing signal generation device shown in FIG. 3. 11.12; Decoders 21 to 28; D-type flip-flops 31.32; Multiplexer 15; Counter 16; Timing forming circuit 17; Micro delay circuit 19- Fig. 4-368-

Claims (1)

[Claims] High resolution is achieved by providing two timing signals formed at a timing equal to one cycle of a clock with respect to a reference timing signal and giving a minute delay based on delay data generated for each time slot. In a timing signal generator that obtains a timing signal, A. Divide the delayed data into two spaces into n pieces (n is an integer greater than or equal to 2) whose phase differs by one time slot, and B. data indicating that if a predetermined reference timing signal is manipulated, a timing signal corresponding to the reference timing signal will not be generated (hereinafter referred to as "open data"); ■An open data division circuit that divides and holds each time slot into n spaces with different phases, and a delayed data selection circuit that selects one of the n pieces of delayed data space-divided by the C and J1 data division circuits. and D. An open data selection circuit that selects one of the open data space-divided into n pieces by the open data division circuit, and E. The selected open data is selected by the open data selected by the open data selection circuit. F. A reset circuit that selects and resets the open data division circuit that is generating open data; F. The open data selected by the open data selection circuit causes the delayed data selection circuit, the oven data selection circuit, and the reset A timing signal generation device comprising: a selection signal generation circuit that advances each selection of a circuit;