JPS6036614B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to instruction code prefetch control for an information processing apparatus that is microprogram controlled.

In a microprogram-controlled information processing device, in order to decode and execute an instruction, the instruction is first read from the main memory and stored in an instruction buffer.

At this time, the instruction buffer generally stores a plurality of prefetched instruction words to improve processing speed. Thereafter, only the instruction word to be executed is taken out from the instruction buffer at the address specified by the instruction counter, the instruction code is decoded, and the control memory is accessed. Therefore, the instruction counter always detects the length of the instruction to be executed and determines from where in the instruction buffer the instruction should be read next. Generally, commands are stored in the command buffer for each chairperson.

However, the command word is not necessarily limited to one chairman, and it is common for command words of half word length or two word length to be mixed. Therefore, it is necessary to select the instruction code through an instruction word alignment circuit so that the instruction code can be determined based on the value of the instruction counter. After performing these series of operations, the control memory is accessed and each instruction word is executed by a series of microinstructions. If there is no branch in the instruction sequence, there is no problem with this series of operations, but once an instruction with a branch operation is executed, the instruction in the instruction buffer cannot be used and the instruction is read out from the main memory again. A need arises. Conventionally, even in this case, the instruction word is temporarily stored in the instruction buffer as described above, and then the instruction word is read out from the instruction buffer at the address indicated by the instruction counter, the instruction code is decoded through the instruction word alignment circuit, and the control memory is stored. I was accessing it.

In this operation, when an instruction word that involves a branch operation is executed, a considerable amount of time is required until the next instruction word is executed. That is, there is a drawback that it takes too much time to store the instruction word of the branch destination in the instruction buffer, then read it from outside the instruction counter and decode the instruction code. The present invention has been made in order to solve the above-mentioned drawbacks of the conventional art, and therefore, an object of the present invention is to store an instruction word of a branch destination in an instruction buffer at the time of a branch operation, and also store an instruction code of the instruction word. It is an object of the present invention to provide a new information processing device controlled by a microprogram, which is provided with a branch destination instruction code register to speed up instruction code decoding and control storage access during a branch operation. The above object of the present invention is to provide an instruction word buffer that preempts and holds successive instruction words, an instruction word counter that stores the address of the next instruction word to be executed, and an instruction word buffer that stores instructions from the instruction word buffer by the output of the instruction word counter. an instruction word alignment circuit that formats the read instruction word; and a branch destination instruction code register that sets and holds an instruction code portion of write data when the write data to the instruction word buffer is a branch destination instruction word. , furthermore, a branch detection circuit that detects whether the execution result of the instruction word currently being executed is a branch, and an instruction code from the instruction word alignment circuit and an instruction code from the branch destination instruction code register based on the output of the branch detection circuit. An instruction code selection circuit is provided which selects the instruction code of the instruction word in the instruction word buffer when successive instructions are executed one after another, and selects the instruction code of the instruction word in the instruction word buffer to be executed first after a branch operation. This is achieved by an information processing device that selects an instruction code in the branch destination instruction code register and provides the instruction code as data related to an instruction start address in control storage.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the device of the present invention shown in Fig. 1, each word is 4 bytes, there are two types of instruction words: one word length (4 bytes) and half word length (2 bytes), and the instruction code is in the first byte of the instruction word. shows.
An embodiment of the present invention includes an instruction buffer 1 that preemptively holds a plurality of consecutive instruction words, and a control memory that stores a plurality of microinstructions that operate one of the instruction words in this instruction buffer in detail. 6. A control memory address generation circuit 5 that provides an address for executing a microinstruction in the control memory 6 corresponding to an instruction word; an instruction word counter 7 that stores the address of the next instruction word to be executed; an instruction currently being executed; an instruction word length detection circuit 8 that detects the instruction length from the instruction code of the instruction word; an instruction word alignment circuit 2 that reads out the instruction word to be executed next from the instruction word buffer 1 and positions the instruction code of the instruction word in the most significant byte; When the write data to buffer 1 is a branch destination instruction word, the branch destination instruction code register 41 sets and holds the instruction code part of the write data, and the branch destination instruction code register 42 also stores the instruction word currently being executed. a branch detection circuit 9 that detects whether the execution result is a branch; the output of the most significant byte of the instruction word alignment circuit 2, that is, the instruction code; and any one of the branch destination instruction code register 41 and the branch destination instruction code register 42. It consists of an instruction code selection circuit 3 that selects one instruction code.

Next, the operation will be explained.

A plurality of instruction words are prefetched from the main memory (not shown) through signal lines 111 to 114 and stored in the instruction word buffer 1, but when reading out the instruction word buffer 1, two words can be read at the same time. It is a command word buffer.

That is, when the word address field of the instruction word counter 7 is "n", bytes 0, 1, 2, 3 at address n of the instruction word buffer 1
are output to signal lines 101, 102, 103, and 104, respectively, and bytes 0, 1, 2, and 3 at address n11 are output to signal lines 105, 106, 107, and 108, respectively. The instruction word counter 7 is a counter that stores the address of the instruction word buffer 1, and the lower two bits are used as a byte address field indicating the position of a byte in a word, and the other parts are used as a word address field.

Now, when there is a prefetched instruction in the instruction buffer 1, the next instruction to be executed is read from the instruction buffer 1 at the address indicated by the instruction counter 7.

At this time, the instruction words read out from the instruction word buffer 1 are aligned by the instruction word alignment circuit 2 according to the value of the byte address field of the instruction word counter 7. In other words, if the byte address field is “0”, bytes 0 and 1 of the instruction word to be executed next
, 2, 3 are signal lines 101, 102, 103, 104, respectively.
Therefore, in the instruction word alignment circuit 2, the signal line 101
The contents of ~'04 are output to signal lines 201-204. Furthermore, when the byte address field is "10", bytes 0, 1, 2, and 3 of the next instruction word to be executed are connected to the signal line 10, respectively.
3, 104, 105, and 106, the instruction word alignment circuit 2 outputs the contents of the signal lines 103 to 106 to the signal lines 2.
01 to 204, and the command words are arranged so as to be executable. Therefore, byte 0 of the instruction word to be executed next, that is, the instruction code, is sent to the instruction code selection circuit 3 through the signal line 201, and if the branch detection circuit 9 does not detect a branch, the instruction code selection circuit 3 The signal line 201 is selected as the code, the control memory address generation circuit 5 generates the address of the control memory 6 corresponding to the instruction code, and the control memory 6 is accessed through the signal line 501. As a result, a series of microinstructions are executed one after another to complete the execution of the instruction word.

When the completion of execution of the instruction word is detected, the instruction word length detection circuit 8
The value of the instruction word cursor 7 is updated according to the output. That is, if the currently executed command is half a word long, the command counter 7 is incremented by 12, and if it is one word long, the command counter 7 is incremented by 14. Access word buffer 1. When the instruction words are executed one after another as described above, the prefetched instruction words are read out from the main memory one after another when the instruction word buffer 1 becomes empty, and are passed through the signal lines 111 to 114. Written to instruction word buffer 1. However, some commands to be executed involve branching operations.

At this time, there is little chance of branching to the instruction word in the instruction word buffer 1, and it is generally necessary to read out the instruction word again from the main memory. Now, when the control memory 6 is accessed and an instruction is executed in the process described above, if the instruction is an instruction word that involves a branch, the branch detection circuit 9 operates to detect whether or not it is a branch.

If there is no branch, the instruction word sequentially read from the instruction word buffer 1 is executed next as described above. However, when the branch detection circuit 9 detects that a branch occurs as a result of instruction word execution, the instruction word buffer 1
A branch destination instruction word and a plurality of instruction words following it are written from the main memory through signal lines 111 to 114.
At the same time, byte 0 of the first word of the instruction read from the main memory is stored in the branch destination instruction code register 42.
is stored through signal line 111. Also, byte 2 from the main memory is stored in the branch destination instruction code register 41 through the signal line 113. Thereafter, the branch detection circuit 9 detects the output signal line 4 of the branch destination instruction code register 42 when the branch destination address indicates a one-word mirror field address.
21, and output signal line 4 of the branch destination instruction code register 41 when the branch destination address indicates a half-word length boundary address.
11 is selected by the instruction code selection circuit 3.
Issue commands through 01. Therefore, the instruction code of the instruction word to be executed first after a branch operation is selected by the instruction code selection circuit 3 as the contents of either the branch destination instruction code register 41 or the branch destination instruction code register 42, and the signal line 30
1 to the control memory address generation circuit 5, the corresponding address of the control memory 6 is generated, and the control memory 6 is accessed thereby. As a result, the branch destination instruction word is executed. In subsequent operations, since multiple instructions following the branch destination instruction are stored in advance in instruction buffer 1, the above process is repeated, and a series of instructions including instructions that involve branching are sequentially executed. be done. Note that the branch destination instruction code register stores only the instruction code, and for operands included in the instruction word, the contents of the instruction word buffer 1 are used when the instruction is executed. As an embodiment of the present invention, we have described the case where each command word is 4 bytes long and has two types of command words: one chairman and half word length.
It goes without saying that the word size, type of command word length, structure, etc. can be freely selected and do not impose any constraints on the present invention.

As explained above, the present invention provides a branch destination instruction code register in addition to the instruction word buffer, and uses this register to bypass the instruction word buffer during a branch operation. This has the effect of speeding up access to control memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Instruction word buffer, 2...Instruction word sorting circuit, 3
...Instruction code selection circuit, 41...Branch destination instruction code register, 42...Branch destination instruction code register, 5...Control storage address generation circuit, 6. ... Control memory, 7 ... Instruction word counter, 8 ... Instruction word length detection circuit, 9 ... Branch detection circuit, 101 to 901 ... Signal line. Figure 1

Claims (1)

[Claims] 1. In an information processing device that has an instruction word buffer that preempts and holds a plurality of consecutive instruction words, and starts execution of an instruction by reading control memory from an address related to an instruction code in the instruction word, an instruction word counter that stores the address of the instruction word to be executed next; an instruction word alignment circuit that formats the instruction word read from the instruction word buffer according to the output of the instruction word counter; and an instruction word alignment circuit that formats the instruction word read from the instruction word buffer; and write data to the instruction word buffer. A branch destination instruction code register that sets and holds the instruction code portion of the write data when is a branch destination instruction word, and a branch detection device that detects whether or not the result of execution of the currently executed instruction word is a branch. and an instruction code selection circuit that selects an instruction code from the instruction word alignment circuit and an instruction code from the branch destination instruction code register based on the output of the branch detection circuit, so that consecutive instruction words are When executing, the instruction code of the instruction word in the instruction word buffer is selected, and for the instruction word to be executed first after the branch operation, the instruction code in the branch destination instruction code register is selected and the instruction code is controlled. An information processing device characterized in that data is provided as data related to a storage instruction start address.