JPS6038850A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6038850A
JPS6038850A JP58147085A JP14708583A JPS6038850A JP S6038850 A JPS6038850 A JP S6038850A JP 58147085 A JP58147085 A JP 58147085A JP 14708583 A JP14708583 A JP 14708583A JP S6038850 A JPS6038850 A JP S6038850A
Authority
JP
Japan
Prior art keywords
layer
conductor
conductor layer
wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58147085A
Other languages
Japanese (ja)
Inventor
Hitoshi Nagano
永野 仁
Tadashi Matsumoto
忠 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58147085A priority Critical patent/JPS6038850A/en
Publication of JPS6038850A publication Critical patent/JPS6038850A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48Insulating materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/981Auxiliary members, e.g. spacers
    • H10W72/983Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the fall-off of a wiring reaching to a conductor from a semiconductor element and the increase of the electrical resistance of the wiring by constituting a conductor layer for the wiring by a first conductor layer having strong adhesive properties to an insulating layer and a second conductor layer, which is formed on the first conductor layer and mainly comprises aluminum. CONSTITUTION:Conductor layers 4 for wirings consist of a conductor layer 11 composed of a polysilicon layer or a metallic layer having strong adhesive properties to an insulating layer 2 and a conductor layer 12 composed of aluminum or a material mainly comprising aluminum, and a conductor 5 consisting of gold or a material mainly comprising gold is connected to the conductor layer 12. Consequently, even when a hole is formed in the conductor layer 12 by giving heat, the state in which the conductor layers 4 for the wirings are connected to the conductor 5 is kept because the conductor layer 11 is shaped, and the electrical resistance of the wirings reaching to the conductor 5 through the conductor layers 4 for the wirings from a semiconductor element does not increase. There is possibility of which the conductor 5 falls off together with one part of the conductor layers 4 for the wirings because the conductor layer 11 has strong adhesive properties to the insulating layer 2 and a section between the conductor layer 11 and the conductor layer 12 has solid adhesion.

Description

【発明の詳細な説明】 本発明は、半導体素子4形成しCいる坐り体基板」ニに
絶縁層が形成され、εの絶縁層重に半導体素子に連結さ
れ、nつバラ1一部をイi ”lる配線用導体層が形成
され、その配線用脅体層のバット部に金または金を主成
分と・)る祠11 rなる導線が連結されている?1′
力1本具1.u、lの改良に関りる。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides an insulating layer on which a semiconductor element 4 is formed and an insulating layer connected to the semiconductor element with an insulating layer layer of A conductor layer for wiring is formed, and a conductor wire made of gold or gold as a main component is connected to the butt part of the threat layer for wiring.
1 force 1 tool 1. Involved in improving u and l.

従来のこのJ、う4i半ンク捧1−置は、第′1図に小
すように、半導体片、子(図小1! f )を形成して
いる半導体基板1土に、例えばS!0+でなる絶縁図2
が形成され、−で−の絶縁F!21−に、゛1′導体素
子に連結され、11つバット部3をイjりる配線用導体
層4が形成され、ての配線用導体Fj/1のパラ1〜部
3に、金まlこは金を1−成分とりる材料でなる導線5
が、ボンデングによつC連結されている考品成をイjし
ている。<1i1j、61よ、1色j家性保護膜である
As shown in FIG. 1, this conventional J, 4i, and half-ink mounting is performed by applying, for example, S! Insulation diagram 2 consisting of 0+
is formed, and the insulation F! 21-, a wiring conductor layer 4 connected to the ``1'' conductor element and extending beyond the 11 butt parts 3 is formed, and a gold metal layer is formed on paras 1 to 3 of each wiring conductor Fj/1. This is a conductive wire 5 made of a material containing gold as one component.
However, it has a structure that is C-connected by bonding. <1i1j, 61, one color j family protective film.

この場合、配線用う9体層4μノ′ルミニウム(なる。In this case, nine layers for wiring are made of 4 μm aluminum.

しかしながら、このJ、うな!111成を右ηる21′
5!j休装置の場合、はと、4のバット部3に、導線5
をホンデングして後、熱処理がなされる場合、導Pit
 5の金と、配線用導体層4のアルミニウムとが反応し
て、ALIAl+ 、Δu2 △1などの合金が形成さ
れ、このため、配線用導体層4内に、?”1号7で示1
′J:うに、空孔が生じ、電気的抵抗が増大Jるという
欠点を有していた。
However, this J, Una! 21' to the right of 111
5! In the case of a j-rest device, the conductor 5 is attached to the butt part 3 of the dovetail 4.
If heat treatment is performed after heating, the conductive pit
The gold of No. 5 reacts with the aluminum of the wiring conductor layer 4 to form alloys such as ALIAl+ and Δu2 Δ1. ”1 No. 7 indicates 1
'J: Sea urchins had the disadvantage of forming pores and increasing electrical resistance.

また、配線用導体層4がアルミニウムでなる!こめ、配
線用導体層4ど絶縁層2どの間の接6カが弱く、このた
め、導線5が、絶縁層2からMl fillし易く、と
くに上述したように空孔7が形成されるどき、導線5が
配線用導体層4の一部ととbに、11;2落してしまう
欠点を有していた。
Moreover, the wiring conductor layer 4 is made of aluminum! Therefore, the contact between the wiring conductor layer 4 and the insulating layer 2 is weak, so that the conductive wire 5 is easily filled with Ml from the insulating layer 2, especially when the holes 7 are formed as described above. There was a drawback that the conductor 5 fell onto a part of the wiring conductor layer 4.

J、って本発明は、上述した欠点のない、新ノM4ド1
′導1ホ其置を提案せんとりるもので、以下述べるとこ
ろから明らかとなるであろう。
J, the present invention is a new M4D1 without the above-mentioned drawbacks.
This will become clear from what follows.

第2図は本発明による半導体装i4の一例を示し、第1
図どの対応部分には同一符号を付して詳細ill!明は
省略するが、第1図に示寸構成において、その配線用導
体層4が、ポリシリコン層でなる、またはタンタル、ク
ロム、[リブi゛ン、タングステンなどの絶縁層2に対
して弾接る1′1を右し、且つ耐熱性をh FJる全屈
層てなる■11本層11と、その導体層11上に形成さ
れた)アルミニウムまたはアルミニウムを主成分とJる
祠ねでなる導体層12とからなり、そして導線5が、導
体層12上のバラ1へ部3に連結されていることを除い
−C,第1図の暢:含と同仔の構成を右する。
FIG. 2 shows an example of a semiconductor device i4 according to the present invention.
Corresponding parts in each figure are given the same reference numerals for details! Although the details are omitted, in the configuration shown in FIG. (11 layers 11 and a conductor layer 11 formed on the conductive layer 11) consisting of aluminum or aluminum as a main component. 1, except that the conductive wire 5 is connected in part 3 to the rosette 1 on the conductor layer 12.

以」ニが、本発明にJ、る半導体1411イの一例(1
4成である。
This is an example of the semiconductor 1411 (1) according to the present invention.
It is four generations.

このような構成によれば、配線用導体層4が、導体層1
1及び12どからなり、でして導!5が導体層12に連
結8れCいるので、たとえ、導線5をη体層12に連結
りるどさに、導体層12に第1図に場合のように空孔が
形成されCも、導体層11を有しているので、配線用導
体Fi4が導線5に連結されている状態に変りはイjく
、また、心体層11が絶縁層2どの間で強接着ツノを有
しているので、第1図の場合のような剥は1を生じない
According to such a configuration, the wiring conductor layer 4 is the same as the conductor layer 1.
It consists of 1 and 12, and is the guide! 5 is connected to the conductor layer 12, so even if a hole is formed in the conductor layer 12 as in the case shown in FIG. Since it has the conductor layer 11, the state in which the wiring conductor Fi4 is connected to the conductor wire 5 is not changed, and the core layer 11 has a strongly adhesive horn between the insulating layer 2. Therefore, peeling as in the case of FIG. 1 does not result in 1.

従って、第4図に示゛Jように、第1図に承り半導体装
置と比較して1りれた特1ηをず1する。
Therefore, as shown in FIG. 4, the characteristic 1η, which is 1 less than the semiconductor device shown in FIG. 1, is reduced by 1.

なお、上jホにd3いては、右イホ唐12が11層であ
る場合につきjホべたが、第3図に承りように、2層1
3及び14とすることt)Cきる。この場合総13及σ
゛14はそれぞれTi及びptとし得る。
In addition, when d3 is placed in the upper jho, the right Iho 12 is the 11th layer, but as shown in Figure 3, the 2nd layer 1
3 and 14 t) C cut. In this case, a total of 13 and σ
14 may be Ti and pt, respectively.

その仙、4〜光明の精神をl1ii !Jることなしに
、種々の変型、変更をなし看るであろう。
That immortal, 4~ The spirit of light is l1ii! Various modifications and changes may be made without further ado.

【図面の簡単な説明】[Brief explanation of drawings]

7A1図は、従来の半府体・伐:ζ°′iを小111線
n’i 1lJi面図である。 第2図及び第3図は、本発明にJ、る半39休4・装置
を示り゛路線的断面図である。 出願人 L1Δ(電イjr 7[j話公社代理人 弁即
上 11」中1冶 特許庁長官 若 杉 和 夫 殿 1.事件の表示 特願昭58−147085号2、発明
の名称 半導体装置 3、補正をする者 事件どの関係 特許出願人 住 湧 東京都千代IJ′1区内幸町1丁目1番6号名
 称 (422)日本電信電話公社 代表者 真 藤 恒 4、代理人 住 所 〒102 東京都千代田区麹町5丁目7番地 
秀和紀尾井町TBR820号 5、補正命令の日付 昭和58年11月29日6、補正
にJ:り増加する発明の数 なし7、補正の対象 明I
II書の図面の簡単な説明の欄B、補正の内容 (1) 明細書中箱5頁16行1・・・・・・・・・路
線的rg1面図である。」の次に、下記を加入づる。 「第4図は、第1図に示J従米の半導体装置及び第2図
に示す本発明にJ、る半導体装置の電源電圧マージンの
「4間変化を小す図でdうる。」 以上 手続ネ山正書 昭和 年 月 日 特許庁長官 若 杉 和 夫 殿 1、事件の表示 特願昭58−147085号2、発明
の名称 半導体装置 3、補正をする者 jlイ′1どの関係 特許出願人 住 所 東京都千代田区内幸町1丁目1番6号名 称 
(422)日本電信電話公社 代表者 真 藤 恒 4、代理人 住 所 〒102 東京都千代11区麹+11J 5丁
目7番地 秀和紀尾井町T B R820号5、?1l
iilE命令の目付 自発補正6.7+li正により増
加する発明の数 なし7、補止の対象 明細店及び図面
の全文8、補止の内容 別紙の通り 明 細 E、+ <全文i」止〉 1、発明の名称 半導体装{1′′ず 2、特許請求の範囲 半導体素子を形成している半導体J、L仮十に絶縁層が
形成され、 該絶縁層上に上記半導体、)、子に連れ−され1]っバ
ット部を右する配線用導体層が形成され、該配線用導体
層のバラ1〜部に金よIこけ金を主成分とする41石で
なる導線か連rl’iされている(14成を有り−る半
導イホ装1ηに(〕3いで、上記配線用導体層が、上記
絶’I)′、Inに対して強接着1(Lを有づ゛るポリ
シリ」ン11η、Llこ1.L金属屑でなる第1の導体
層と、該第1の)9]ホ層上に形成されIこアルミニウ
ムまIこはアルミ−ラムを主成分とする材料でなる第2
の29体層とからなり、上記導線が、上記第2の導体層
の上記バラ1一部に連結されていることを特徴とづる半
39休装買。 3、発明の詳細な説明 本発明は、半導体索子を形成しているEl’ 尋(ホ是
板上に絶縁層が形成され、その絶縁層上に半導体素子に
連結され且つバット部を有ずる配線用導体層が形成され
、その配線用導体層のバット部に金または金を主成分と
する材料でなる導線が連結されている4M成を右ずる半
導体装置の改良に関する。 従来のこのような半導体装置は、第1図に示t J:う
に、半導体素子(図示せず)を形成している半>9体阜
仮1土に、例えばS!0+でなる絶縁層2が形成され、
その絶縁層2上に、半導体索子(図示μず)に連結され
且つパラ1一部3を右りる配線用導体層4が形成され、
その配線用導体層4のバラ1〜部3に、金または金を主
成分とJる材料でなる導線5が、ボンデングによって連
結されている構成を有している。なお、6は、絶縁性保
護膜である。 この場合、配線用導体層4が、アルミニウムでなる層の
単層でなる。 以上が、従来の半導体装置の構成である。 このような{j4成を有づる半導体装置の場合、導線5
が、金または金を」成分どりる)A A.J+で114
成されているので、導線どし(の19れた4’.i j
’Jを右タ゛る。 また、配線用導体層4が、アルミニウム(゛なるため、
そのバフ1〜部3に,13いC、金または金を主成分と
する月利でなるy9m 5どの間ぐ良りfな連結関係が
得られる、という特徴を有づる。 しかしながら、弟1図に示り゛1′−導体装貿の場合、
導線5を配線用導体層4のバラ1・部3にボンデングに
よって連結して後、熱か!jえられlJ場合、配線用導
体層4のバラ1・部3に、心線5の金と、配線用導体R
?i /lのアルミニウムとが反応して、All AI
 r 、Au + 八l 13トU)合金カ形成され、
このIこめ、配線用導体層4内に、13号7で示すよう
に、空孔が生じ、よって、1′導体素子から配線用導体
層4を介しC導線5に到る配線の電気的11(抗が人さ
く増入りる、という欠点を右していた。 また、第1図に示づ従来の半導体装置の場合、配線用導
体層4がアルミニラl\(41るため、配線用導体層4
ど絶縁層2との間の接着力が弱く、このため、配線用)
9体層4が、絶縁層2から剥餌し易い。′このため、配
線用導体層4に、上述したJ:うに空孔7が形成されれ
ば、導線5が配線用導体層4の一部とともに、脱落づる
おそれを有する、という欠点を有していた。 さらに、第1図に示J゛従来の半導体装置の場合、」ニ
)ホした欠点を有しているので、長期に亘り、所期の特
性で、安定に動作しないという、欠f気を右していた。 よって、本発明は、上述した欠点のない、新規な半導体
装置を提案けんとするもので、以下Jべろどころから明
らかとなるであろう。 第2図は本発明による半導体装置の一例を示0 第2図にJ3いて、第1図との対応部分には同一符号を
f(Jシて詳細説明を省略する。 第2図に示づ本発明による半導体装置は、次の事sr4
を除いて、第1図の場合と同様の構成をイ1!Jる。 すなわち、配線用導体Fi4が、jアルミニウムでなる
層の単層であるのに代え、絶縁層2に対して強接着性を
イ1するポリシリ」ン層、j、たはタンタル、クロム、
[リブデン、タングステンなどの絶縁層2に対して強接
着性をイjし月つ耐熱性を右する金属層でなる導体層′
11と、その導体層11上に形成されたアルミニウムま
たはアルミニウムを主成分どりる祠II ’rなる導体
層12とからなる。 しかして、金または金を主成分どりる祠18ICなる導
線5が、アルミニウムよlどはアルミニウムを主成分ど
する材料でなる后1ホh?i12上のバット部3に連結
されている。 以上が、本発明ににる半1fl(本装置の一例構成であ
る。 このにうな構成によれば、導線5が、第1図に示す従来
の半導体装置の場合と同様に、金または金を主成分どり
る拐お1で4.M成されているので、第1図に示す従来
の半導体}装置の場合と同様に、導線としての1受れた
141!lをイjりる。 また、導線5が配線用導体層4のバット部3にJ3いC
直接連結される配線用導体層4の導体層12が、アルミ
ニウムまたはアルミニウムを主成分としている材料でな
るため、配線用導体層4のパラ1〜部3にJ3いて、配
線用心体層4ど金または金を主成分とする材料でなる導
線5との間C1第1図に承り従来の半導体′14置の場
合と同様に、良好な連結関係が得られる、という14徴
をイ]!Jる。 しかしながら、第2図に承り本発明ににる半導体装置の
場合、配線用心体層層4が、絶縁層2に対しく強接着性
を右りるポリシリコン層また(よタンタル、クロム、モ
リブデン、タングステンなどの金属層でなる導体層11
ど、アルミニウムまたはアルミニウムを主成分どする材
料でなる導体層12とからなり、イして金または金を主
成分とする材料でなる導線5が、アルミニウムまたはア
ルミニウムを主成分とする材料でなる導体層12に連結
されているので、たとえ、導Fd5を導体層12に連結
して後、熱が与えられることによって、導体層12に第
1図に場合のように空孔が形成されても、ζ(体層11
をイjしているので、配線用導体層4が導線5に連結さ
れている状態を保っていることに変りはなく、よって、
坐り9体素子から配線J1100層4を介して導FA5
に到る配線の電気的抵抗が、第1図に承り従来の半導体
装V1の場合のJ、うに増入りる、ということがない、
という特徴をイ1りる。 また、配線用心体層4の心体層11が、絶縁層2に接し
、そしてCの導体層11が絶縁K・12に対して強接着
性をイjilるポリシリコン層まIこはタンタル、り1
:1ム、モリブデン、タングステンなどの金属層でなる
ので、ンクイホ層11ど絶縁層2との間の接着力が、第
1図に承り従来の半う9体装ηの配線用導体E・i /
Iと絶縁層2の間の接着〕〕に比し強く、このため、導
体層11が絶縁層2から剥II!II L難い。勿論、
ンク体層11ど心体層12との間は、導体層11ど絶縁
層2どの間に比し強い接おりを有し、このlJめ、導体
II′1712が導体層11から剥# L !!l[い
。 従って、配線用導体層4の導体層12に上述したように
3?孔が形成されても、導線5が、第1図に示す従来の
半導体装置の場合のように、配線用導体層4の一部どど
もに、[12落するおそれがあるということがない、と
いう特徴を右する。 さらに、本発明による半導体装置によれば、上1本しI
ご特徴を右するので、第1図に示す従来の半導体装置に
比し、長期に回り、所期の特性で、安定に動作する、と
いう特徴を有する。 囚みに、第1図に示づ従来の半導体装置(絶縁層2/、
ASiO+でなる)の5個ど、第2図に示す4(発明に
にる半導体装置(絶縁層2が5iO7でなり、配線用導
体層4の導体層11がポリシリコン層、導体層12がア
ルミニウムでなる)の8個どを、260℃の温度で、3
80011、−開動作さUたどころ、従来の半導体装置
の場合、その5個中の2個に故障を生じたが、本発明に
よる半導体装置の場合、その8個の全−Cに故障を生じ
なかった。 また、第1図に示づ従来の一′1′導体装置(絶縁層2
が8102でなる)の5個と、第2図に示す本発明に示
す半導体装置(絶縁rう2がSiO2でなり、配線用導
体層40脣休層11がポリシリコン層、導体層12がア
ルミニウムでなる)の5個とを、290℃の温度C・、
’I El OOIl、’+ Itil動作させたとこ
ろ、従来の半導体装置の場合、ぞの5個中の111!J
に1攻障を1−じl”: i)j、、本発明による半導
体装置の場合、その5個の仝でに故障を生じなかった。 さらに、第1図に小り従来の半導体装置(絶縁層2がS
fO+でなる)と、第2図に示り本発明による半導体装
置く絶縁tA2がS i Or ′cなり、配線用導体
層4の導体層11がポリシリコン層、導体Fi12がア
ルミ−ラムCなる)どについて、半導体素子から配線用
導体層4を介し−C導線5に到る配線の電気的11(抗
の111間変化を、電気的抵抗の増減に応じて増減づる
〉16導体装置に封する電源電圧のマージンの時間変化
で、測定したところ、従来の半導体装置の場合、第4図
中点線図示するように、500詩間を経過しIc++y
 )HHから急激に゛電源電圧マージンが上昇り”るの
に対し、本発明による半導体装置の場合、第4図中実線
図示のように、500詩間を経過しても電源電圧マージ
ンが殆んど上背しない、という結果が得られた。 以上のことから、本発明による半導体装置によれば、第
1図に示り゛従来の半導体装置に比し長期に亘り、所期
の特性で、安定に動作するという特徴を有することが明
らかであろう。 なJ3、上述においては、配線用導体層4の導体層11
が単層である場合につき述べたが、第3図に示すように
、絶縁層2側の導体層13と、その上に形成されICM
J体層1402層とJ−ることもU′きる。この場合、
導体層13は、絶縁層2に対し°τ強接着性を有するl
−i層としMl 、またY!体層14は、導体層12か
らのアルミニウムよlこはアルミニウムを主成分とする
材料が導体層13側に拡散するのを阻止する性質を有す
る11 を層とし胃る。 その他、本発明の精神を11+2 することなしに、種
々の変型、変更をなし1するであろう。 4、図面の簡単な説明 第1図は、従来の半導体装置を示1’ 118 Fll
的断面図である。 第2図及び第3図は、本発明による半導体装置の実施例
を示す路線的断面図である。 第4図は、第1図に示り一従来の゛1′−導体肢置及び
第2図に示り一木発明による半導体装置の雷j’!a電
圧マージンの時間変化を示づ図r″ある。 1・・・・・・・・・・・・・・・・・・半導体基板2
・・・・・・・・・・・・・・・・・・絶縁層3・・・
・・・・・・・・・・・・・・・バラ1へ部4・・・・
・・・・・・・・・・・・・・配線用n体層5・・・・
・・・・・・・・・・・・・・導線6・・・・・・・・
・・・・・・・・・・絶縁性1+A:護膜+1.12.
13.14
Fig. 7A1 is a view of the conventional Hanfutai/boring: ζ°'i on the small 111 line n'i 1lJi. FIGS. 2 and 3 are sectional views showing a half-section device according to the present invention. Applicant: Kazuo Wakasugi, Commissioner of the Japan Patent Office, 1. Indication of the case: Japanese Patent Application No. 147085/1985 2, Name of the invention: Semiconductor device 3 , What is the relationship between the person making the amendment and the case? Patent Applicant: Yuu 1-1-6 Uchisaiwai-cho, Chiyo IJ'1-ku, Tokyo Name (422) Nippon Telegraph and Telephone Public Corporation Representative Tsune Shinto 4 Address of agent: 102 Tokyo 5-7 Kojimachi, Chiyoda-ku, Miyako
Hidekazu Kioicho TBR No. 820 5, Date of amendment order November 29, 1980 6, Number of inventions increased by J: None 7, Subject of amendment Mei I
Column B of the brief description of the drawings in Book II, contents of amendment (1) Box 5, line 1, line 1, page 5 of the specification...This is a line RG 1 view. ”, then add the following. ``Figure 4 is a diagram that minimizes changes in the power supply voltage margin of the semiconductor device shown in Figure 1 and the semiconductor device of the present invention shown in Figure 2.'' The above procedure Masashi Neyama, Showa year, month, day, Japan Patent Office Commissioner Kazuo Wakasugi 1. Indication of the case: Japanese Patent Application No. 58-147085 2. Title of the invention: Semiconductor device 3. Person making the amendment: Relationship: Patent applicant Address: 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Name:
(422) Nippon Telegraph and Telephone Public Corporation Representative Tsune Shinfuji 4, Agent address 5-7 Koji+11J, Chiyo 11-ku, Tokyo 102 Hidekazu Kioicho TBR 820-5, ? 1l
Weight of iiiE command Voluntary amendment 6.7 + Number of inventions increased by li correction None 7, Target of amendment Full text of specification and drawings 8, Contents of amendment As shown in the attached sheet Details E, + <Full text i''stop> 1 , Title of the invention Semiconductor device {1''Z2, Claims Scope of Claims An insulating layer is formed on the semiconductors J and L forming the semiconductor element, and on the insulating layer the above-mentioned semiconductor), A conductor layer for wiring is formed on the right side of the butt part, and a conductive wire made of 41 stones whose main components are gold and moss gold is connected to the parts 1 to 1 of the conductor layer for wiring. (3) The wiring conductor layer is made of a polysilicon film having a strong adhesion to the above-mentioned In and In. A first conductor layer made of metal scrap, and an aluminum layer formed on the first layer are made of a material containing aluminum as a main component. Second
29 conductor layers, and the conductor wire is connected to a portion of the rosette 1 of the second conductor layer. 3. Detailed Description of the Invention The present invention provides an insulating layer formed on an element plate forming a semiconductor cable, which is connected to a semiconductor element on the insulating layer, and has a butt part. The present invention relates to an improvement of a semiconductor device having a 4M structure in which a wiring conductor layer is formed and a conductive wire made of gold or a material containing gold as a main component is connected to a butt portion of the wiring conductor layer. The semiconductor device is shown in FIG. 1, in which an insulating layer 2 made of, for example, S!0+ is formed on a semiconducting layer forming a semiconductor element (not shown).
On the insulating layer 2, a wiring conductor layer 4 is formed which is connected to a semiconductor cable (not shown) and which extends over a portion 3 of the parallax 1,
A conductive wire 5 made of gold or a material containing gold as a main component is connected to the parts 1 to 3 of the wiring conductor layer 4 by bonding. Note that 6 is an insulating protective film. In this case, the wiring conductor layer 4 is made of a single layer of aluminum. The above is the configuration of the conventional semiconductor device. In the case of a semiconductor device having such a {j4 configuration, the conducting wire 5
A. 114 with J+
4'.i j
'Turn right on J. In addition, since the wiring conductor layer 4 is made of aluminum (
The buffs 1 to 3 have the characteristic that a good connection relationship can be obtained between 13C and y9m5, which is made of gold or a monthly interest mainly composed of gold. However, in the case of ``1''-conductor equipment shown in Figure 1,
After connecting the conductive wire 5 to the parts 1 and 3 of the wiring conductor layer 4 by bonding, it gets hot! In the case that the wiring conductor layer 4 has the gold of the core wire 5 and the wiring conductor R
? i/l of aluminum reacts to form All AI
r, Au + 8l 13tU) alloy is formed,
As a result, holes are formed in the wiring conductor layer 4 as shown by No. 13 7, and therefore the electrical 11 of the wiring from the 1' conductor element to the C conductor 5 via the wiring conductor layer 4 is generated. In addition, in the case of the conventional semiconductor device shown in FIG. 1, since the wiring conductor layer 4 is made of aluminum 4
(For wiring)
The nine-body layer 4 is easily peeled off from the insulating layer 2. 'For this reason, if the above-mentioned holes 7 are formed in the wiring conductor layer 4, there is a drawback that the conductor 5 may fall off together with a part of the wiring conductor layer 4. Ta. Furthermore, in the case of the conventional semiconductor device shown in Fig. 1, it has the following drawbacks: Was. Accordingly, the present invention aims to propose a novel semiconductor device free from the above-mentioned drawbacks, which will become clear from the following section. FIG. 2 shows an example of a semiconductor device according to the present invention. In FIG. 2, parts J3 and corresponding parts to those in FIG. The semiconductor device according to the present invention has the following characteristics sr4.
I1! has the same configuration as in Figure 1, except for . Jru. That is, instead of the wiring conductor Fi4 being a single layer of aluminum, it is made of a polysilicon layer that has strong adhesion to the insulating layer 2, or tantalum, chromium,
[A conductor layer made of a metal layer such as livedenum or tungsten that has strong adhesion to the insulating layer 2 and has good heat resistance.'
11, and a conductor layer 12 formed on the conductor layer 11 and made of aluminum or aluminum as a main component. However, if the conductor wire 5, which is gold or an IC whose main component is gold, is made of a material whose main component is aluminum, such as aluminum? It is connected to the butt part 3 on i12. The above is one example of the structure of the present device according to the present invention. According to this structure, the conductive wire 5 is made of gold or gold, as in the case of the conventional semiconductor device shown in FIG. Since the main component is 4.M, the conductor wire 141!l is removed as in the case of the conventional semiconductor device shown in FIG. , the conductor 5 is attached to the butt part 3 of the wiring conductor layer 4
Since the conductor layer 12 of the wiring conductor layer 4 to be directly connected is made of aluminum or a material containing aluminum as a main component, the conductor layer 12 of the wiring conductor layer 4 is made of aluminum or a material containing aluminum as a main component. Or, between C1 and the conducting wire 5 made of a material whose main component is gold, as shown in FIG. Jru. However, in the case of the semiconductor device according to the present invention as shown in FIG. Conductor layer 11 made of metal layer such as tungsten
The conductor layer 12 is made of aluminum or a material containing aluminum as a main component, and the conducting wire 5 is made of aluminum or a material containing aluminum as a main component. Since it is connected to the conductor layer 12, even if holes are formed in the conductor layer 12 by applying heat after connecting the conductor Fd5 to the conductor layer 12, as in the case of FIG. ζ (body layer 11
Since the wiring conductor layer 4 remains connected to the conductive wire 5, there is no change.
Conductive FA5 from the sitting 9-body element via wiring J1100 layer 4
As shown in FIG. 1, the electrical resistance of the wiring that leads to J does not increase as much as in the case of the conventional semiconductor device V1.
I have the following characteristics. Further, the core layer 11 of the wiring core layer 4 is in contact with the insulating layer 2, and the conductor layer 11 of C is a polysilicon layer that has strong adhesion to the insulation layer 12, or is made of tantalum, Ri1
1, molybdenum, tungsten, and other metal layers, the adhesion between the conductor layer 11 and the insulating layer 2 is as shown in FIG. /
Therefore, the conductor layer 11 peels off from the insulating layer 2. II L is difficult. Of course,
There is a stronger contact between the conductor layer 11 and the central body layer 12 than between the conductor layer 11 and the insulating layer 2, and at this point, the conductor II'1712 is peeled off from the conductor layer 11. ! l[I. Therefore, as described above, the conductor layer 12 of the wiring conductor layer 4 has 3? Even if the hole is formed, there is no risk that the conductive wire 5 may fall onto some parts of the wiring conductor layer 4, as in the case of the conventional semiconductor device shown in FIG. This characteristic is true. Furthermore, according to the semiconductor device according to the present invention, the upper
Compared to the conventional semiconductor device shown in FIG. 1, the semiconductor device has the characteristics of being able to operate stably over a long period of time with desired characteristics. In contrast, the conventional semiconductor device shown in FIG. 1 (insulating layer 2/,
A semiconductor device according to the invention (the insulating layer 2 is made of 5iO7, the conductor layer 11 of the wiring conductor layer 4 is a polysilicon layer, and the conductor layer 12 is an aluminum layer) as shown in FIG. 3) at a temperature of 260℃.
80011, -In the case of the conventional semiconductor device, a failure occurred in two of the five semiconductor devices, but in the case of the semiconductor device according to the present invention, a failure occurred in all eight of the semiconductor devices. There wasn't. In addition, the conventional one'1' conductor device (insulating layer 2
8102) and a semiconductor device according to the present invention shown in FIG. ) and 5 pieces at a temperature of 290℃ C・,
When I operated 'I El OOIl, '+ Itil, in the case of a conventional semiconductor device, 111 out of 5! J
In the case of the semiconductor device according to the present invention, no failure occurred among the five components.Furthermore, FIG. Insulating layer 2 is S
fO+), the insulation tA2 of the semiconductor device according to the present invention as shown in FIG. ), the electrical resistance of the wiring from the semiconductor element to the -C conductor 5 via the wiring conductor layer 4 is sealed in a 16-conductor device. When measuring the time change in the margin of the power supply voltage, in the case of a conventional semiconductor device, as shown by the dotted line in FIG.
) In the semiconductor device according to the present invention, as shown by the solid line in FIG. As shown in FIG. It is clear that it has the feature of stable operation.
As shown in FIG. 3, the conductor layer 13 on the insulating layer 2 side and the ICM formed thereon are
The J body layer 1402 and the J-layer can also be separated by U'. in this case,
The conductor layer 13 has l having strong adhesion to the insulating layer 2.
−i layer, Ml, and Y! The body layer 14 is made of aluminum having a property of preventing a material mainly composed of aluminum from the conductor layer 12 from diffusing toward the conductor layer 13 side. In addition, various modifications and changes may be made without departing from the spirit of the invention. 4. Brief description of the drawings Figure 1 shows a conventional semiconductor device.
FIG. FIGS. 2 and 3 are cross-sectional views showing an embodiment of a semiconductor device according to the present invention. FIG. 4 shows a conventional conductor arrangement shown in FIG. 1 and a semiconductor device according to Ichiki's invention shown in FIG. 2. Figure r'' shows the change in voltage margin over time. 1... Semiconductor substrate 2
・・・・・・・・・・・・・・・Insulating layer 3...
・・・・・・・・・・・・・・・Rose 1 Part 4...
・・・・・・・・・・・・N-body layer 5 for wiring
・・・・・・・・・・・・・・・Conductor 6・・・・・・・・・
・・・・・・・・・Insulation 1+A: Protective film+1.12.
13.14

Claims (1)

【特許請求の範囲】 半導体素子を形成している半導体基板上に絶縁層が形成
され、該絶縁層上に上記半々1本素子に連結され、且つ
、パラI・部を右りる配線用心悸層が形成され、該配線
用導体層のバット部に金よlこは金を主成分どりる祠1
′31でなる導線が連結されCいる(1η成を右する半
導体装置において、配線用心悸層が、ポリシリコン層で
なる、または上記絶縁層に対して強接着性を有する金属
層′c1.<る第1の心体層と、該第1の心体層上に形
成されたアルミニウムまたはアルミニウムを主成分ど゛
りる月利でなる第2の導体層とからなり、 上記導線が、上記第2のη体層上記バット部にの連結さ
れていることを特徴どする半導体装置。
[Scope of Claims] An insulating layer is formed on a semiconductor substrate forming a semiconductor element, and on the insulating layer there is provided a wiring wire connected to the above-mentioned half-and-half element, and extending to the right side of the para-I section. A layer is formed, and a shrine 1 containing gold as a main component is formed on the butt part of the wiring conductor layer.
In a semiconductor device having a 1η structure, the wiring layer is made of a polysilicon layer, or a metal layer having strong adhesion to the insulating layer. a first core layer formed on the first core layer, and a second conductor layer formed on the first core layer and made of aluminum or mainly composed of aluminum; A semiconductor device characterized in that a second η body layer is connected to the butt portion.
JP58147085A 1983-08-11 1983-08-11 Semiconductor device Pending JPS6038850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58147085A JPS6038850A (en) 1983-08-11 1983-08-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58147085A JPS6038850A (en) 1983-08-11 1983-08-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6038850A true JPS6038850A (en) 1985-02-28

Family

ID=15422125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58147085A Pending JPS6038850A (en) 1983-08-11 1983-08-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6038850A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52143785A (en) * 1976-05-26 1977-11-30 Hitachi Ltd Semiconductor device
JPS533084A (en) * 1976-06-29 1978-01-12 Nec Corp Semiconductor device
JPS53101267A (en) * 1977-02-16 1978-09-04 Hitachi Ltd Semiconductor device
JPS5425679A (en) * 1977-07-28 1979-02-26 Nec Corp Manufacture for semiconductor device
JPS5756211A (en) * 1981-05-06 1982-04-03 Naito Seisakusho:Kk Feeding device of molding material to die in compression molding machine

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52143785A (en) * 1976-05-26 1977-11-30 Hitachi Ltd Semiconductor device
JPS533084A (en) * 1976-06-29 1978-01-12 Nec Corp Semiconductor device
JPS53101267A (en) * 1977-02-16 1978-09-04 Hitachi Ltd Semiconductor device
JPS5425679A (en) * 1977-07-28 1979-02-26 Nec Corp Manufacture for semiconductor device
JPS5756211A (en) * 1981-05-06 1982-04-03 Naito Seisakusho:Kk Feeding device of molding material to die in compression molding machine

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