JPS6039092U - pattern generation circuit - Google Patents
pattern generation circuitInfo
- Publication number
- JPS6039092U JPS6039092U JP13157283U JP13157283U JPS6039092U JP S6039092 U JPS6039092 U JP S6039092U JP 13157283 U JP13157283 U JP 13157283U JP 13157283 U JP13157283 U JP 13157283U JP S6039092 U JPS6039092 U JP S6039092U
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- generation circuit
- pattern generation
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Image Generation (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はＣＲＴの画面上にへ四角の形のエリアでパター
ンの書換を行なおうとする場合にそのパターンの種類を
例示した図、第２図は本考案を利用したディスプレイ装
置の構成例を示す図、第３図はビデオＲＡＭとＣＲＴの
画面との相対関係を示した図である。Figure 1 is a diagram illustrating the types of patterns to be rewritten in a rectangular area on a CRT screen, and Figure 2 is an example of the configuration of a display device using the present invention. The figure shown in FIG. 3 is a diagram showing the relative relationship between the video RAM and the CRT screen.
Claims (1)
トの信号を記憶できるパターンレジスタ４と、スタート
アドレスとストップアドレスのデータを記憶するレジス
タ５，７と、前記スタートアドレス又はストップアドレ
スのどちらかのデータを導入してこのデータについてカ
ウントアツプ又はカウントダウンするカウンタ９と、前
記スタートアドレス又はストップアドレスのデータとカ
ウンタからのデータを比較して一致した場合に終了信号
を出力するコンパレータ１１，１２とを備え、 前記パターンレジスタに所望の四角形の発生パターンの
一部分を形成する複数ビットのパターン信号を書込むよ
うにし、前記カウンタの出力をアドレス信号として前記
パターンレジスタの内容を繰り返し読出して次段（ビデ
オＲＡＭ）へ転送するようにしたパターン発生回路。[Claims for Utility Model Registration] A circuit used in a graphic device includes a pattern register 4 capable of storing a plurality of bit signals, registers 5 and 7 storing data of a start address and a stop address, and a pattern register 4 capable of storing data of a start address and a stop address. A counter 9 that inputs data from either address and counts up or down for this data; and a comparator 11 that compares data from the start address or stop address with data from the counter and outputs a termination signal when they match. . A pattern generation circuit that transfers data to a video RAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13157283U JPS6039092U (en) | 1983-08-25 | 1983-08-25 | pattern generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13157283U JPS6039092U (en) | 1983-08-25 | 1983-08-25 | pattern generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6039092U true JPS6039092U (en) | 1985-03-18 |
| JPH0112309Y2 JPH0112309Y2 (en) | 1989-04-11 |
Family
ID=30297413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13157283U Granted JPS6039092U (en) | 1983-08-25 | 1983-08-25 | pattern generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039092U (en) |
-
1983
- 1983-08-25 JP JP13157283U patent/JPS6039092U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0112309Y2 (en) | 1989-04-11 |
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