JPS6039187B2 - pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern generator used when testing the operation of a semiconductor device such as a microprocessor IC, and in particular to a pattern generator that uses a pattern memory with a slow generation speed to It is designed to generate a pattern signal faster than the speed.

Operation tests for IC-based microprocessors, etc. are summarized below.
This is done as follows.

There are two types of pattern signals generated by the pattern generator: input pattern signals and expected value pattern signals.
The input pattern signal is a pattern signal containing input information to be applied to an input pin of the IC under test, and based on this pattern signal, the pattern signal is input to the IC under test. As a result, the IC under test performs a specific operation and generates a constant output signal. The thus output signal is compared with the expected value pattern signal to test whether or not the operation of the IC under test is normal. The pattern signal is output from the pattern memory.

Therefore, for example, if a pattern signal with a repetition frequency of F (day 2) is required, a pattern signal with a cycle time shorter than the memory element Akiyoshi (Sec) used for the pattern memory must be used. This is because the pattern addresses are not only output sequentially but also randomly specified. Therefore, in conventional pattern generators, in order to increase the F (Hz) mentioned above and generate high-speed patterns, a high-speed memory element is required, which is not only expensive but also requires a pattern whose speed exceeds the cycle time of the memory element. It cannot be caused to occur. For this reason, methods have been considered in which high-speed patterns are generated using slow-response memory elements. This method is called the memory interleaving method, and as shown in Figure 1, multiple memory elements such as la, lb, lc, and ld are prepared, and these memory elements l
Address controls a to ln. A pattern address is supplied from the controller 2, pattern signals which sequentially change are obtained from each memory element la to ld, and each pattern signal is sequentially taken out by a multiplexer 3. That is, as shown in FIG. 2, the pattern address M-1,
M, M+1, M12, M13, M+4, . . . are output. Pattern signals corresponding to pattern addresses M, M14, M+8, M+12, . . . are output from memory element la, and pattern signals corresponding to pattern addresses M are output from memory element lb.
Pattern signals corresponding to 11, M15, M19, M113, ... are output, and patterns corresponding to pattern addresses M12, M+6, M110, M+14, ... are output from the memory element lc. A signal is output, and pattern addresses M-1, M13, M+7, M+11,
A pattern signal corresponding to... is output. These pattern outputs are selected by the multiplexer 3 based on, for example, the lower two pitches of the pattern address, and are output as data corresponding to the pattern address. According to the pattern generator configured in this way, each memory element la
~ld means that when the pattern address changes at a repetition frequency of F (Hz), the next address is specified at F/4 (Hz). Therefore, the cycle time of the memory element required to generate a pattern of F(HZ) is 4/F.
(sec) or less, and therefore, a high-speed pattern can be generated by a low-speed response type memory element. However, this memory interleaving method has the following drawbacks. That is, in the above example, the pattern addresses are M, M11, M12.
, M+3, . . . , a case where the change occurs sequentially has been described, but a dummy cycle occurs when the change does not occur sequentially. There is no problem if the pattern signal you want to output can be obtained by sequentially accessing the memory elements la to ld, but if the same memory element is
A problem arises when accesses must be made at intervals shorter than the cycle time of /F (seconds). For example, in FIG. 3, when it is desired to output Dx after the pattern output data DM12, since both DM12 and Dx are stored in the memory element lc, in order to prevent a dummy cycle from occurring, the memory element lc must be set at the cycle time. It is necessary to access continuously in F (seconds). However, in the case of the interleave method, one memory element is sequentially accessed in four cycles, so when this operation occurs, the memory element requires a maximum of four cycles to access one address, so the PA
As shown in FIG. 3, at least three dummy cycles occur after the pattern specified by =M12 is output until the next pattern is output. If an IC memory is tested using a pattern signal having a dummy cycle, the dummy cycle becomes wasted time, resulting in an inconvenience that the test time becomes longer. An object of the present invention is to provide a pattern generation device that uses a slow response memory element and does not generate dummy cycles.

In this invention, two sets of memo IJ blocks are prepared to explore the memory interleaving method explained in FIG. This is to prevent this from occurring.

An embodiment of the present invention will be described in detail below using FIG. 4.

In FIG. 4, 1 and 1' are memo 1'' blocks each having a plurality of memory elements as described in FIG. 1 and capable of generating a high-speed pattern by memory interleaving during sequential addressing.

Patterns to be generated are stored in exactly the same form in these memory blocks 1 and 1'. That is, the same pattern is stored at the same address. Reference numeral 2 denotes an address controller, from which pattern addresses A and B are output, pattern address A is supplied to memory block 1, and pattern address B is supplied to memory block 1'.

Pattern addresses A and B of the address controller 2 are controlled by a sequence control memory 4.
This sequence control memory 4 is a memory that stores discontinuous address designation positions, for example, memory AD.
M+2 is stored in R, and X is stored in ADR2. It is now assumed that a sequential pattern A is being generated by the pattern generation memory block 1.

As long as patterns are generated with sequential addresses, no dummy cycles occur. At this time, the sequence control memory 4 indicates discontinuous (non-sequential) addresses. Therefore, from the address control 2, the address to be updated by the pattern address B, in this case X, can be specified in advance. Therefore, the pattern generation memory block 1' outputs data corresponding to the address X to be updated and waits. On the other hand, the pattern address A is constantly compared with the contents of the memory ADR of the sequence control memory 2.

When the contents of pattern address A and memory ADR match, it is detected that the address to be specified next is discontinuous, and at this time pattern address B has already been specified.
The pattern corresponding to the jump destination address X prepared by is sent out through the multiplexer 3, and no dummy cycle is generated. Thereafter, pattern generation is performed sequentially using the pattern generation memory block 1'. Memory ADR of sequence control memory 4
, and the next control word is revealed to ADR2,
Control next jump. In the next control, pattern addresses A and B and pattern generation memory blocks 1, 1
', patterns A and B are opposite to the above example. As described above, according to the present invention, there are two sets of memory blocks 1 and 1' that adopt the memory interleaving method and the address controller 2.
By specially providing the sequence controller 4 and the sequence controller 4, a high-speed pattern generation device can be constructed, and a high-speed pattern generation device that does not generate dummy cycles during jump operations can be obtained.

Therefore, there is an advantage that the test time for IC elements can be shortened due to high-speed pattern generation and no dummy cycles.

[Brief explanation of the drawing]

FIG. 1 is a system diagram for explaining a conventional pattern generator, FIGS. 2 and 3 are time charts for explaining its operation, and FIG. 4 is a system diagram showing an embodiment of the present invention. . 1, 1'...Memory block, 2...Address controller, 3...Multiplexer, 4...Sequence control. Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] 1 A. In a pattern generation device in which a pattern signal is stored in a memory and an address is given to the memory to obtain a desired pattern signal. a memory block; C; an address controller that reads information at the jump destination by giving a jump destination address to the other memory block while giving a sequential address to one of the two memory blocks; and D; a sequence control memory that detects that the address given to the memory block is the address immediately before the jump;
1. A pattern generation device comprising: a multiplexer for transmitting a pattern signal read from the other memory block from the cycle after detecting an address immediately before a jump.