JPS604272A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To attain the simplification of the process and the reduction of the cost by enabling the formation of an electroless plated electrode by the adoption of an edge cleaning process of dry etching system. CONSTITUTION:After the thickness of a P type Si sungle crystal substrate 41 is reduced by etching, an N<+> layer 42 is formed by phosphorus diffusion by means of the mixed carrier gas of nitrogen and oxygen in a diffusion furnace with POCl3 as a source. Next, an Al base 44 is formed over the back surface by a screen printing method and thereafter calcined, when Al atoms are diffused into the Si, resulting in a P<+> layer 45 of an alloy metal. Then, the substrate 41 having an inclined surface 47 is formed by plasma etching, and successively a plating resist 48 is formed by screen printing. Afterwards, Ni layer 49 are formed on both surfaces back and front by Ni electroless plating, electrode bases thus being formed. Lead wires 51 is connected to solder layers 50 formed thereon, leading to the completion of the solar battery.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a solar cell, and relates to a method for manufacturing a solar cell that satisfies low cost while maintaining high characteristics.

[Technical background of the invention and its problems] Conventionally, a solar cell as shown in FIG. 1, which is made of silicon single crystal or the like as a material for photoelectric conversion of sunlight, has been widely put into practical use.

That is, for example, an n+ diffusion layer (by thermal diffusion or the like) is formed at a depth of 0.2 to 0.6 μm from the − surface of the p-type silicon single crystal substrate (1) with a thickness of 0.3 to 0.4 μm. 2) is provided to form a pn junction shown by a broken line, and 5 two lattice electrodes (81, C on the back surface of the p-type silicon single crystal substrate (1) Second, a back electrode (4) is formed over the entire surface.Also, a diffusion layer (4) is formed from the air.
2) When light is incident on a surface, a portion of the light is reflected by the surface, but in order to improve the loss due to this reflection, the surface
Second, an antireflection film (5) is formed. This is the same even when a p+ diffusion layer is formed on an n-type silicon single crystal substrate.

Various methods for manufacturing such solar cells are known, but the method for manufacturing solar cells includes a pn junction formation step, a t
The process can be divided into three main steps: the JL&formation process and the antireflection film formation process.

Among these, the pn junction forming step 12 conventionally involves keeping the substrate at a high temperature in an atmosphere containing impurities of a conductivity type different from that of the substrate.
A method using a diffusion furnace that diffuses the C2 impurity in the substrate due to the difference in impurity concentration is a common method, and is widely adopted from the viewpoint of uniformity and mass production. In addition, ion implantation and epitaxial growth methods are also used in the semiconductor industry to form pn junctions, but they are not widely used for solar cells because of their low productivity.

In addition, vapor deposition methods, spin coating methods, etc. have generally been attempted in the antireflection film forming process, but in practice, as a method that does not require the provision of a special coating layer, the selection of the surface of the diffusion layer based on the alkaline condition V* is recommended. A method of forming an anisotropically etched surface using etching properties has been adopted.

As mentioned above, in the 52 pn junction formation process and the anti-reflection film formation process, if the current single crystal silicon substrate is used and the cost is lowered, impurity thermal diffusion and anisotropic etching surface, respectively, are currently the most effective. preferable.

Recently, attempts have been made to use inexpensive polycrystalline silicon or ribbon crystalline silicon for some silicon substrates, and some of them have been crystallized. Since crystal grains with various orientations are present in the substrate in these two cases, even if anisotropic etching is performed, a good antireflection effect cannot be obtained.

In other words, planes with an orientation close to the (100) plane are etched relatively anisotropically, but planes with other orientations are etched homogeneously, or because the rates are different, a grain boundary step simply occurs. It must be anti-reflection f2. Therefore, it is necessary to form an anti-reflection film on an inexpensive substrate (pair) having such grain boundaries. At present, the method of forming the preventive film and forming the bond at the same time is considered to be the shortest process.

Next is the electrode formation process C, in which the current collecting electrode is formed.Secondly, the method of forming a metal thin film using vapor deposition or sputtering is the most reliable method, but has extremely low throughput, so mass production is aimed at low cost. They are shunned from the process.

Electrode forming processes that have been put to practical use in this mass production process include one based on a printing method and one based on a plating method.

Among these, those using the printing method usually use a paste containing a large amount of expensive silver as a raw material, and if the overall cost of C2 decreases in the near future, it will be difficult to use it. Among the pastes that are based on base metals instead of silver, there is currently an aluminum paste for making p-type high-grade 1 (B8F) solar cells, but this aluminum paste is used for electrodes. My son is L.

Further, electrodes produced by the printing method require a high-temperature firing step as a post-treatment, and the oxidized layer on the surface must be removed by etching afterwards, otherwise the solder will not stick well and cannot be put to practical use. Also, hydrofluoric acid is usually used to remove this etching, but
In this case, if the printed electrode gold is present, a staining phenomenon may occur on the substrate, resulting in stain-like stains.

In addition, when silver is exposed to surface C2, oxidation progresses during long-term use, and it also changes color, reducing the commercial value, and increasing the series resistance of solar cells, deteriorating their characteristics. It often caused. Furthermore, printed electrical contacts have poor adhesion to the substrate, which can lead to electrode peeling accidents, which poses problems in terms of reliability.

On the other hand, plated electrodes can be efficiently formed using relatively inexpensive materials such as nickel and copper, and if a solder layer is formed on top of this, long-term reliability can be guaranteed. Its use has become commonplace.

However, because electroless plating, which is commonly used, tends to adhere to the substrate, the process becomes complicated due to the need to form a plating mask on the substrate and the bonding separation method to remove the plating on the end surface. be.

Among these, for plating masks, it has traditionally been done to form a photoresist pattern, and after forming the resist on the entire surface, a pattern [etching] is performed by light exposure C2 to fill in the grooves. It had been plated.

Furthermore, in the bonding/separation method C, since plating conventionally adheres to the entire end surface, the edge portion of the end surface C2 and the main surface C2' is finally ground off with a grinder. However, in this case, if the board is scraped at high speed, it is easy for the board C to crack, so the maximum is 50 pieces/hour, and for square boards, the special 5 grinder must be operated at low speed at the corners, so 20 pieces/hour can be automated. Therefore, even if a low-cost production process using plating is selected, the bonding and separation process takes too much time, and this process must be performed outside the assembly line.

On the other hand, currently in the semiconductor industry, dry etching technology based on plasma is becoming popular. Of course, this dry etching is also possible for silicon, and if this technique is used for junction separation of solar cells and the method for forming the plating resist is improved (2. [Objective of the Invention] The present invention has been made in view of the above-mentioned problems and requests, and is intended to improve the manufacturing process of solar cells using plated electrodes. In order to adopt a high index dry etching type etch cleaning process, the etched surfaces of the silicon substrate and impurity diffusion layer are covered with plating resist immediately after etch cleaning, and then electroless plating electrodes are formed. It is an object of the present invention to provide a method for manufacturing a solar cell that can obtain a highly reliable solar cell that achieves simplification and cost reduction.

Summary of the Invention] The method for manufacturing a thick 1U battery of the present invention includes a step of expanding the dopant from one surface of a silicon substrate to form an impurity diffusion layer of another conductivity type, and a step of forming an impurity diffusion layer of another conductivity type. The slope where the joint part is formed is located near the outer periphery of the silicon substrate t.
The process includes a process of separating the junction by etching, a process of forming a C2 plating resist on the impurity diffusion layer so that this junction is also sharp, and a process of forming an electrode by electroless plating. It is characterized by containing. According to the manufacturing method of the present invention, dry etching, which is highly mass-producible, can be incorporated into an integrated manufacturing process including the plating electrode process, thereby making it possible to shorten the length of the solar cell manufacturing process.

[Embodiment of the Invention] Next, an embodiment of the present invention will be described.As mentioned above, the purpose of the present invention is to completely perform junction separation.
I will discuss this point in detail.

First, Figures 2(a) and (b) are a substrate (211I - other conductivity types are as shown in Figure 2(a). A diffusion source is applied to one surface of the lζ substrate, and then baked. A case where two substrates are brought into contact with their back surfaces and the diffusion layer is removed, or a case where the back diffusion layer of FIG. As shown in Figure 2(a), (
b) In both cases, the diffusion layer on the end face is removed to form the final electrode (4
)) Complete the solar cell with. At this time, since the electrodes (next to the electrodes) are taken from the pnn one after another part of the pn junction, it is necessary to separate the front side and the back side of the junction. In this junction separation, I'i
The method shown in FIGS. 3 and 81 is commonly used.

That is, FIG. 3 shows a method in which silver is formed into poles (turns) by a printing method as shown in (3)(a), and then the end surface is shaved as shown in FIG. 3(b).

Figure 4 shows the case where an electrode is used by the plating method, and as shown in Figure 1(a), an electrode μ5) consisting of a plating layer is formed on the unfinished surface of the patterned resist example. (b) after removing the resist.
As shown in FIG. 1, 9iiV 111 is removed along with the flimsy layer formed thereon. Figures 3 and 4
For fall removal of the edge τ and jl in the figure, mechanical methods such as using a stone or sandblasting are generally used, but plasma dry etching for silicon etching used in the semiconductor industry is also used in some cases. There is. However, in this case, the etching force of the plating layer is limited, so the process using printed electrodes and the process C1 for converting the state shown in FIG. 2(a) to the state 1 shown in FIG. 2(b) are limited. There is.

On the other hand, in the present invention, in order to perform junction separation using plasma dry etching f2 with a high yield, the dry etching conditions are considered and the etching shape of the peripheral area is devised.
In addition, by devising the formation of the plating resist and finding the optimal conditions, we have made it possible to perform high-productivity plasma dry etching end face cleaning in the process using plating@electrodes. Now, the relationship between the state of the dry etched surface and the state of resist coating will be explained.

First, after forming another isoelectric type impurity diffusion layer (reflection) on the substrate (8j), a plating resist B; Mj is formed, resulting in state C2 in FIG. 5(a).This plating resist (
Cut (keep the exposed part (331) of the two-way joint (8B) ii
p; In order to do this, as shown in Fig. 2(b), a slope including an exposed part (331) in the entire shell area near the outer periphery (forming a garden, and this child ρ
The main idea is to form the f-2 plating resist bullet 9 so as to include at least the exposed portion (331) between the slopes.

By forming the plating resist...) on the inclined surface □ including the cNN groups 331), it is possible to print the plating resist g34), etc.; +: The exposed part (331) of the joint (Sa) is maintained even if there is any cracking during the baking process as shown in (d) of the same figure. Shattered.

In this case, as shown in FIG.
It becomes difficult for people to be accepted. Furthermore, as shown in Figure (7), if the slope is made gentler, the effective area that contributes to photoelectric conversion decreases, and the area around the edge (the boundary between 351 and the iron surface or the wavy J
:Ill, my outside judgment will get worse. It was also found that the #'f 81Mt field of both of these phenomena is sensitive to the gas pressure during etching.

Since the etching is carried out only on the area near the outer periphery, that is, on the end face, the C substrate (31) is stacked in the etching chamber as shown in Fig. 6. The board within (
8J) does not move. When etching is performed, the substrate (8) is etched as shown in FIG. 7, 12. The substrates (3ia) and (31b) of this combination ψt1 are dummy, but the surface is made of a material that is difficult to be etched □□□)
It is unpleasant to keep it coated.

That is, the etching radicals are not consumed in the etching i2 of the large area portion of the surface, but act effectively f2 on the s\M plane, thereby shortening the etching time. For example, when using a composition mainly composed of CF4 mixed with several acids of acid as the etching gas, it is preferable to form a photoresist or a silicon 9ide film as the etching-resistant material ta5+.

Control of the etching shape depends largely on the gas pressure, and if there is almost no inclination as shown in FIG. 5(e), the etching shape will be 0. Comparison of less than ITorr (+: + Two cases occur when the soldiers' prospects are good, and the slope as shown in Figure 5 (J) becomes significantly large, but it is more than 3 'l'o r r, The most preferable gradient 1 is in the range of 0.1 to 3 Torr.
” was found to be.

In order to further reduce the waving phenomenon and eliminate etching unevenness, f2 is set between the laminated substrates (8J) as shown in FIG.
Insert a spacer (36) of several microns to several tens of microns.
For example, it is preferable to apply BSF on one side of the substrate due to the process.
A fired layer of aluminum paste provided in the forming C may be used.

A plating resist mask is formed on top of the etching described above. This mask uses a simple printing method, and the plating resist includes resin, vegetable oil derivative, thickener,
A conventional material containing a solvent as a component can be used, and printing may be carried out along the outer periphery of the substrate, or over a slightly wider area. The key is to sufficiently preserve the exposed portion of the joint.

Next, an embodiment of the method for manufacturing a hot water battery according to the present invention will be described with reference to FIG.

First, as shown in the same figure (a), the direction [100] thickness 37
A p-type silicon single crystal substrate t411 with a diameter of 4 inches is prepared using the CZ method with a resistivity of 0μ and a resistivity of 1Ω·α.

Next, this p-type silicon single crystal substrate...) was heated to 20% ta.
Etching was performed for 8 minutes in a boiling aOH aqueous solution of m- to reduce the thickness of the substrate (...) and remove the damaged layer on the surface. After that, after washing with hot water and water, 2% NaOH
A mixture of an aqueous solution and Inglobil alcohol (4:1c) was allowed to rise, and etching was performed therein. As a result, the f2 anisotropic etching surface (41
1) is formed and the thickness of the substrate (for the substrate) is also reduced by 290 μm. This reaction was also stopped using boiling water C2, and then
Rinse with water for 5 minutes. Next, surface 1: In order to neutralize the remaining alkaline components, immerse in a 10% HcJ aqueous solution for 3 minutes, then rinse again with water for 15 minutes. After drying thoroughly, μs element and oxygen are mixed in a diffusion furnace. Carrier gas (second POc
Using J3 as a source, phosphorus is diffused. The furnace temperature at this time should be 875°C, and the deposition should be carried out for 20 minutes.
From the second step, as shown in FIG. 11 (C), an n-layer light layer is formed via a 1U junction (6) with a junction depth of 0.3μ.

However, the anisotropically etched surface (411) will be omitted below.

Next, as shown in FIG. 11(d), a aluminum paste (trade name: Engelbar A-3484) is formed on the entire surface by screen printing. Next 200℃
After drying for 30 minutes, it is fired for a short time in a conveyor-type firing furnace equipped with a near-infrared lamp.

Maximum temperature 750℃ for 10 seconds, room temperature to lowest temperature 5
A with a steep rise in temperature of 1 minute, and after holding at the maximum temperature for 10 seconds, returning to room temperature 1-1 for 10 minutes.
i) Bake the paste. The atmosphere for this mating may be air. Through this structuring, the C2ht atoms in the silicon are diffused and an alloy layer (p"l・Hinoki (8)) is formed. Next, plasma etching is performed to form the peripheral part (2 formed n+Jd f44i). At this time, the substrates are screwed together and attached as shown in Figure 8(b) in the vacuum 4'11C'', and after the pressure is reduced with a rotary pump, EP4 gas containing 5% oxygen is etched. 0.5 Torr2t
When etching is performed for 15 minutes by applying 600 W of RF power to generate plasma and etching for 15 minutes, the n layer M around the substrate g13 and the silicon near both ends are etched, resulting in an inclined surface 1i171 as shown in FIG. 9(e). (for the board that cures)
is formed, and the joint portion 1 of the front and back surfaces is made.

Next, remove the silicon and aluminum oxide films on the surface by 10%.
The sample was removed by lightly etching it with hydrofluoric acid for 15 seconds, washed with water for 15 minutes, and dried. Next, as shown in Figure 9) C1, (Niacryl (Plating resist made of ☆ J fat, other oil derivatives, thickener, organic solvent) 118) was formed to a minimum gauze width of 180μ by screen printing, 130
When heated at ℃ for 30 minutes to solidify, the minimum line width is 15
It becomes 0μ. Then 10% hydrofluoric acid treatment x1! After that, the commonly known Ni electroless plating was performed at pH 6.5 and 65°C for 20 minutes to form two Ni layers (9) on both sides of the coating.
Form an electrode base.

Next, in the same figure (f), after removing the plating resist @8 by curing C142cJ2+ as shown in the figure, heating it at 200℃ for 30 minutes to strengthen the adhesion, and dipping the board in soldering flux for 150℃. ℃ and heat for 10 minutes. Next 22
Pb and Sn containing 2 molten At heated to 0℃
6-3 Immerse it in solder C2 for about 3 seconds and pull it out, and two solder layers (5υ) are formed on both sides of M layers. fire t
Surface C1 Remaining flux for half Bj was removed by Freon cleaning, and copper C2 solder plated lead wire 1
) to complete the solar cell.

Furthermore, the solar cells manufactured by C2 are AM (Ai
rMass) 1,5, incident power 100mw/C
As a result of measuring the characteristics of the solar simulator (-) under the conditions of J, the conversion efficiency was 15%, which is higher than the conventional 4'i
*Compared to the IL polar element using the in-l junction separation method, the characteristics have been improved by one side.This is because the junction separation according to the present invention completely covers the plating resist. By introducing a highly productive process using plasma, the process can be shortened and productivity increased! - It can be seen that this is an excellent manufacturing method.

In this Example 11, a double-crystalline silicon substrate was used as the substrate C, but it goes without saying that the same method can also be applied to a polycrystalline silicon substrate or a substrate on which an anti-reflection film is formed.

[Effects of the Invention] As mentioned above (according to the method for manufacturing a solar cell of the present invention),
It is possible to realize mass-producible, low-cost solar cells with excellent (, -j condylar co-τ-).

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional view showing the structure of a conventional solar cell, Figure 2
Figures to Figure 8 are diagrams showing the main steps of the present invention, and the second
Figures (a) and (b) are explanatory cross-sectional views showing different examples in which impurity diffusion layers are formed on silicon substrates having -type 1 frost conduction, and Figure 2 (c) is an explanatory cross-sectional view of the completed solar electrode. Cross-sectional views, WJa figures (a) and (b) are explanatory cross-sectional views in which the electrodes are formed by the printing method and then the end faces are scraped off in order. Figures 4 (a) and (b) are the electrodes formed by the H plating method. 5 is an explanatory cross-sectional view showing the step of scraping off the end surface after forming, and FIG. 5 is a diagram showing the relationship between trial etching and plating resist, and FIG. 5(a) is a diagram of the substrate without dry etching. An explanatory cross-sectional view showing the relationship between the impurity diffusion layer and the plating resist, FIG. 5(b) is an explanatory cross-sectional view showing the ideal shape of the plating resist formed by dry etching, and FIG. 5(C) is an explanatory cross-sectional view showing the relationship between the impurity diffusion layer and the plating resist. An explanatory cross-sectional view showing the shrinkage of the plating resist, FIG. 5(d) An explanatory cross-sectional view showing the sagging of the FD plating resist, FIGS. A sectional view showing the
Figures 6 to 8 are diagrams showing a dry etching method using IYt stacking of substrates. Figure 6 is an explanatory diagram showing an example of a state in which the substrates are stacked, and Figure 7 is a diagram showing an example of stacked substrates. Explanatory diagram showing the state in which dry etching is performed, No. 8
The figure is an explanatory view showing a state in which a spacer is inserted between substrates and dry etching is performed, and FIG. 9 is an explanatory cross-sectional view showing an embodiment of the method for manufacturing a solar rectangle according to the present invention in the order of steps. 1, 21.31.31a, aib, 41 one board 2
, 22.32.42... n+ layer 24, 34.48... plating resist 35.47.
・・Slanted surface 45 ・Aluminum paste 49 ・・
・Nickel layer 50...Solder layer 51...Lead wire agent Patent attorney Mr. Inoue Figure 5 Figure 6 Figure 7 Figure 8

Claims (6)

[Claims] (1) A method for manufacturing a solar cell in which at least a part of the electrode is formed by electroless plating method C2, comprising: - forming an impurity diffusion layer of another conductivity type from one surface of a silicon substrate having one conductivity type; , a step of forming an inclined surface on which a bonding portion between the silicon substrate and the impurity diffusion layer is exposed in a region near the outer periphery of the silicon substrate by etching, and etching the impurity diffusion layer so that the exposed bonding portion is also etched. A method for manufacturing a solar cell, comprising: forming a plating resist thereon. (2) Method 0 for manufacturing a solar cell according to step 1 of the claims, characterized in that the etching is performed by plasma etching method C2 using fluorocarbon gas added with an acid system. (3) Pressure of freon gas added with oxygen is 0.1-3T
Method 0 for manufacturing a solar cell according to claim 2, characterized in that orr. (4) The method for manufacturing a thick@battery according to claim 1, wherein the etching is performed in an etching container by closely stacking a plurality of silicon substrates. (5) The method for manufacturing a solar cell according to claim 1, wherein the etching is performed by forming a desired portion≦2 coatings on at least one surface of the silicon substrate. (6) The method for manufacturing a solar cell according to claim 5, wherein the coating is formed by a printing method. 5. The method of manufacturing a solar cell according to claim 4, wherein (γ) the outer surface of both ends of the laminated silicon substrate is coated with a material having an etching rate lower than that of C-silicon.