JPS6042976B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention connects an input/output control device and a storage device to a set of input/output buses connected to a central control device, and communicates between the input/output control device and the storage device. large amount of data transfer,
The present invention relates to a data processing device that can be controlled by the central control device.

Data is transferred between the input/output device and the main memory during data processing, but when storing a large amount of external data in the main memory, the capacity of the main memory is Restrictions (In the case of 16 bits, you can only access up to 64KW (words).

) (2) The capacity of the main storage device is limited due to physical limitations of the interface between the main storage device and the central control device.

Therefore, instead of the main storage device, an external storage device such as a porcelain drum is connected to the input/output bus to transfer data between the input/output device 1 such as the porcelain drum and other general input/output devices 2. There is. In this case, (1) the response time will be slow; (2) if data is transferred between I/O device 1 and I/O device 2 without going through the main memory or central control device, both control devices will (3) Through the main memory and the central control unit, the input/output device 1 - the central control unit - the main memory and the main memory - the central control unit -
For each data transfer of I/O device 2, two I/O commands are required when relaying the main storage device, and considering the data preparation before issuing the I/O command, I/O device 1 and I/O device 2 are required. The data transfer speed between
There were other drawbacks.

An object of the present invention is to connect a plurality of memory devices each having a memory element similar to the memory element of the main memory device to an input/output bus;
An object of the present invention is to provide a data processing device that has a large storage capacity, can be executed with one input/output command, and has a high data transfer speed by transferring data between an input/output device and a storage device without going through a main storage device.

In other words, the storage capacity is multiplied by the number of storage devices that can be connected to the input/output bus.

For example, in the case of 10 addresses 8 bits, the number of storage devices that can be connected to the input/output bus is 255, and the data width is 1
If it is 6 bits, a storage capacity of 16 MW (64 kW x 255 units) can be obtained. Therefore, it is possible to greatly overcome the limitations of storage capacity due to physical limitations on data width and interfaces. Furthermore, since data transfer between the input/output device and the storage device is performed with one input/output instruction without going through the main storage device, the transfer speed is increased. Furthermore, since the response time of the storage device is faster in data transfer between an input/output device and a storage device than in data transfer between an input/output device and an input/output device, the latter has a higher transfer speed. Furthermore, data transfer between input/output devices and storage devices is carried out under the control of the central control unit using registers, arithmetic circuits, and other circuits of the central control unit. The amount of gold can be reduced. According to the data processing device of the present invention, the main memory device MM;
A central control device with a built-in channel function, an input/output device, and an input/output control device that controls data transfer of the input/output device,
It is composed of a plurality of storage devices 10M made of memory elements similar to those of the main storage device, and an input/output bus connecting the central control device, input/output control device, and storage devices.

In a channel control word that controls data transfer stored in the main memory, information is provided to identify whether the data is being transferred between the input/output control device and the main memory MM or the memory 10M. Data transfer between the main memory device and the input/output control device is performed by the control device via the input/output bus according to the channel control word in the main memory device MM.

Data transfer between the input/output control device and the storage device 10M is
Based on the identification information in the channel control word, the central controller learns that the destination of the input/output controller's transfer is not the main memory MM but the storage device 10M, and the central controller transfers data via the main memory MM. Rather, data transfer between the central controller and the input/output controller and within the central controller and the storage device 10M is performed, that is, via the central controller, so that the data transfer between the central controller and the input/output controller 10C and the storage device 10M is performed. Data transfer between can be executed with one instruction. Furthermore, in the case of data transfer from the storage device 10M to the input/output control device, the following three methods can be used.

(1) When the central control unit learns that the data transfer is from the storage device 10M, it issues a command to the input/output control device to temporarily suspend the data transfer signal from the storage device 10M, and at the same time A command to read data from 10M is issued to the storage device.

When the input/output control device receives the suspension command from the central control device, it prohibits outputting the data transfer signal onto the input/output bus. When the central control unit receives data from the storage device 10M, it releases the data transfer signal transmission hold for the input/output control device, sends the data received from the storage device 10M to the input/output control device, and sends the data to the input/output control device. receives the data. The above procedure enables data transfer from the storage device 10M to the input/output control device. (2) When the central controller learns that the data is to be transferred from the storage device 10M, the central controller issues a command to read data into the storage device 10M.

The storage device 10M receives this and sends back the data using a data transfer signal for the storage device 10M. The central controller receives this data and sends it to the I/O controller, which in turn receives the data. The above procedure enables data transfer from the storage device 10M to the input/output control device. (3) When the central controller activates the input/output controller, if it identifies that the data transfer destination of the input/output controller is the storage device 10M, it immediately receives data from the storage device 10M and stores it within the central controller. Data is stored in the input/output controller buffer register of , and when there is a transfer request from the input/output controller, the already stored data is transferred to the input/output controller, and then the data is transferred to the storage device 10M. Read in order to pre-fetch the next data.

The above procedure enables data transfer from the storage device 0M to the input/output control device. Next, an embodiment of a data processing apparatus according to the present invention will be described with reference to the drawings.

The main storage device M■ is connected to the central control unit CC2 through a memory bus (having a data bus, an address bus, and a control bus), and is connected to the central control unit CC2 through an input/output bus IOB3 (a data bus, (with address bus and control bus) are connected. Input/output bus IOB3
n input/output control devices 10Ci4 (1 indicates any number from 1 to n) are connected to the input/output control devices 1
An input/output device 1Q5 whose data transfer is controlled by these is connected to 0C and 4, respectively. Input/output bus IOB3
is further connected to m storage devices 10M, 6 (j indicates any number from 1 to m), and unlike so-called large-capacity external storage devices such as magnetic drums, this storage device 10Mj has a high capacity. The main memory MMl is designed to operate at high speed.
It is composed of a memory element similar to the memory element of . 1st
As shown in the figure, a main storage device 1 is included in a part of the central control device 2.
A main memory control unit MMCO is provided for exchanging data with. The input/output control device 10q includes a bus interface section 10BCi and a device interface section 10DCI that are connected to each other.
0Bq is connected to the input/output bus 10B, and the device interface section 10DCI is connected to the input/output device 101. The storage device 10M is a normal storage device unit 10MUj and 1
0B, and an interface section 10MC.

The storage unit 10MUj is, for example, as shown in the document DlO type automatic switchboard, Part 4, Central control unit and main storage device (edited by Tamoto Telegraph and Telephone Public Corporation, Telecommunications Mutual Aid Association, published on April 5, 1939), at the top of 21. Any ordinary storage device can be used. The IOB interface section 10MC has a bus interface section 10Bq and a storage interface section M connected to each other.
The bus interface unit 10Bq is connected to the bus IOB and has the same configuration as the bus interface unit 10Bq in the input/output control unit 10q, and the storage interface unit MMC is connected to the storage device 0M. , has the same configuration as the main memory control unit MMCO of the central control unit CC. Although data transfer between each device has been specifically explained, the configuration and operation of the present invention will be explained. First, the principle of an addressing method that overcomes the limitations of storage capacity due to physical limitations on data width and interfaces will be explained below. In order to expand the main memory capacity, the present invention extends the main memory device MM to the input/output bus IOB3.
are connected.

In this case, if n=255, the address capacity (space) is, referring to FIG. 26, up to 64KW for the main memory device MM, up to 128KW (64KW×2) for the storage device 10M1, and 16MW for the storage device 10M255. In the address space configured in this way, a case will be described in which an arbitrary address Aj within 0 to 16 MW is specified.

Now, if the address Aj is equal to or smaller than 64KW, it is specified in the main memory device MM as shown in FIG. Can be specified.

Next, when the address Aj is larger than 64KW and equal to or smaller than 16MW, the address Aj can be expressed as.

Here, j is the device address of the storage device 10M, and αj is an address within the storage device 10M. That is, the address Aj specifies the storage device 10Mi and the storage device 10M,
It is determined by the address αj within.

Next, the method of specifying these will be explained. In FIG. 1, in order to specify the storage device 10Mj and its internal address αj from the central controller CC2, information is sent from the central controller QC2 onto the input/output bus 0B3 in accordance with the procedure shown in FIG. 17, which will be described later. That is, the memory device 10M,
An internal device address αj can be specified on the address DATAOUT (16 bits). Note that ■0A0UT is 8 bits, so storage device 10M, address 0-255, D
ATAOUT is 16 bits and is the internal address αj of the device.
is 0 to 64KW.

Furthermore, although the read operation from the storage device 10M has been explained here with reference to FIG. 17, the write operation (first
The same applies to the case shown in Fig. 5).

Furthermore, since all IOCs on IOB3 and IOM6 are specified by IOAOUT8 bits, the following is obtained.

As shown in FIG. 1, the management of the 64KW address in the storage device 10M is performed by the storage interface section MMq at the end of the IOB interface section 10Mq.

This is because the central controller CC2 has 64KW of main memory MM.
This is exactly the same as the management of MMCO being performed by the main memory unit MMCO. Next, a normal data transfer procedure between the input/output control device 10q and the main memory device MM will be described.

Data transfer is typically divided into three phases: startup, transfer, and termination. The data transfer procedure on the input/output bus 3 between the central control unit 2 and the input/output control unit 10q at the time of startup is as shown in FIG. That is, the central control device specifies the address of the input/output device (hereinafter referred to as 10A) to the input/output control device 10C using an input/output device address signal (hereinafter referred to as 10A0UT signal), and sends a command command signal (hereinafter referred to as CNTOUT signal). When the data transfer signal (hereinafter referred to as the SRVOUT signal) is activated (in the case of activation, a write instruction is specified) and a data transfer signal (hereinafter referred to as the SRVOUT signal) is sent, the input/output control side checks the address of the input/output device. If they match, it knows that it is an access to its own input/output control device, reads the command command CNTOUT signal, and inputs its own device address IOA with the IOAIN signal to indicate the state of the input/output device (hereinafter referred to as DST). ) is a data transfer signal (hereinafter referred to as SRVIN signal) from the input/output control device that indicates that the command has been executed by the DATAOUT signal.
The startup procedure is terminated with each notification. This channel function of the central controller is controlled by a microprogram.

FIG. 8 shows the microprogram flow. That is,
When a program issues a data transfer command (hereinafter referred to as a CHC command), in order to know which input/output device should be activated in the microprogram, the channel control word CCW prepared in advance by the program is changed to the channel address word CAW.
Bring it from (801). Channel address word CAW
is located in the system area of the main memory device MM as shown in FIG. 2, and indicates the address where the channel control word CCW is stored. The channel control word CCW is composed of three words CCWO to CCW2 as shown in FIG.
The input/output device address IOA is used to specify the other party for data transfer, and the command code CM is used to specify the transfer direction (read/write), etc.
In C, the number of words to be transferred is indicated by a word counter WC, and the transfer start address is indicated by a data address DA. A channel word CHW is created from this channel control word CCW as shown in FIG. 8 (802).

The channel word QHW is stored in the system area of the main memory MM at the input/output device address 10A as shown in FIG.
It is fixedly assigned. Once this channel word CHW is created, if there is a data transfer request from an input/output device, the channel code can be easily found from the address IOA and the transfer can be controlled. As shown in Figure 4, the channel word CHW is composed of three words CHWO to CHW2, number of transfer words WCl transfer data address DAl transfer direction (read/write) R/W1 channel status CS
It is made up of T etc. Next, in FIG. 8, the IOAOUT signal is transferred from the input/output device address IOA to the transfer direction R/W.
The data transfer SRVOUT signal is sent to the input/output control device by setting the DATAOUT signal and the command cold CNTOUT signal due to activation (80
3). As a result, the startup procedure is started, as is clear from FIG. Next, the input/output control device returns the status DST of the input/output device in the DATAIN signal.

The microprogram checks its state DST and the channel's state CST (804). If the result is good, the condition code CDC is set to O to indicate that the activation was valid. (805). of this code”
The CDC consists of 2 bits, can be viewed from the program, and is also used to determine whether input/output device instructions have been executed normally. If there is an error indication in the input/output device status CST or the channel status DST, its contents are stored in the channel status word CSW (CSWAl at startup, CSWB at termination) (806)
. As is clear from FIG. 2, channel status word CSWA is fixedly allocated to the system area of main memory MM. As shown in FIG. 5, the structure of the channel status word CSWA is made up of channel status CST, input/output device status DST1, input/output device status DST1, and input/output device address IOA. Channel status word CS
After storing it in WA, the condition code CDC is set to 2 (807). Next, the data transfer procedure on the input/output bus IOB between the central control unit and the input/output control unit 10Ci during transfer is as shown in FIG. That is, when the data transfer request REQIN signal is sent from the input/output control device 10q side, the central control device side receives the data transfer request reception RE.
Issue QOUT signal. The input/output control device side is configured by a priority circuit so that only the input/output control device issuing the data transfer request REQIN signal on the input/output bus can receive this signal. The input/output control device that received the transfer acceptance REQOUT signal transfers its own address IOA to IO.
When transferring data from the input/output control device to the main storage device, read data is set in the AIN signal and the DATAIN signal, respectively, and a data transfer SRVIN signal is sent to the central control device side. The central controller side receives this SR ■ prisoner signal and sets the address of the transfer destination in the IOAOUT signal,
In the case of data transfer from the main memory device to the input/output control device, the contents of the main memory device MM specified by the channel word CHW are set in the one-word DATAOUT signal, and the data transfer S
The data transfer procedure ends by sending the RVOUT signal.
This channel function of the central controller is controlled by a microprogram.

FIG. 10 shows the microprogram flow. That is, when a data transfer request REQIN signal is sent from the input/output control device side, the central control device side is interrupted and starts processing the microprogram transfer procedure, and at the same time, the hardware control returns a transfer request acceptance REQOUT signal. Transfer request RE
When the input/output control device that issued the QIN signal receives this signal, it sets its own address to the IOAIN signal and, when reading data, sets the read data to the DATAIN signal and transfers it. Send RVIN signal. This S on the central controller side
When the RVIN signal is received, the input/output device address 10A is learned from the IOAIN signal (1001), and the channel word CHW corresponding to that address IOA is stored in the main memory MM.
The data is read from the system area (1002). It is determined from the word counter WC of the channel word CHW whether it is the final transfer (if WC = 1, it is the final transfer) (100
3) If you want to continue the transfer, proceed to the data transfer process (
1004). In this process, the address IOA of the transfer destination is changed from the IOAIN signal to the IOAOUT signal, and when writing data, the address IOA of the transfer destination is transferred to the main memory MM according to the specification of the channel color HW.
Set the contents of each to the one-word DATAOUT signal,
Send data transfer SRVOUT signal. If it is determined that the transfer is the final transfer, the central control unit sets the command command CNTOUT to 111 to instruct the input/output control unit to terminate (1009), and performs the above transfer process (1004). Move.

When the transfer process (1004) is completed, the transfer start address DA
is +1 (1005), word counter WC is -1 (
1006), the result is stored in the channel word C of the main memory MM.
It is stored in the HW area (1007).

Next, if the transfer request REQIN signal is not issued, the transfer procedure ends. If the REQIN signal is output (in the case of burst mode), the transfer sequence is repeated again.
(1008). Next, FIG. 11 shows the data transfer procedure on the input/output bus IOB between the input/output control unit and the central control unit at the time of termination.

That is, when the termination request signal STPIN is sent from the input/output control device side, the termination request acceptance signal S is sent from the central control device side.
Issue TPOUT. The input/output side control device side is configured by a priority circuit so that only the input/output control device issuing the termination request STPIN signal on the input/output bus can receive this STPOUT signal. The input/output control device that receives the STPOUT signal sets its own address as the IOAIN signal.
Set the device status DST to the DATAIN signal and transfer the data? Send the RVIN signal to the central controller side.
The central controller side receives the SRVIN signal and sends the IOAIN signal.
The termination procedure is completed by setting the signal to the IOAO signal and sending the SRVOUT signal. This channel function of the central controller is controlled by a microprogram. 12th
The figure shows the microprogram flow. That is, when the termination request STPIN signal is sent from the input/output control device side, the central control device side is interrupted and starts microprogram termination sequence processing, and at the same time, the hardware control returns the termination request acceptance STPOUT signal. When the input/output control device that issued the termination request STP signal receives this signal, it sets its own address to the IOAIN signal and the status DST of the input/output/output device to the DATAIN signal, and transfers the data? RVI
Send N signal. Is this the central control unit? When receiving the RVIN signal, it learns the input/output device address from the IOAIN signal (1201), and reads out the channel word CHW corresponding to that address from the system area of the main memory MM (1202). A termination indication is set in the condition code CST of the channel word CHW and stored in the system area of the main memory MM (1203). Next, the contents of condition code CST1 status DST (DST is D
The contents of ATAIN) are stored in the channel status words CSWBO, CSWBl (see FIG. 2) in the system area. The contents of channel status words CSWBO and CSWBl consist of CST, IOA and DST as shown in FIG. Finally, the interrupt source ISl4 is set to complete the termination procedure. When interrupt source 1S14 is set, it interrupts the program and the program knows that the data transfer operation is complete. The activation, transfer, and termination procedures described above are already well known as data transfer procedures.

Next, according to the present invention, the storage device 10 connected to the input/output control device 10C, which is a main part of the data processing device, and the input/output bus.
Data transfer to and from M will be described. This IOC-1
In order to enable data transfer between 0M and 0M, one part is added to the configuration of the conventional channel control word CCWl channel word CI (W), and the input/output control device 10C is changed as shown by the bold frame in FIGS. Identification information indicating whether the transfer destination is the main storage device MM or the storage device 10M is attached.

That is, the channel control word CCW has an IOM bit in the most significant bit of CCWl, and when 10M=1, IOC-10
M transfer is assumed, and when IOM=0, IOC-MM transfer is assumed. Furthermore, CCW3 is newly added and IOM-10A
will be established. IOM-10A of CCW3 when IOM=1
Let be the device address of the storage device 10M. The channel word CHW is also changed according to the channel control word CCW. That is, the IOM bit is provided in the second bit from the top of CHWO, and
When OM=1, it is IOC-10M transfer, when IOM=0, it is 10C-MM transfer, and IOM●IOA is provided in the upper 8 bits of ClIW2, and when IOM=1, IOM
●10A is the device address of the storage device 10M. Since the channel control word CCWl channel word CHW is structured like this, is it possible to change the data in the program? When an HC instruction is issued, the IOC-MM is
It is easily determined whether the data transfer is the data transfer of the IOC-10M or the data transfer of the IOC-10M. And when IOM=1, of course the device address IOM-■0A of the storage device 10M to be transferred is IOC-
This becomes more necessary than data transfer between MMs.
Next, data transfer from the input/output device Kq to the storage device 10MJ will be explained in detail.

The microprogram control flow for the startup procedure at startup and the data transfer procedure on the input/output bus is the same as in FIGS. 8 and 9. That is, the channel address word CA
Read channel control CCW from W, channel word CHW
Create a command, send a command to the input/output control device 1α, and send a condition code CD to the program.
Return C. The data transfer procedure on the input/output bus during transfer is as shown in FIG. 15, and the microprogram control flow of the transfer procedure is shown in FIG. That is, from the address IOA received from the input/output control device 10q (1
601), read the corresponding channel word CHW (1602)
If the IOM bit in the CHWO is 1 (1603
), IOM・FLAG=1 (1614), CHW
When the most significant bit R/W of O is designated for writing (1604), write processing is performed (1615) (described later), and when it is designated for reading, the word counter W is
It is checked whether C is 1 or not (1605), and if it is 1, it is the final transfer data, so the command CNTOUT is given a termination instruction and the process proceeds to data transfer read processing (1615).

In the data transfer read process, the read data from the input/output control device 10C1 is received from the DATAIN signal, the address IOA of the input/output control device 10q is set to the IOAOUT signal, and the transfer SRVOUT signal is issued (1606). Add 1 to transfer start address DA of CHWl
Then, the word counter WC of CHWO is decremented by 1 and stored in the channel word CHW fixed area of the main memory MM (1607) to (1609).

Finally, the data read from the input/output control device 10C is written to the storage device 10M. For this reason, first address IOAO
Set the UT signal to the IOM address, set the write address to the DATAOUT signal, and issue the command command CNTO.
Sends the transfer JSRVOUT signal with the UT signal as a write designation. After that, the same IO is sent to the address IOAOUT signal.
The data read from IOq is set in the M address and the DATAOUT signal, respectively, and the transfer SRVOUT signal is sent out again (1611), and the sending procedure ends. Finally, at the time of termination, the data transfer procedure of the input/output bus and the startup procedure microprogram control flow are the same as at the time of startup.
Similar to Figures 1 and 12. In this way, 10q−+
IOM, data transfer becomes possible. Next, the storage device 10
The data transfer from M, to the input/output control device 10Ci will be explained in detail. This may be the case (1) to (3) above, and the case (1) will be described first. At startup, the data transfer procedure on the input/output bus, the startup procedure, and the microprogram control flow are the same as in the case of normal transfer, as shown in FIGS. 7 and 8. At the time of transfer, the data transfer procedure and transfer procedure microprogram control flow are shown in FIGS. 16 and 18, respectively. That is, in determination 1604 in FIG.
,→IOq, the process moves to write processing (1615) in FIG. 16. In this writing process, the 18th
As shown in the figure, the SRV is transferred to the input/output control device 10q.
Command command CNTOUT (=0
11), set the address of the input/output control device to address IOA
The transfer SR 0UT signal is sent by setting each to the OUT signal (1803). When the input/output control device 10Ci side receives the reservation designation, it issues a command command C as shown in FIG.
NTOUT is decoded, its output sets the holding flip-flop 12, and its output is controlled by the inhibit gate 13 to be turned on? ? The output of RVIN signal generation circuit 14 is prohibited from being supplied to HIB bus 15, and therefore the SRVIN signal is prohibited from appearing on the input/output bus. Next, the central controller sets the address of the storage device 10M to the address IOAIN signal, the read address in the storage device 10M to the DATAOUT signal, and the read designation to the command CNTOUT signal, and then sends the storage device 10M to the address IOAIN signal.
A transfer SRVOUT signal is sent to M (1804).

The storage device 10Mj receives this signal, sets its own address in the IOAIN signal, sets the read data in the DATAIN signal, and sends back the sent SRVIN signal. Furthermore, if it is determined from the word counter WC that it is not the final transfer (1805), the data (DATAIN) just read from the storage device 10M is set to the DATAOUT signal for the input/output control device 10Ci, and a write operation is executed (
1806).

At this time, the command command CNTOUT is set to 101 to issue a command to release the temporary hold on the input/output control device side. If the judgment result of the word counter WC is the final transfer, the command command CNTOU instructs the termination at the time of the above writing specification.
Specify with T signal (1814). Next, the channel word CHW
Transfer start address DA is +1, word counter WC is -1, and stored in the fixed area of main memory MM (18
07)-(1809). On the other hand, in the case of normal IOq-MM transmission, the main memory MM specified by the channel word CHW
Reads one word of the content (1812), input/output control device 10
The data read for C is set in the DATAOUT signal and the transfer SRVOUT signal is sent out (1813).

Furthermore, the transfer start address DAl word counter WC is processed in the same way as in the case of transfer from the input/output control device 10q to the storage device 10M. With this, the transfer process ends.
At the time of termination, the data transfer procedure on the input/output bus and the termination microprogram control flow are the same as in the case of normal transfer, that is, in the case of FIGS. 11 and 12. Through the above processing, data transfer from IOM to IOq is performed. (2)
In the case of startup, the data transfer procedure on the input/output bus and the startup procedure microprogram control flow are normal transfers.
That is, it is similar to FIGS. 7 and 8.

The data transfer procedure and transfer procedure microprogram control flow at the time of transfer are shown in FIGS. 20 and 21, respectively. That is, the data transfer request REQIN signal from the input/output control device 10q enters the IOq←IOMj transfer procedure shown in FIG. move on. In the write process, in order to read data from the storage device 10Mj, the address of the storage device 10Mj is set to the IOAOUT signal, the read address is set to the DATAOUT signal, and the read specification is set to the command command CNTOUT signal, and the transfer SRV
Gives an OUT signal.

On the other hand, when the storage device 10M receives this signal, it sets the read data to the DATAIN signal and sends out the data transfer MSRVOUT signal for the storage device 10M (2103).
. When the final transfer has not been made (2104), the central control side" writes this read data to the input/output control device 10q,
Set the address of the input/output control device to the 10A0UT signal,
A transfer SRVOUT signal is output in which the write data is set to the DATAOUT signal. (2105). In the case of final transfer, the command command CNTOUT is set to 001 and the process proceeds to the above processing (2113). Also, the case of normal MM-10q data transfer instead of 10M,→IOq has already been described, so a description thereof will be omitted (2109) to (2112).

After data transfer (write designation) to the input/output control device 10C1, the transfer start address DAl word counter WC is updated, and the channel word CHW is stored in a fixed area of the main memory device MM (2106) to (2108). After the write process is completed, the process returns to FIG. 16 and the transfer procedure ends.

The termination time is the same as normal IOCi-MM data transfer. Data transfer between 10M and Iα is performed by the above procedure. In case (3), the data transfer procedure on the input/output bus at startup is shown in FIG. 22, and the startup procedure microprogram control flow is shown in FIG. 23, respectively.

That is, when CHW-10M=0, that is, when data transfer between the input/output control device 10q and the main memory device MM is specified, the transfer is exactly the same as the normal IOCi-MM transfer. When CHW-10M=1, as shown in FIG. 23, the process is exactly the same as the IOq-MM transfer (2301) to (2303) until the input/output control device 10q is activated. Next, when data is transferred from the storage device 10M to the input/output control device 10q (2304), it is necessary to read one word of data from the storage device 10Mj in advance at startup. Therefore, the address of the storage device 10M is set to the IOAOUT signal, and the address of the storage device 10M is set to the DATAOUT signal.
A reading designation is set for each CNTOUT signal, and a rolling VOUT signal is sent out (2305). Storage device 10
M, side receives this signal and reads the read data as DATAIN.
signal and sends back the transfer SRVIN signal. The central controller side reads this data and sends it to the input/output controller 10C.
Store it in the buffer register assigned to (23
06). After this, the channel word status and input/output device status are checked by CST and DST (2307
), and sets the condition code CDC according to the check result (2308) (2310).

In the event of an error, the contents of CST and DST are stored in a fixed area of the main memory MM as a channel status word CSWA (2309). The above is the operation at startup. Next, at the time of transfer, the data transfer procedure on the input/output bus and the transfer procedure microprogram control flow are shown in FIGS. 24 and 25, respectively. As is clear from the figure, when the input/output control device 10C receives a data transfer request, the data that has already been read ahead is sent to the input/output control device 10q, and then the data is transferred to the storage device 10M.
, the next data is read and stored. To explain with reference to the figure, a microprogram transfer procedure is started in response to a transfer request REQ signal from the input/output control device 10q. The central control device accepts transfer requests via hardware control.
Immediately send back the T signal. The input/output control device 10q side sets its own address in the IOAIN signal and transfers SRVIN.
give a signal. The central control unit reads the channel word CHW from the main data unit MM using the IOAIN signal (2501
), (2502), sets the data from the storage device 10M, which has already been stored in the buffer register during startup or the previous transfer procedure, to the DATAOUT signal, sets it to the address IOAOUT signal of the input/output control device 10q, SRV
Sends an OUT signal (2504). After that, the address of the storage device 10MJ is read into the IOAOUT signal, the address in the storage device 10M is read into the DATAOUT signal, the designation is set into the CNTOUT signal, and the SRVOUT signal is read.
Send a signal (2506). In response to this, storage device 1
0Mj reads one word of data from the specified address,
Set read data to the DATAIN signal, set its own address to the IOAIN signal, and send the signal to the SRV. The central control unit stores this data in a buffer register prepared for each input/output control device of the central control unit for the next transfer request (2507). In the case of final transfer (2505), the above two processes (250
6) (2507) is omitted. Next, transfer start address D
Al word counter WC is updated respectively and the channel word CH
Store W in the fixed area of main memory MM (2508
) ~ (2510). The transfer procedure is thus completed. At termination, the data transfer procedure on the I/O bus and the termination procedure microprogram control flow are the same as in the conventional 10q-MM case and are shown in FIGS. 11 and 12. Data transfer of IOMj-+IOCi is performed through the above procedure.

In the above description, the channel function built into the central controller is executed by microprogram control, but hardware control may also be used.

As explained above, by connecting the storage device 10M to the input/output bus and adding it to the information channel word indicating data transfer between the storage device 10M and the input/output control device, the storage capacity can be dramatically expanded. and enables large amounts of data to be transferred between the input/output control device and the storage device 10M,
Furthermore, transfer processing can be performed at high speed with a single instruction without going through the main memory, and the accumulation of data input from outside this data processing system can be processed at high speed, allowing the release of registers in the central control unit. By using them in common, there is no need to increase the amount of hardware in the input/output control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data processing device according to the present invention, FIG. 2 is a diagram showing a system area map in the main memory, and FIG. 3 is a channel control crystal? Figure 4 shows the configuration of CW, Figure 4 shows the configuration of channel word CHW, Figure 5 shows the configuration of channel word CHW.
The figure shows the channel status word CSWA when input/output operation starts.
6 is a diagram showing the structure of the channel status word CBWBO,l at the end of input/output operation,
Figure 7 is a diagram showing the startup procedure during MM-10q transfer, Figure 8
The figure shows the microprogram control flow of the MM-10q startup procedure, FIG. 9 shows the transfer procedure during MM-10q transfer, and FIG. 10 shows the microprogram control flow of the MM-10q transfer procedure. Figure 11 shows MM-Kq
Figure 12 is a diagram showing the termination procedure during transfer, and Figure 12 is a diagram depicting the microprogram control flow of the MM-10q termination procedure.
Figure 3 shows the channel control word CCWl during IOM-IOC transfer.
, A diagram showing the configuration of CCW3, Figure 14 is IOM-10C
FIG. 15 is a diagram showing the configuration of channel words CHWO and CHW2 during transfer. FIG. 15 is a diagram showing the transfer procedure during IOq-10Mj transfer. FIG. 16 is a diagram showing the microprogram control flow of the IOqeIOM and transfer procedure. FIG. 17 is 10M, →I
Diagram showing case (1) of transfer procedure of OC, transfer, No. 18
The figure shows the write processing microprogram control flow in case (1) of the IOMj+IOq transfer procedure, Figure 19 shows the SRVIN signal 1 time hold circuit in the input/output control device, and Figure 20 shows the IOM, → Transfer procedure for IOq transfer (2)
FIG. 21 is a diagram showing the write processing microprogram control flow in case of 10M, → IOq transfer procedure (2), FIG. 22 is a diagram showing the startup procedure of 10M, → IOC, transfer. Figure 23 is a diagram showing the IOM,→IOq startup procedure microprogram control flow, and Figure 24 is a diagram showing the IOq startup procedure microprogram control flow.
FIG. 25 is a diagram showing the microprogram control flow in the case of IOM,→10q transfer procedure (3), and FIG. 26 is the addressing method in the present invention. FIG. 2 is a diagram showing an address space for explaining. 1: Main memory, 2: Central control unit, 3: Input/output bus,
4: input/output control device, 5: input/output device, 6: storage device.

Claims (1)

[Claims] 1 Built-in main storage device, an input/output device, an input/output control device that controls data transfer to the input/output device, and a channel function that controls data transfer between the main control device and the input/output control device. a first bus (address bus, data bus, control bus) that connects the central controller and the main memory, and a second bus (address bus, In a data processing device equipped with a data bus, a control bus),
A plurality of storage devices configured with storage elements similar to the storage elements of the main storage device are connected to the second bus, and a channel control word that controls data transfer stored in the main storage device is connected to the second bus. Identification information for data transfer between the output control device and the main storage device or data transfer between the input/output control device and the storage device is provided, and the central control device identifies the identification information and transfers the data to the input/output control device. A data processing device characterized in that data transfer to and from the storage device is executed by one instruction via a central control unit.